Patent Application
20240204011
The present disclosure relates to a field of manufacturing display panels, and more particularly, to a semiconductor device, a sensor device, and an electronic device.
With continuous development of semiconductor manufacturing technologies, computer integrated control systems have been increasingly applied to many fields. For example, diverse machines, such as intelligent vehicles, are provided with a semiconductor device to control such devices.
In conventional technologies, during processes of manufacturing semiconductors, the semiconductor devices are usually manufactured on a silicon substrate, thereby forming a silicon substrate chip which is a circuit component constituted by a semiconductor film, a conductive film, and an insulating film stacked on a silicon substrate. By integrating multiple components on a silicon substrate, a semiconductor device having a small size, a light weight, and integration can be realized. However, compared to other manufacturing material, monocrystalline silicon substrates used to form a carrier have high manufacturing cost, high integration degrees, and complicated manufacturing processes. Furthermore, demand for semiconductor devices grows increasingly, and silicon substrate material having high cost will limit supply of semiconductor devices, which is not beneficial for controlling manufacturing cost and developing a semiconductor industry. Therefore, it is necessary to find alternative material and manufacturing processes of devices to reduce manufacturing cost and improve comprehensive performance of the devices.
As such, it is necessary to provide a solution to solve conventional issues.
Regarding the technical issues:
In conventional manufacturing processes of semiconductor devices, the semiconductor devices have high manufacturing cost and complicated manufacturing processes, which is not beneficial for a large supply of semiconductor devices and development of a semiconductor industry.
To solve the above issues, embodiments of the present disclosure provide a semiconductor device, a sensor device, and an electronic device to effectively improve manufacturing processes, reduce manufacturing cost, and enhance comprehensive performance of devices.
To solve the above technical issues, the present disclosure provides a semiconductor device, comprising:
According to one embodiment of the present disclosure, along a length direction of a channel area corresponding to the first TFT and the second TFT, an average size of a plurality of particles in the active layer of the first TFT is greater than an average size of a plurality of particles in the active layer of the second TFT.
According to one embodiment of the present disclosure, the particles in the active layer of the first TFT comprise a first boundary along the first direction and a second boundary along the second direction; and
According to one embodiment of the present disclosure, the active layer of the first TFT and the active layer of the second TFT have same material, the active layer of the first TFT and the active layer of the second TFT are disposed on a same layer, a gate of the first TFT and a gate of the second TFT are disposed on a same layer, and a source/drain metal layer of the first TFT and a source/drain metal layer of the second TFT are disposed on a same layer.
According to one embodiment of the present disclosure, a gate of the first TFT is insulatedly disposed on the active layer of the first TFT, a source/drain metal layer of the first TFT is insulatedly disposed on the gate of the first TFT, the active layer of the second TFT is insulatedly disposed on the source/drain metal layer of the first TFT, and a gate of the second TFT is insulatedly disposed on the active layer of the second TFT.
According to one embodiment of the present disclosure, the first TFT comprises a low-temperature polycrystalline silicon TFT, and the second TFT comprises a metal oxide TFT;
According to one embodiment of the present disclosure, the semiconductor device comprises a gate insulating layer disposed on the gate of the first TFT and the gate of the second TFT, wherein the active layer of the second TFT is disposed on the gate insulating layer, the source/drain metal layer of the first TFT and the source/drain metal layer of the second TFT are disposed on a same layer and are disposed on the gate insulating layer.
According to one embodiment of the present disclosure, the source/drain metal layer of the second TFT is at least partly disposed on a surface of the active layer of the second TFT, and is electrically connected to the active layer of the second TFT.
According to one embodiment of the present disclosure, a type of the first TFT and a type of the second TFT are different, the second TFT is disposed on the first TFT, and the semiconductor device comprises a passivation layer disposed between the first TFT and the second TFT.
According to one embodiment of the present disclosure, the semiconductor device comprises a second gate insulating layer, a gate of the second TFT is disposed on the passivation layer, the second gate insulating layer is disposed on the passivation layer, the active layer of the second TFT is disposed on the second gate insulating layer, and the source/drain metal layer of the second TFT is disposed on the second gate insulating layer; and
wherein the source/drain metal layer of the second TFT is at least partly disposed on a surface of the active layer of the second TFT, and is electrically connected to the active layer of the second TFT.
According to one embodiment of the present disclosure, the first IC comprises any one of a gate driving IC, a logic control IC, a low-pass control IC, or a digital-to-analog converter IC, and the second IC comprises any one of a memory IC or an operational amplifier IC.
According to a second aspect of an embodiment of the present disclosure, the present disclosure further provides a sensor device, comprising a sensor area and an outer circuit area defined on a side of the sensor area;
According to one embodiment of the present disclosure, in the sensor area, the sensor device comprises:
According to one embodiment of the present disclosure, the data signal lines are electrically connected to the first IC, the second IC is electrically connected to the first IC, and the first IC is electrically connected between the sensor unit and the second IC.
According to one embodiment of the present disclosure, the first IC comprises any one of a low-pass control IC, the analog control IC, or a digital-to-analog converter IC, and the second IC comprises any one of a memory IC or an operational amplifier IC.
According to one embodiment of the present disclosure, the first IC comprises a low-pass control IC electrically connected to the data signal line, an analog control IC electrically connected to the low-pass control IC, and a digital-to-analog converter IC electrically connected to the analog control IC, the second IC comprises a memory IC, the low-pass control IC is electrically connected between the sensor unit and the analog control IC, and the digital-to-analog converter IC is electrically connected between the analog control IC and the memory IC.
According to one embodiment of the present disclosure, active layer of the first TFT comprises low-temperature polycrystalline silicon, and the active layer of the second TFT comprises a metal oxide.
According to one embodiment of the present disclosure, the first IC and the second IC are both disposed on a same side of the insulating substrate, the first sensor module is disposed on a side of the first IC away from the insulating substrate, and the first sensor module is electrically connected to the first TFT.
According to one embodiment of the present disclosure, the first IC and the second IC are both disposed on a first surface of the insulating substrate, and the first sensor module is disposed on a second surface of the insulating substrate opposite to the first surface; and
According to a third aspect of an embodiment of the present disclosure, the present disclosure provides an electronic device, comprising a semiconductor device;
Regarding the beneficial effects:
Embodiments of the present disclosure provide a semiconductor device, a sensor device, and an electronic device. The semiconductor device comprises a first integrated circuit (IC) and a second IC. The first IC comprises a first thin-film transistor (TFT) and a second TFT disposed on an insulating substrate. Mobility of a charge carrier in an active layer of the first TFT is greater than mobility of a charge carrier in an active layer of the second TFT. In the embodiments of the present disclosure, a TFT device of an IC is directly disposed on the insulating substrate, and different TFT devices have different mobilities. High-cost semiconductor material is replaced by low-cost insulating material, thereby reducing manufacturing cost and improving performance of devices.
The following description of the various embodiments is provided with reference to the accompanying drawings to demonstrate the embodiments of the present disclosure.
With the continuous improvement of digitalization and intelligence, semiconductor devices require more and more ICs. The ICs can effectively control the devices and improve performance of the devices. However, during processes of manufacturing ICs, electronic components are usually integrated on silicon wafer substrates which have high cost. Furthermore, the manufacturing processes are complicated, which is not beneficial for further improving IC technologies.
An embodiment of the present disclosure provides a semiconductor device to effectively processes of manufacturing ICs and effectively reduce manufacturing cost of the ICs.
As shown in
Specifically, in the present embodiments, the touch control display panel includes a support circuit board 100. Furthermore, a plurality of chip integrating areas 101 are defined in the support circuit board 100, and each of the chip integrating areas 101 is provided with a corresponding IC.
Please refer to a partly enlarged schematic view of
In the present embodiment, the first IC 104 and the second IC 105 may have a same function or different functions. For example, the first IC 104 is a digital control IC, and the second IC 105 is a signal control IC. A touch control display panel can be controlled and operated by the first IC 104 and the second IC 105.
Furthermore, in the first IC 104 and the second IC 105, the first IC 104 includes a first base layer 108, and the second IC 105 includes a second base layer 109. That is, a substrate used to manufacture the first IC 104 is the first base layer 108, and a substrate used to manufacture the second IC 105 is the second base layer 109.
In the present embodiment, the first base layer 108 and the second base layer 109 are insulating substrates. Preferably, the first base layer 108 and the second base layer 109 are glass substrates. By replacing conventional silicon substrates, which an IC is disposed on, with glass substrates provided by the present embodiment, manufacturing cost of the IC can be effectively reduced, and an arrangement area of the IC can be optimized.
In the present embodiment, a third IC 102 and a fourth IC 103 are further disposed in each of the chip integrating areas 101. The third IC 102 and the fourth IC 103, and the first IC 104 and the second IC 105 are disposed on different positions. For example, the third IC 102 and the fourth IC 103 are disposed in different rows of the first IC 104. The third IC 102 and the fourth IC 103 may have different functions, which can be determined according to requirements for controlling actual products.
Furthermore, each of the above ICs may include a memory IC, a logic control IC, an analog control IC, a low-pass control IC, or a digital-to-analog converter IC. Arrangements of ICs are determined according to the ICs' functions. For example, ICs having high performance, such as logic control ICs, low-pass control ICs, sensor ICs, and digital-to-analog converter ICs, are provided with corresponding TFTs having high mobility. ICs having low performance, such as memory ICs, are provided with corresponding TFTs having low mobility. Therefore, devices are ensured to work normally.
Please refer to
In the present embodiment, when the TFT disposed in the dielectric layer 110 is manufactured, each of the ICs can be provided with multiple same or different TFTs.
In following embodiments, the first IC includes multiple first TFTs 309, and the second IC includes multiple second TFTs 308. The TFTs may be individually disposed on the corresponding insulating substrate in an array manner.
Furthermore, mobility of a charge carrier in an active layer of the first TFT 309 is greater than mobility of a charge carrier in an active layer of the second TFT 308.
In the present embodiment, the first TFT and the second TFT may be disposed on a same layer, or may be stacked. A length of a channel area of the active layer of the first TFT may be greater than a length of a channel area of the active layer of the second TFT, thereby fitting devices having different sizes. This can be determined according to performance and specification of corresponding ICs, which is not described here.
Preferably, particles are formed in an active layer of different TFTs. For example, particles are formed in a channel area of an active layer. In the present embodiment, since mobility of the first TFT is greater than mobility of the second TFT, an average size of particles in the channel area of the first TFT is greater than an average size of particles in the channel area of the second TFT.
Preferably, as shown in
Furthermore, please refer to
In the present embodiment, the first IC and the second IC may also be stacked. Meanwhile, the first IC can be bonded to the second IC.
Specifically, in the present embodiment, when the first IC 104 or the second IC 105 is manufactured, a TFT is formed on the first base layer 108 or the second base layer 109, then other wiring layers are formed on the TFT, and finally each of the ICs is encapsulated.
Specifically, please refer to
Please refer to
Specifically, the sensor device includes a sensor area 23 and an outer circuit area 24 defined on a side of the sensor area 23. The sensor area 23 includes a plurality of gate signal lines 279 and a plurality of data signal lines 278. The gate signal lines 279 cross the data signal lines 278, thereby forming a plurality of intersection areas. Moreover, each of the intersection areas is provided with at least one sensor unit. In the present embodiment, the sensor unit is a first sensor module 210 which is taken as an example. The data signal lines 278 are electrically connected to the sensor module 210, and the data signal lines are electrically connected to an IC disposed in the outer circuit area 24, thereby controlling the first sensor module 210 by the IC. In the present embodiment, the semiconductor device may also be other devices which are not described here.
In the present embodiment, the outer circuit area is provided with different ICs. The ICs, such as the first IC and the second IC, are disposed on the insulating substrate. Specifically, the data signal lines 278 are electrically connected to the first IC, the second IC is electrically connected to the first IC, and the first IC is electrically connected between the first sensor module 210 and the second IC.
Different ICs can realize different control functions. In the present embodiment, the first IC may include a plurality of logic control ICs 206, a plurality of low-pass control ICs 205, a plurality of digital-to-analog converter ICs 203, and a plurality of analog control ICs 204. The second IC may include at least one of a memory IC 202 or an operation IC. Furthermore, the second IC is provided with a TFT having low mobility. A corresponding TFT disposed in the first IC is a low-temperature polycrystalline silicon TFT, and a corresponding TFT disposed in the second IC is a metal oxide TFT.
Specifically, the data signal lines 278 are electrically connected to the low-pass control ICs 205, the analog control ICs 204 are electrically connected to the low-pass control ICs 205, and the digital-to-analog converter ICs 203 are electrically connected to the analog control ICs 204. Furthermore, the low-pass control ICs 205 are electrically connected between the first sensor module 210 and the analog control ICs 204, and the digital-to-analog converter ICs 203 are electrically connected between the analog control ICs 204 and the memory ICs 202.
In the present embodiment, each of the above ICs can be manufactured by directly etching the insulating substrate. Each of the ICs is provided with a plurality of TFTs. Each of the TFTs of the ICs is manufactured according to the structure provided by the present embodiment which can effectively reduce manufacturing cost, improve manufacturing processes, and enhance working performance.
Furthermore, the sensor device is provided with a plurality of conductive wires which are arranged from the sensor area to the outer circuit area, thereby transmitting signals.
In the present embodiment, the sensor device further includes a voltage converter module and a shift register. Since the voltage converter module and the shift register need to have high performance, a plurality of TFTs of a plurality of ICs corresponding to the voltage converter module and the shift register may be low-temperature polycrystalline silicon TFTs which have high mobility. Details are not described here.
In the present embodiment, both the first IC and the second IC can be disposed on a same side of the insulating substrate. The first sensor module 240 is disposed on a side of the first IC away from the insulating substrate and is electrically connected to the first TFT of the first IC.
Furthermore, both the first IC and the second IC are disposed on a first surface of the insulating substrate, and the first sensor module is disposed on a second surface opposite to the first surface of the insulating substrate.
As shown in
The first base layer 108 is a glass layer. A light-shading layer is further disposed on the first base layer 108. A buffer layer 302 fully covers the light-shading layer. Furthermore, the first TFT 309 is further provided with a first active layer 310, a first gate insulating layer 303, a first gate 313, and a first interlayer dielectric layer 304.
In the present embodiment, the first active layer 310 is disposed on the first buffer layer 302, the first gate insulating layer 303 is disposed on the first buffer layer 302, and the first gate insulating layer 303 fully covers the first active layer 310. In addition, the first gate 313 is disposed on the first gate insulating layer 303, the first interlayer dielectric layer 304 is disposed on the first gate 313, and a first source/drain metal layer 312 is disposed on the first interlayer dielectric layer 304. The first source/drain metal layer 312 is electrically connected to the first active layer 310 by a corresponding through-hole.
Furthermore, a second buffer layer 305 is disposed on the first TFT 309. A second active layer 306 is disposed on the second buffer layer 305. A second gate 314 is disposed on the second active layer 306. A second interlayer dielectric layer 307 is disposed on the second active layer 306. A second source/drain metal layer 311 is disposed on the second interlayer dielectric layer 307. The second source/drain metal layer 311 is electrically connected to the second active layer 306 by a through-hole.
In the present embodiment, both the first TFT 309 and the second TFT can be low-temperature polycrystalline silicon TFTs, and mobility of a charge carrier in the first TFT 309 is greater than mobility of a charge carrier in the second TFT 308.
Specifically, an average size of particles of corresponding material of the channel area of the first active layer 310 is greater than an average size of particles of corresponding material of the channel area of the second active layer 306, thereby ensuring that mobility of the first TFT is greater than mobility of the second TFT. Therefore, ICs formed of different semiconductor devices have different functions, and ICs having different functions can have high performance when a high-speed signal or a low-speed signal is applied to the ICs. As such, working performance of the ICs can be improved.
In the present embodiment, in the first base layer, an orthographic projection of the first TFT 309 on the substrate does not fully overlap an orthographic projection of the second TFT 308 on the substrate.
Specifically, the semiconductor device is further provided with other components which can be electrically connected to a corresponding TFT, thereby transmitting signals. After encapsulation processes, the ICs having the insulating substrate are formed.
Furthermore, please refer to
Specifically, the first TFT 309 is disposed on a side of the second TFT 308, and the first active layer 310 of the first TFT 309 and the second active layer 306 of the second TFT 308 may be disposed on a same layer. Specifically, the first active layer 310 and the second active layer 306 both are disposed on the first buffer layer 302.
Moreover, the source/drain metal layer 312 of the first TFT 309 and the source/drain metal layer 311 of the second TFT 308 may be disposed on a same layer such as the first interlayer dielectric layer 304. In addition, the first gate 313 and the second gate 314 are disposed on a same layer. For example, the first gate 313 and the second gate 314 both are disposed on the first gate insulating layer 303.
In the present embodiment, the first TFT 309 may be electrically connected to the second TFT 308, thereby transmitting signals. In addition, the first TFT 309 and the second TFT 308 may be different TFTs having different functions. For example, mobility of a charge carrier in the first TFT 309 is greater than mobility of a charge carrier in the second TFT 308.
Specifically, the first TFT 309 and the second TFT 308 both are polycrystalline silicon TFTs.
Please refer to
Furthermore, a source/drain metal layer 510 of the first TFT 309 and a source/drain metal layer 610 of the second TFT 308 are both disposed on a passivation layer 705. In the present embodiment, an active layer 609 of the second TFT 308 is disposed on the passivation layer 705. The source/drain metal layer of the second TFT 308 at least partly covers the active layer 609, and is electrically connected to the active layer 609. For example, the source/drain metal layer 610 of the second TFT is overlappingly connected to two edges of two sides of the active layer 609. Thus, a thickness of the second TFT 308 can be further reduced, thereby reducing a thickness of panels.
Furthermore, please refer to
Moreover, a gate 620 of the second TFT 308 is disposed on the passivation layer 705. A gate insulating layer 703 is disposed on the passivation layer 705 and fully covers the gate 620. In addition, the active layer 609 is disposed on the gate insulating layer 703, and the source/drain metal layer 610 of the second TFT 308 is disposed on the gate insulating layer 703. In the present embodiment, the source/drain metal layer of the second TFT 308 at least partly covers the active layer 609 and is electrically connected to the active layer 609. For example, the source/drain metal layer 610 of the second TFT is overlappingly connected to two edges of two sides of the active layer 609, thereby making the first TFT 309 and the second TFT 308 form a stacked structure. In
Please refer to
Please refer to the structural schematic view of
The above different TFTs can be chosen according to a function of a memory IC. For example, if a corresponding IC needs a low leakage current, a metal oxide TFT can be chosen. If a corresponding IC needs a high push force, a low-temperature polycrystalline silicon TFT can be chosen. Encapsulation processes are conducted sequentially. Thus, working performance of manufactured ICs can be effectively improved.
Furthermore, please refer to
Please refer to
In the present embodiment, the second IC 604, the first IC 605, the third IC 606, and the fourth IC 607 are disposed on the first base layer 108 and are disposed on a same side of the base layer 108.
In the present embodiment, a plurality of TFTs disposed in the ICs may be stacked. Specifically, the sensor unit 603 is disposed on the buffer layer 602, and the buffer layer 602 is disposed on another IC. Therefore, the sensor unit 603 and other ICs form a stacked structure.
Please refer to
Please refer to
Please refer to
Furthermore, as shown in
Specifically, as shown in
The buffer layer 702 is disposed on the first base layer 108, and the gate insulating layer 703 is disposed on the buffer layer 702. The interlayer dielectric layer 704 is disposed on the gate insulating layer 703, and the passivation layer 705 is disposed on the interlayer dielectric layer 704. In the present embodiment, the first base layer 108 is an insulating substrate.
A plurality of TFTs are disposed in the semiconductor device and may correspond to different ICs. For example, the first IC includes a first TFT 721, the second IC includes a second TFT 722, and the third IC includes a third TFT 723. Each of the TFTs includes an active layer, a gate, and a source/drain metal layer. Specific structures are as shown in the drawings and are not described here.
In the present embodiment, the semiconductor device further includes a first sensor module 706. The first sensor module 706 is a sensor unit such as a photosensor unit. The first sensor module 706 is disposed on the passivation layer 705 and is electrically connected to the third TFT 723.
In the present embodiment, the first sensor module 706 includes a first sensor electrode 72, a second sensor electrode 73, a connector electrode layer 74, and an enhancement layer 71. Specifically, the first sensor electrode 72, the second sensor electrode 73, and the connector electrode layer 74 are stacked. The connector electrode layer 72 is disposed on the passivation layer 705 and is electrically connected to the source/drain metal layer of the third TFT 723 by a through-hole.
Furthermore, the enhancement layer 71 surrounds and covers the first sensor electrode, the second sensor electrode, and the connector electrode layer. When external light enters layers, the enhancement layer will receive the light, thereby improving a light-sensing effect.
Furthermore, the above TFTs may be different. In following embodiments, the first TFT 721 and the third TFT 723 both are low-temperature polycrystalline silicon TFTs, the second TFT is a metal oxide TFT such as an indium gallium zinc oxide (IGZO) TFT.
Please refer to
In
In the present embodiment, the source/drain metal layer of the first TFT 721 and the source/drain metal layer of the second TFT 722 are disposed on a same layer. For example, the source/drain metal layer of the first TFT 721 and the source/drain metal layer of the second TFT 722 are disposed on the interlayer dielectric layer 704. Furthermore, the gate of the first TFT 721 and the gate of the second TFT 722 are disposed on a same layer. For example, the gate of the first TFT 721 and the gate of the second TFT 722 are disposed on the gate insulating layer 703. The source/drain metal layer of the second TFT 722 is at least partly disposed on a surface of the active layer of the second TFT. Thus, corresponding ICs of the above TFTs are disposed on a same side of the insulating substrate. In addition, the first sensor module 706 is disposed on the third TFT 723 and is disposed on a same side as the ICs.
In
Specifically, the first TFT 721, the second TFT 722, and the third TFT 723 are disposed on a same side of the first base layer, and the first sensor module 706 is disposed on another side of the first base layer 108. The first sensor module 706 is electrically connected to the third TFT 723 by a through-hole structure. For example, the first sensor module 706 is electrically connected to a drain of the third TFT 723.
Please refer to
Furthermore, as shown in
In the present embodiment, when the first base layer includes the above stacked layer or a flat structure, connection of corresponding signal lines can be realized by a metal line and a through hole. A lateral-side bonding process or a bottom-side bonding process can be applied to connecting processes. Then, the connecting line and the first base layer are encapsulated to finally form the ICs provided by the present embodiment.
An embodiment of the present disclosure further provides an electronic device, including the semiconductor device provided by the present embodiment. The semiconductor device is provided with a plurality of first ICs and a plurality of second ICs, and mobility of TFTs in the first ICs is greater than mobility of TFTs in the second ICs. The semiconductor device and the electronic device provided by the present embodiment can be applied to different devices such as control devices and display devices. Specifically, the devices may include any products or components having a driving function or a control function such as cell phones, computers, drivers, power mechanisms, or in-vehicle devices. Specific types of the devices are not limited here.
In summary, a semiconductor device, a sensor device, and an electronic device provided by the above embodiments of the present disclosure have been described in detail, which illustrate principles and implementations thereof. However, the description of the above embodiments is only for helping to understand the technical solution of the present disclosure and core ideas thereof, and it is understood by those skilled in the art that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the disclosure that is intended to be limited only by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210913726.9 | Aug 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/113026 | 8/17/2022 | WO |
