Claims
- 1. A method of testing a semiconductor device comprising:
- supporting a semiconductor device on a stationary, electrically insulating body of a test socket with the external leads of the semiconductor device resting on top of the body and a mounting surface on a bottom of a lead end of each lead spaced from the body;
- moving contact terminals mounted on the body into electrical contact with the external leads while the leads are resting on top of the body; and
- testing the semiconductor device through the contact terminals.
- 2. A method as claimed in claim 1 including moving the contact terminals by moving with respect to the body a cover which opposes the body and engages the contact terminals.
- 3. A method as claimed in claim 1 wherein the semiconductor device includes a package portion, the method including supporting the external leads adjoining the package portion.
- 4. A method as claimed in claim 1 wherein the semiconductor device includes a package portion, the method including moving the contact terminals into electrical contact with the external leads adjoining the package portion.
- 5. A method of testing a semiconductor device comprising:
- supporting a semiconductor device including a package portion and a plurality of external leads each including a shoulder adjoining the package portion and an inclined portion disposed between the shoulder and a lead end of the lead on a stationary, electrically insulating body of a test socket with a first side of the shoulders of the external leads of the semiconductor device adjoining the package portion resting on top of a positioning base formed on the body and lead ends of the leads spaced from the body;
- moving contact terminals mounted on the body into electrical contact with a second side of the shoulders of the external leads while the leads are resting on top of the positioning base; and
- testing the semiconductor device through the contact terminals.
- 6. A method as claimed in claim 1 including exerting a wiping force on flat surfaces of the external leads with the contact terminals.
- 7. A method as claimed in claim 6 wherein the wiping force has a vertical component and a horizontal component.
- 8. A method as claimed in claim 1 wherein the semiconductor device includes a package portion, and a bottom surface of the package portion is suspended above the body of the test socket.
- 9. A method as claimed in claim 1 wherein only the external leads of the semiconductor device contact the body of the test socket.
- 10. A method as claimed in claim 1 wherein each contact terminal comprises a shape memory alloy, and moving the contact terminals into contact with the external leads comprises heating the contact terminals to a temperature at which the contact terminals assume a memorized shape contacting the external leads.
- 11. A method as claimed in claim 1 including contacting the contact terminals against a first side of each external lead and contacting springs mounted on the body against a second side of each external lead.
- 12. A method as claimed in claim 11 wherein the springs have a lower elasticity than the external leads.
- 13. A method as claimed in claim 11 including contacting the contact terminals and the springs against the lead ends of the external leads.
- 14. A method as claimed in claim 1 including resting each external lead on the body at a location closer to a package portion of the semiconductor device than to the lead end of the lead.
- 15. A method as claimed in claim 1 wherein the semiconductor device includes a package portion, the method including supporting a first side of each external lead adjoining the package portion and moving the contact terminals into electrical contact with a second side of each external lead adjoining the package portion.
- 16. A method of testing a semiconductor device comprising:
- supporting external leads of a semiconductor device on top of a stationary, electrically insulating body of a test socket with lead ends of the external leads spaced from the body and the body contacting each external lead from below at a location closer to a package portion of the semiconductor device than to the lead end of the external lead;
- moving contact terminals mounted on the body into electrical contact with the external leads while the leads are supported on top of the body; and
- testing the semiconductor device through the contact terminals.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-328264 |
Dec 1992 |
JPX |
|
5-301792 |
Dec 1993 |
JPX |
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Parent Case Info
This disclosure is a division of patent application Ser. No. 08/545,381, filed Oct. 19, 1995, now U.S. Pat. No. 5,693,982, which is a continuation of prior patent application Ser. No. 08/162,951, filed Dec. 8, 1993, and which matured into U.S. Pat. No. 5,461,258 on Oct. 24, 1995.
US Referenced Citations (8)
Foreign Referenced Citations (3)
Number |
Date |
Country |
61-157290 |
Sep 1986 |
JPX |
62-67483 |
Apr 1987 |
JPX |
63-25477 |
Feb 1988 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
545381 |
Oct 1995 |
|
Continuations (1)
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Number |
Date |
Country |
Parent |
162951 |
Dec 1993 |
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