Semiconductor device with a driver circuit for light emitting diodes

Abstract

A novel semiconductor device includes a plurality of light emitting diodes, a plurality of transistors, a source pad, and a plurality of wires. The plurality of transistors drive the plurality of light emitting diodes. The source pad is connected to sources of the plurality of transistors and supplies an electric current to each of the plurality of transistors. The plurality of wires connect the source pad and the sources of the plurality of transistors. The plurality of wires also provide substantially equal resistance to the electric current passing therethrough.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a layout diagram illustrating a background driver circuit for light emitting diodes;

FIG. 2 is an exemplary circuit diagram of the background driver circuit for light emitting diodes of FIG. 1;

FIG. 3 is a layout diagram illustrating another background driver circuit for light emitting diodes;

FIG. 4 is a layout diagram illustrating a driver circuit for light emitting diodes according to a preferred embodiment disclosed in this patent specification; and

FIG. 5 is a circuit diagram of a driver circuit for light emitting diodes according to another embodiment disclosed in this patent specification.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner. Referring now to FIG. 4, a driver circuit 100 for light emitting diodes (LEDs) of a semiconductor device 1 according to a first preferred embodiment is described.

FIG. 4 illustrates an exemplary layout diagram of the LED driver circuit 100.

The driver circuit 100 includes a first transistor array C1, a second transistor array C2, wires 101, 102, 103, 104, 105, and 106, connection pads 121, 122, 123, 124, 125, and 126, a pair of source pads 131 and 132, and a thick wire 133.

The first transistor array C1 is disposed substantially along one side of the circuit 100, including a first transistor 111, a second transistor 112, a third transistor 113, and a fourth transistor 114. The second transistor array C2 is disposed substantially along another side of the circuit 100, including a fifth transistor 115 and a sixth transistor 116. The transistors 111 through 116 may be N-channel metal oxide semiconductor (NMOS) transistors of substantially uniform size and characteristics, serving as drives for a plurality of LEDs (not shown). Alternatively, P-channel MOS transistors may be used according to the intended purpose.

The plurality of LEDs are respectively connected to corresponding one of drains of the transistors 111 through 116 via the connection pads 121 through 126. The pair of source pads 131 and 132 are located between the forth transistor 114 and the fifth transistor 115 and coupled via the thick wire 133.

The first through fourth wires 101 through 104 respectively connect sources of the first through fourth transistors 111 through 114 to the source pad 131. The fifth and sixth wires 105 and 106 respectively connect sources of the fifth and sixth transistors 115 and 116 to the source pad 132.

An electric current for each of the plurality of LEDs is supplied from one of the pair of source pads 131 and 132 to flow in one of the transistors 111 through 116 via corresponding one of the wires 101 through 106. The electric current is supplied to one of the plurality of LEDs via corresponding one of the connection pads 101 through 106.

Each of the wires 101 through 106 has a particular wire length and a particular wire width. The wire length is a length of wire between the transistor and the corresponding source pad. The wire width is a width of wire. Each of the wires 101 through 106 has a particular wire resistance to passage of the electric current in accordance with the particular wire length and the particular wire width.

Given that the wires 101 through 106 are formed of a metal material with a substantially same thickness, values of the wire resistance R₁, R₂, R₃, R₄, R₅, and R₆ for the wires 101, 102, 103, 104, 105, and 106, respectively, are defined by the following equation:

R=R _s ┌L/W  [1]

where “R_s” represents wire resistance per unit area of surface, “L” represents the wire length, and “W” represents the wire width.

The wire resistance R is adjusted by increasing or decreasing the wire length L and/or the wire width W. In the circuit 100, the wires 101 through 106 have particular wire lengths L₁, L₂, L₃, L₄, L₅, and L₆ and particular wire widths W₁, W₂, W₃, W₄, W₅, and W₆, respectively, such that values of the wire resistance R₁, R₂, R₃, R₄, R₅, and R₆ are substantially identical.

To determine the wire length L and the wire width W for each of the wires 101 through 106, the wire length L and the wire width W of a wire connected to a transistor farthest from the source pad are first determined. The wire width W is determined to be within a reasonable range within the constraints of design rules for a particular circuit layout and electrical parameters.

For example, the wire width W₁ and the wire length L₁ of the wire 101 connecting the first transistor 111 and the source pad 131 are first determined to obtain the resistance R₁. The wire length L and the wire width W for each of the other wires are determined in accordance with the layout of the components such that the resistance R is substantially identical to R₁.

The wire 104 connecting the fourth transistor 114 to the source pad 131 may be extended to have the wire length L₄ such that the wire width W₄ is not less than a minimum limit determined by configuration of the driver circuit 100, such as design rule and maximum electric current applied to the wires.

For example, among the values of wire length L₁, L₂, L₃, and L₄, L₁ is largest, L₂ is second largest, and L₃ is least. Among the values of wire width W₁, W₂, W₃, and W₄, W₁ is largest, W₂ is second largest, and W₃ is least.

The value of L₄ may be set substantially equal to the value of L₂, for example. In this case, the values of W₄ and W₂ are substantially equal to each other. However, L₄ need not be equal to L₂, and W₄ need not be equal to W₂. The values of L₄ and W₄ may be arbitrarily defined in accordance with equation [1] and the configuration of the driver circuit 100.

Referring now to FIG. 5, an LED driver circuit 10 according to another preferred embodiment is described. FIG. 5 is a circuit diagram illustrating an example of the LED driver circuit 10.

The circuit 10 includes first through sixth LEDs D1, D2, D3, D4, D5, and D6 and first through sixth transistors 11, 12, 13, 14, 15, and 16. The circuit 10 also includes a small transistor 17, first through sixth connection pads 21, 22, 23, 24, 25, and 26, a constant current source 30, a pair of source pads 31 and 32, first resistors R11, R12, R13, R14, R15, and R16, second resistors R21, R22, R23, R24, R25, and R26, and a power supply Vdd.

The power supply Vdd is connected to anodes of the LEDs D1 through D6, and the connection pads 21 through 26 are respectively connected to cathodes of the LEDs D1 through D6. The connection pads 21 through 26 respectively connect the LEDs D1 through D6 with the transistors 11 through 16.

The small transistor 17 is a MOS transistor of the same conductivity type as the transistors 11 through 16. For example, when the transistors 11 through 16 are NMOS transistors, the MOS transistor 17 is also an NMOS transistor. The small transistor 17 has a size several dozen to several thousand times smaller than the size of the transistors 11 through 16.

The source of the small transistor 17 is grounded, and the drain of the small transistor 17 is connected to the power supply Vdd via the current source 30. The gate of the small transistor 17 is connected to the gates of the transistors 11 through 16. The gate and the drain of the small transistor 17 are connected.

The gates of the transistors 11 through 16 are biased at a bias voltage V_b. The power supply Vdd provides each of the LEDs D1 through D6 with a drive current corresponding to the bias voltage V_b. The amount of drive current supplied to each of the LEDs D1 through D6 is several dozen to several thousand times larger than the amount of electric current supplied by the current source 30.

The drive current supplied to one of the LEDs D1 through D4 passes through corresponding one of the first resistors R11 through R14 and at least one of the second resistors R21 through R24 to flow in the source pad 31. Similarly, the drive current supplied to one of the LEDs D5 and D6 passes through corresponding one of the first resistors R15 and R16 and at least one of the second resistors R25 and R26 to flow in the source pad 32. The number of resistors through which the drive current for one of the LEDs D1 through D6 passes varies depending on the position of the transistor in relation to the corresponding source pad.

The first resistors R11 through R16 and the second resistors R21 through R26 represent resistance provided by wires used to form the circuit 10. Values of resistance of the first and second resistors R11 through R16 and R21 through R26 are determined such that total resistance between each of the transistors 11 through 16 and the corresponding source pad is substantially equal to a constant R_a.

The values of resistance of the first resistors R11 through R16 and the second resistors R21 through R26 are defined to satisfy the following equations:

R ₁₁ +R ₂₁ =R ₁₂

R ₁₂ +R ₂₂ =R ₁₃

R ₁₃ +R ₂₃ =R ₁₄

R ₁₆ +R ₂₆ =R ₁₅

R ₁₄ +R ₂₄ =R ₁₅ +R ₂₅ =R _a

where R₁₁, R₁₂, R₁₃, R₁₄, R₁₅, and R₁₆ respectively represent the values of resistance of the first resistors R11, R12, R13, R14, R15, and R16, and R₂₁, R₂₂, R₂₃, R₂₄, R₂₅, and R₂₆ respectively represent the values of resistance of the second resistors R21, R22, R23, R24, R25, and R26.

Each of the transistors 11 through 16 has gate-source voltage which is substantially constant and independent of the electric current supplied to the LEDs D1 through D6. The values of resistance R₁₁ through R₁₆ may be controlled by any suitable means, e.g., varying length and/or width of the wires.

Shapes and locations of the components as described in the present specification are preferred examples of the semiconductor device according to the disclosure of this patent specification. However, the present invention is not limited to the examples described herein.

Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.

This patent specification is based on Japanese patent application, No. JPAP2006-11936 filed on Apr. 14, 2006 in the Japanese Patent Office, the entire contents of which are incorporated by reference herein.

Claims

1. A semiconductor device, comprising: a plurality of light emitting diodes;a plurality of transistors having sources and configured to drive the plurality of light emitting diodes;a source pad connected to sources of the plurality of transistors and configured to supply an electric current to each of the plurality of transistors; anda plurality of wires configured to connect the source pad and the sources of the plurality of transistors and to provide substantially equal resistance to the electric current passing therethrough.

2. The semiconductor device according to claim 1, wherein the plurality of wires respectively connect the sources of the plurality of transistors to the source pad.

3. The semiconductor device according to claim 2, wherein each of the plurality of wires has a particular length and a particular width so that the resistance to the electric current passing through each of the plurality of wires is substantially equal.

4. The semiconductor device according to claim 3, wherein the particular width of a longest wire of the plurality of wires is largest.

5. The semiconductor device according to claim 3, wherein the particular length of a widest wire of the plurality of wires is largest.

6. The semiconductor device according to claim 2, wherein at least one of the plurality of wires is extended to increase the particular length thereof.

7. The semiconductor device according to claim 2, wherein the plurality of transistors have a substantially uniform size and substantially common characteristics.

8. The semiconductor device according to claim 2, wherein said transistors have gates that are connected in common, and a predetermined bias voltage is applied thereto to form a constant current circuit.

9. The semiconductor device according to claim 8, further comprising a transistor of a reduced size relative to, and a same conductivity type as, the plurality of transistors and having a gate and a drain connected together, the reduced size transistor being configured to provide a gate-source voltage generated by providing a constant current to the drain thereof as a bias voltage.

10. The semiconductor device according to claim 1, wherein at least one of the plurality of wires is extended to increase the particular length thereof.

11. The semiconductor device according to claim 1, wherein the plurality of transistors have a substantially uniform size and substantially common characteristics.

12. The semiconductor device according to claim 1, wherein gates of the plurality of transistors have gates that are connected in common, and a predetermined bias voltage is applied thereto to form a constant current circuit.

13. The semiconductor device according to claim 12, further comprising a transistor of a reduced size relative to, and a same conductivity type as, the plurality of transistors, said reduced size transistor having a gate and a drain connected together, the reduced size transistor being configured to provide a gate-source voltage generated by providing a constant current to the drain thereof as the bias voltage.

14. The semiconductor device according to claim 1, wherein each of the wires of said plurality of wires has a substantially constant respective width.

15. The semiconductor device according to claim 14, wherein each of the wires of said plurality of wires has a substantially constant thickness.

16. The semiconductor device according to claim 1, wherein each of the wires of said plurality of wires has a respective substantially constant cross-section.

17. The semiconductor device according to claim 16, wherein at least some of the wires of said plurality of wires differ in length and in cross-section but have substantially the same resistance to electric current.