Semiconductor device with multiple channels and method of fabricating the same

Abstract

A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIGS. 1A through 10A are perspective views illustrating a method of fabricating a semiconductor device with multiple channels according to an embodiment of the present invention;

FIGS. 1B through 10B are cross-sectional views of the semiconductor device with the multiple channels taking along a line B-B of FIG. 1A; and

FIGS. 1C through 10C are cross-sectional views of the semiconductor device with the multiple channels taking along a line C-C of FIG. 1A.

Claims

1. A semiconductor device with multiple channels comprising: a semiconductor substrate;a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other;a partial insulation layer disposed on the semiconductor substrate between the conductive regions;a channel layer in the form of at least two bridges contacting the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction;a gate insulation layer on the channel layer; anda gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

2. The semiconductor device of claim 1, wherein the conductive regions are impurity doped source and drain regions.

3. The semiconductor device of claim 1, wherein the partial insulation layer is formed to a thickness that prevents formation of a parasitic channel on the semiconductor substrate beneath the partial insulation layer.

4. The semiconductor device of claim 1, further comprising a device isolation layer defining an active region including the conductive regions and the channel layer and is connected with the partial insulation layer in the first direction.

5. The semiconductor device of claim 4, wherein the partial insulation layer and the device isolation layer are formed of substantially the same insulation material.

6. The semiconductor device of claim 4, wherein the partial insulation layer is separated from the device isolation layer in the second direction by the conductive regions.

7. The semiconductor device of claim 1, wherein the channel layer is formed in the shape of a nanowire.

8. The semiconductor device of claim 1, wherein the channel layer is a Si (silicon) layer.

9. The semiconductor device of claim 1, wherein the gate insulation layer substantially encompasses the channel layer except for a portion of the channel layer contacting the partial insulation layer.

10. The semiconductor device of claim 1, wherein the gate electrode layer extends in the first direction.

11. The semiconductor device of claim 1, wherein the gate electrode layer substantially encompasses the gate insulation layer except for a portion of the gate insulation layer contacting the partial insulation layer.

12. A method of fabricating a semiconductor device with multiple channels comprising: sequentially forming a sacrificial layer and a first semiconductor layer on a semiconductor substrate, the sacrificial layer and the first semiconductor layer extending in a first direction and having a predetermined width in a second direction that is at an angle relative to the first direction;forming a second semiconductor layer on the semiconductor substrate and the sacrificial layer such that the second semiconductor layer covers the sacrificial layer;forming a mask layer defining an active region on the second semiconductor layer;removing portions of the second semiconductor layer, the sacrificial layer and the semiconductor substrate using the mask layer as an etch mask to form a recess region;removing the sacrificial layer;filling a space created by removing the sacrificial layer to form a partial insulation layer and filling the recess region to form a device isolation layer;removing the mask layer to a predetermine width in the second direction to form an opening exposing an upper portion of the second semiconductor layer;removing the exposed upper portion of the second semiconductor layer to provide a channel layer in the form of at least two bridges contacting the partial insulation layer, the at least two bridges being spaced apart from each other in the first direction and connecting the conductive regions with each other in the second direction;forming a gate insulation layer on the channel layer; andforming a gate electrode layer on the gate insulation layer.

13. The method of claim 12, wherein forming the sacrificial layer and the first semiconductor layer having the predetermined width includes: sequentially forming the sacrificial layer and the first semiconductor layer on the semiconductor substrate, the sacrificial layer and the first semiconductor layer having an etch selectivity to each other;forming the mask layer on the first semiconductor layer, the mask layer extending in the first direction and having a predetermined width; andpatterning the first semiconductor layer and the sacrificial layer using the mask layer as an etch mask.

14. The method of claim 12, wherein the first semiconductor layer and the sacrificial layer have an etch selectivity of greater than approximately 30.

15. The method of claim 12, wherein the sacrificial layer is a SiGe (silicon germanium) layer.

16. The method of claim 12, wherein the first semiconductor layer, the sacrificial layer, and the second semiconductor layer are formed by an epitaxial growth method.

17. The method of claim 12, wherein removing the sacrificial layer proceeds with using one selected from the group consisting of a mixture solution including H2O2, HF and CH3COOH, another mixture solution including NH4OH, H2O2 and deionized H2O, and an etch solution including C2H4O3.

18. The method of claim 12, wherein forming the channel layer includes: forming a spacer on inner sidewalls of the mask layer disposed on the second semiconductor layer within the opening, the spacer having an etch selectivity to the second semiconductor layer; andremoving the second semiconductor layer using the spacer and the mask layer as an etch mask to expose the partial insulation layer.

19. The method of claim 18, prior to forming the gate insulation layer, further comprising: removing the spacer and the mask layer; andremoving an upper portion of the device isolation layer such that the channel layer is exposed.

20. The method of claim 19, further comprising rounding the exposed channel layer by a hydrogen annealing process prior to the forming of the gate insulation layer.

21. The method of claim 19, prior to forming the gate insulation layer, further comprising: performing a thermal oxidation process on the exposed channel layer to form a thermal oxide layer on the channel layer;removing the thermal oxide layer; andrepeating the forming of the thermal oxide layer and the removing of the thermal oxide layer to reduce a diameter of the channel layer.

22. The method of claim 19, wherein forming the gate electrode layer includes: filling the removed upper portion of the device isolation layer except for the partial insulation layer on which the channel layer of the first direction is formed, so that the device isolation layer is at substantially the same upper level as an upper portion of the channel layer; andforming the gate electrode layer encompassing the gate insulation layer extending in the first direction and formed on the channel layer.

23. The method of claim 12, further comprising performing a trimming process to reduce a width of the gate electrode layer uniformly after the forming of the gate electrode layer.