Semiconductor device

Abstract

A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a level shifter circuit which increases the voltage of a signal in an I/O power supply area VCC1 (2.5 V) to the voltage of an I/O power supply area VCC2 (3.3 V) in the prior art of the present invention and a first and a second embodiment of the present invention;

FIG. 2( a) shows an example of wiring for true and bar signals in the prior art of the present invention and FIG. 2(b) shows another example of wiring for true and bar signals;

FIGS. 3( a) to 3(c) show the arrangement of signal wires and shield wires in an I/O cell in a semiconductor device according to a first embodiment of the present invention, in which FIG. 3(a) is a top view, FIG. 3(b) is a detail view and FIG. 3(c) is a sectional view;

FIG. 4 schematically shows signal wires and shield wires with I/O cells in place in the semiconductor device according to the first embodiment of the invention;

FIG. 5 schematically shows long-distance wiring with first layer metal shield wires in the semiconductor device according to the first embodiment of the invention;

FIGS. 6( a) and 6(b) show the arrangement of signal wires and shield wires in an I/O cell and surrounding power wires in the semiconductor device according to the first embodiment of the invention, in which FIG. 6(a) is a top view and FIG. 6(b) is a sectional view;

FIG. 7 schematically shows surrounding power wires over the shield wires in the semiconductor device according to the first embodiment of the invention; and

FIGS. 8( a) to 8(c) show the arrangement of signal wires and shield wires in an I/O cell of a semiconductor device according to a second embodiment of the present invention, in which FIG. 8(a) is a top view, FIG. 8(b) is a detailed view and FIG. 8(c) is a sectional view.

Claims

1. A semiconductor device comprising an I/O cell having: a first signal wire; anda first shield wire running parallel to the first signal wire,wherein the first signal wire and the first shield wire pass over a plurality of I/O cells.

2. The semiconductor device according to claim 1, wherein the first shield wire comprises a plurality of wires with the same electric potential.

3. The semiconductor device according to claim 1, wherein the I/O cell has a second signal wire and a second shield wire running parallel to the second signal wire;wherein the second signal wire and the second shield wire pass over the plurality of I/O cells; andwherein a signal in the second signal wire is an inverted signal of a signal in the first signal wire.

4. The semiconductor device according to claim 1, wherein a power wire thicker than the first signal wire lies in a layer over the first signal wire.

5. The semiconductor device according to claim 1, wherein a semiconductor substrate lies in a layer under the first signal wire and the first shield wire and the semiconductor substrate have the same electric potential.

6. The semiconductor device according to claim 1, wherein the signal in the first signal wire is a signal between different power supply areas.

7. The semiconductor device according to claim 1, wherein the first signal wire is a wire along which a buffer cannot be inserted midway.

8. The semiconductor device according to claim 1, wherein the length of the first signal wire is larger than the length of one edge of a semiconductor chip constituting the semiconductor device.

9. The semiconductor device according to claim 1, further comprising: an I/O cell for breaking connection between I/O cells by the first signal wire, which does not include the first signal wire.

10. The semiconductor device according to claim 3, wherein the first signal wire and the first shield wire, and the second signal wire and the second shield wire, are multilayered.

11. The semiconductor device according to claim 3, wherein signals in the first signal wire and the second signal wire are part of an input signal to a level shifter circuit.

12. The semiconductor device according to claim 3, wherein the first signal wire and the second signal wire are equal in length.