Patent Application
20140319576
1. Field
Embodiments of the present invention relate to semiconductor devices.
2. Description of the Related Art
As a switching power supply, a DC-DC converter has been known which reduces a direct current (DC) voltage. It is possible to reduce the size of a transformer forming the DC-DC converter by increasing the operating frequency of the DC-DC converter and thus to reduce the size of the DC-DC converter. In order to increase the operating frequency of the DC-DC converter, it is necessary to improve the switching characteristics of an insulated gate bipolar transistor (IGBT) forming the DC-DC converter. In order to achieve a high-speed and low-loss switching operation in the IGBT, it is necessary to reduce a tail current when the IGBT is turned off.
As a technique for suppressing the tail current of the IGBT, instead of the punch-through (PT) IGBT according to the related art, a field-stop (FS) IGBT has been proposed which reduces a tail current (hereinafter, referred to as a hole tail current) caused by the remaining holes when the IGBT is turned off (for example, see Non-patent Document 1). The cross-sectional structures of the PT-IGBT and the FS-IGBT and the waveforms of a collector current in the PT-IGBT and the FS-IGBT when the IGBTs are turned off will be described.
As illustrated in
As illustrated in
As an IGBT which optimizes the lifetime profile of a rear surface structure to perform a high-speed switching operation, a device has been proposed which includes a first region which is a first-conductivity-type semiconductor layer, a second region which is a second-conductivity-type semiconductor layer that is selectively formed in one main surface of the first region, a third region which is a first-conductivity-type semiconductor layer that is selectively formed in one main surface of the second region, a fourth region which is a second-conductivity-type semiconductor layer that is formed on the other main surface of the first region, a control electrode that is formed on a portion of the first region including at least a portion of the second region, with an insulating film interposed therebetween, a first electrode that is formed on a portion of the second region including at least a portion of the third region, a second electrode that is formed on the fourth region, and a plurality of recombination center lattice defects that are locally arranged in the first region (for example, see the following Patent Document 1).
As another IGBT which optimizes the lifetime profile of a rear surface structure to perform a high-speed switching operation, a device has been proposed which includes a first-conductivity-type first semiconductor layer, a second-conductivity-type second semiconductor layer that is formed in a surface layer of a main surface, a first-conductivity-type third semiconductor layer that is selectively formed in a surface layer of the second semiconductor layer, a second-conductivity-type fourth semiconductor layer that is formed in a surface layer of a rear surface, and a first-conductivity-type fifth semiconductor layer that is formed between the first semiconductor layer and the fourth semiconductor layer and has a higher impurity concentration than the first semiconductor layer. In the device, a recombination center lattice defect with one density distribution peak is arranged in the first semiconductor layer such that the peak position is inside the width of a non-depleted region when the turn-off of the device ends (for example, see the following Patent Document 2).
As still another IGBT which optimizes the lifetime profile of a rear surface structure to perform a high-speed switching operation, a device has been proposed which the stored carrier distribution of a drift layer in an on state is uniformly reduced from a collector to an emitter and is the minimum at the end of the emitter and a change in the stored carrier distribution of a portion of the drift layer close to a collector layer is less than a change in the stored carrier distribution of a portion of the drift layer close to a channel diffusion layer (for example, see the following Patent Document 3).
As still yet another IGBT which optimizes the lifetime profile of a rear surface structure to perform a high-speed switching operation, a switching semiconductor device has been proposed which includes a first-conductivity-type region, a second-conductivity-type region, and an electrode. The second-conductivity-type region includes first to third portions. The second portion has a lower impurity concentration than the first portion and the third portion. The first portion and the second portion are disposed between the first-conductivity-type region and the third portion. The third portion is disposed between the first and second portions and the electrode. In an on state, a second-conductivity-type carrier is implanted from the second-conductivity-type region to the first-conductivity-type region. In a turn-off state, a first-conductivity-type carrier flows from the first-conductivity-type region to the second-conductivity-type region (for example, see the following Patent Document 4).
However, in the FS-IGBT illustrated in
An aspect of the invention is to provide a semiconductor device that performs a high-speed switching operation, in order to solve the above-mentioned problems of the related art. In addition, another aspect of the invention is to provide a semiconductor device with low loss in order to solve the above-mentioned problems of the related art. Furthermore, still another aspect of the invention is to provide a semiconductor device capable of reducing costs, in order to solve the above-mentioned problems of the related art.
In order to address problems such as those mentioned above, according to one aspect of the invention, a semiconductor device includes: a first-conductivity-type semiconductor substrate that is to be a first-conductivity-type drift layer; a second-conductivity-type collector layer that is provided in a surface layer of a rear surface of the first-conductivity-type semiconductor substrate; and a collector electrode that comes into contact with the second-conductivity-type collector layer. Carrier concentration of a region of the first-conductivity-type drift layer that is provided at a depth of 0.3 μm or less from a first pn junction between the first-conductivity-type drift layer and the second-conductivity-type collector layer is in the range of 30% to 70% of stored carrier concentration of a region of the first-conductivity-type drift layer that is provided at a depth greater than 0.3 μm from the first pn junction.
In the semiconductor device according to the above-mentioned aspect, the second-conductivity-type collector layer may have a peak impurity concentration of 1.0×1018 cm−3 or less.
In the semiconductor device according to the above-mentioned aspect, the second-conductivity-type collector layer may have a thickness of 0.5 μm or less.
In the semiconductor device according to the above-mentioned aspect, a switching operation in which gate resistance is in the range of 0.5Ω/cm2 to 10Ω/cm2 and a turn-off time is in the range of 0.27 μs to 0.38 μs may be performed.
The semiconductor device according to the above-mentioned aspect may further include a second-conductivity-type base region which is selectively provided in a surface layer of a front surface of the first-conductivity-type semiconductor substrate and in which a channel is formed in an on state. A depletion layer that is spread from a second pn junction between the second-conductivity-type base region and the first-conductivity-type drift layer when the semiconductor device is turned off may not come into contact with the second-conductivity-type collector layer.
The semiconductor device according to the above-mentioned aspect may further include a first-conductivity-type buffer layer that is provided between the first-conductivity-type drift layer and the second-conductivity-type collector layer and has a lower impurity concentration than the first-conductivity-type drift layer. The depletion layer which is spread from the second pn junction when the semiconductor device is turned off may not come into contact with the first-conductivity-type buffer layer.
The semiconductor device according to the above-mentioned aspect may further include a second-conductivity-type base region which is selectively provided in a surface layer of a front surface of the first-conductivity-type semiconductor substrate and in which a channel is formed in an on state and a first-conductivity-type buffer layer that is provided between the first-conductivity-type drift layer and the second-conductivity-type collector layer and has a lower impurity concentration than the first-conductivity-type drift layer. A depletion layer that is spread from a second pn junction between the second-conductivity-type base region and the first-conductivity-type drift layer when the semiconductor device is turned off may not come into contact with the first-conductivity-type buffer layer.
According to embodiments of the invention, after the fall time starts, the hole carrier concentration difference in the vicinity of the second-conductivity-type collector layer (the difference between the carrier concentration of a hole current in the vicinity of the second-conductivity-type collector layer and the stored carrier concentration of a region of the first-conductivity type-drift layer which is deeper than the vicinity of the second-conductivity-type collector layer from the rear surface of the first-conductivity-type semiconductor substrate) is greatly reduced to about 30% to 70% and a large amount of diffusion current flows from the first-conductivity-type drift layer to the collector electrode, which makes it easy to discharge the remaining holes. Therefore, it is possible to rapidly reduce the hole tail current to zero and to reduce the turn-off time. As a result, it is possible to achieve a high-speed and low-loss switching operation in the NPT-IGBT, regardless of the final thickness of the first-conductivity-type semiconductor substrate.
According to embodiments of the invention, it is possible to achieve a high-speed and low-loss switching operation, regardless of whether the lifetime of the rear surface structure is controlled. Therefore, it is not necessary to perform a process for suppressing a variation in the lifetime. In addition, according to embodiments of the invention, the peak impurity concentration of the second-conductivity-type collector layer is equal to or less than 1.0×1018 cm−3 and the thickness of the second-conductivity-type collector layer is equal to or less than 0.5 μm. Therefore, the hole carrier concentration difference in the vicinity of the second-conductivity-type collector layer when the semiconductor device is turned off can be in the range of about 30% to 70%. Since the second-conductivity-type collector layer can be formed by ion implantation and furnace annealing, it is not necessary to pattern the second-conductivity-type collector layer using laser annealing, unlike the related art.
Advantages According to the semiconductor device of embodiments of the invention, it is possible to provide a semiconductor device which performs a high-speed switching operation, to provide a semiconductor device with low loss, and to reduce costs.
Additional aspects and/or advantages will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention.
These and/or other aspects and advantages will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
Hereinafter, preferred embodiments of a semiconductor device according to the invention will be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, in the layers or regions having “n” or “p” appended thereto, an electron or a hole means a majority carrier. In addition, symbols “+” and “−” added to n or p mean that impurity concentration is higher and lower than that of the layer without the symbols. In the description of the following embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and the description thereof will not be repeated.
In the NPT-IGBT 10 illustrated in
The emitter electrode 7 is electrically insulated from the gate electrode 6 by an interlayer insulating film. That is, the emitter electrode 7 and a MOS gate structure including the p base region 2, the n+ emitter region 3, the gate insulating film 5, and the gate electrode 6 are provided as the front surface structure on the front surface of the n− semiconductor substrate. A rear surface structure including the p+ collector layer 8 and a collector electrode 9 is provided on the rear surface of the n− semiconductor substrate. The p+ collector layer 8 is provided in a surface layer of the rear surface of the n− semiconductor substrate. The collector electrode 9 comes into contact with the p+ collector layer 8. An n buffer layer (not illustrated) may be provided between the n− drift layer 1 and the p+ collector layer 8.
In the NPT-IGBT 10, it is preferable that, in a turn-off state, the difference (hereinafter, referred to as a hole carrier concentration difference in the vicinity of the p+ collector layer 8) between the carrier concentration (hereinafter, referred to as hole carrier concentration) of a hole current in the vicinity of the p+ collector layer 8 and the stored carrier concentration of a region of the n− drift layer 1 which is provided at a position that is deeper than the vicinity of the p+ collector layer 8 from the rear surface of the n− semiconductor substrate be in the range of about 30% to 70%. The reason is as follows. In the turn-off state, the remaining holes can be easily discharged from the rear surface of the n− semiconductor substrate to the outside and it is possible to reduce a tail current (hole tail current) caused by the remaining holes.
The vicinity of the p+ collector layer 8 means a region of the n− drift layer 1 which is provided at a depth, for example, of 0.3 μm or less from a pn junction (first pn junction) 11 between the p+ collector layer 8 and the n− drift layer 1. The region of the n− drift layer 1 which is provided at the position deeper than the vicinity of the p+ collector layer 8 from the rear surface of the n− semiconductor substrate means a region of the n− drift layer 1 which is provided at a depth of, for example, 15 μm from the pn junction 11 between the p+ collector layer 8 and the n− drift layer 1.
In order to set the hole carrier concentration in the vicinity of the p+ collector layer 8 to the above-mentioned conditions, the impurity concentration and thickness of the p+ collector layer 8 may be reduced to such an extent that carriers are less likely to be stored in the rear surface structure and current capability is not reduced. Specifically, the peak impurity concentration of the p+ collector layer 8 may be, for example, equal to or less than 1.0×1018 cm−3. Preferably, the peak impurity concentration of the p+ collector layer 8 may be, for example, equal to or less than 5.0×1017 cm−3. The thickness of the p+ collector layer 8 may be, for example, equal to or greater than 0.1 μm and equal to or less than 0.5 μm.
Next, as a method of manufacturing the semiconductor device according to Embodiment 1, for example, an example in which the NPT-IGBT 10 with a rated breakdown voltage of 1200 V is manufactured (produced) will be described.
Then, as illustrated in
Since the defect layer remains in the rear surface of the n− semiconductor substrate, it is possible to reduce the carrier concentration of the surface layer of the rear surface of the n− semiconductor substrate and to reduce the lifetime of the rear surface of the n− semiconductor substrate. In addition, the surface roughness Ra of the rear surface of the n− semiconductor substrate is reduced to, for example, 0.5 μm by plasma etching which is performed after the back grinding and it is possible to further reduce the lifetime. When the lifetime of the rear surface of the n− semiconductor substrate is reduced, it is possible to perform the switching operation of the NPT-IGBT 10 at a high speed.
Then, for example, boron (B) ions are implanted into the etched rear surface of the n− semiconductor substrate with a dose of 7.0×1012 cm−3 at an acceleration energy of 45 keV. Then, furnace annealing is performed for 5 hours at a temperature of 450° C. to form the p+ collector layer 8 in the surface layer of the rear surface of the n− semiconductor substrate. The peak impurity concentration and depth of the p+ collector layer 8 are, for example, 5.0×1017 cm−3 and 0.5 μm, respectively. Then, the collector electrode 9 which comes into contact with the p+ collector layer 8 is formed as a rear surface electrode. In this way, the NPT-IGBT 10 illustrated in
As described above, according to Embodiment 1, after the fall time starts, the hole carrier concentration difference in the vicinity of the p+ collector layer is greatly reduced to about 30% to 70%. Therefore, a large amount of diffusion current flows from the n− drift layer to the collector electrode, which makes it easy to discharge the remaining holes. It is possible to rapidly reduce the hole tail current to zero and to reduce the turn-off time. As a result, it is possible to achieve a high-speed and low-loss switching operation in the NPT-IGBT, regardless of the final thickness of the n− semiconductor substrate. Specifically, for example, the NPT-IGBT can perform a high-speed switching operation in which gate resistance RgA is 0.5Ω/cm2 to 10Ω/cm2 and the turn-off time is in the range of 0.27 μs to 0.38 μs. The turn-off time means the time unit a drain current is reduced to from 90% to 10% of the falling edge of a gate voltage.
According to Embodiment 1, it is possible to achieve a high-speed and low-loss switching operation, regardless of whether the lifetime of the rear surface structure is controlled. When the lifetime of the rear surface structure is controlled, it is not necessary to perform the lifetime profile optimization process according to the related art since the defect layer generated in the surface layer of the rear surface of the n− semiconductor substrate remains to control the lifetime of the rear surface structure. Therefore, it is not necessary to perform a process of suppressing a lifetime variation and to prevent an increase in costs due to a long process flow.
According to Embodiment 1, the peak impurity concentration of the p+ collector layer is equal to or less than 1.0×1018 cm−3 and the thickness of the p+ collector layer is equal to or less than 0.5 μm. Therefore, the hole carrier concentration difference in the vicinity of the p+ collector layer can be in the range of about 30% to 70% when the semiconductor device is turned off. Since the p+ collector layer can be formed by ion implantation and furnace annealing, it is not necessary to pattern the p+ collector layer using laser annealing, unlike the related art. Therefore, it is possible to prevent an increase in costs due to an increase in the number of processes.
In the PT-IGBT 20, an n buffer layer 21 is provided between a p+ collector layer 8 and an n− drift layer 1. In the PT-IGBT 20, the vicinity of the p+ collector layer 8 means a region of the n− drift layer 1 which is provided at a depth of, for example, 0.3 μm or less from a pn junction 22 between the p+ collector layer 8 and the n buffer layer 21. A region of the n− drift layer 1 which is provided at a position deeper than the vicinity of the p+ collector layer 8 from a rear surface of an n− semiconductor substrate means a region of the n− drift layer 1 which is provided at a depth of 15 μm from the pn junction 22 between the p+ collector layer 8 and the n buffer layer 21.
As a method of manufacturing the semiconductor device according to Embodiment 2, for example, an example in which the PT-IGBT 20 with a rated breakdown voltage of 1200V is manufactured (produced) will be described. First, similarly to Embodiment 1, a front surface structure is formed on the front surface of the n− semiconductor substrate which will be the n− drift layer 1. Then, the rear surface of the n− semiconductor substrate is ground to reduce the thickness of the n− semiconductor substrate to, for example, 140 μm. Similarly to Embodiment 1, a defect layer is formed with a depth of about 20 μm in the ground rear surface of the n− semiconductor substrate.
Then, for example, the rear surface of the n− semiconductor substrate is removed by about 15 μm by plasma etching and the final thickness t2 of the n− semiconductor substrate is reduced to, for example, 125 μm. In this way, similarly to Embodiment 1, a defect layer with a thickness of about 5 μm, which is a lifetime killer, remains in the surface layer of the rear surface of the n− semiconductor substrate. The reason why the defect layer remains in the rear surface of the n− semiconductor substrate is the same as that in Embodiment 1. Then, for example, phosphorus (P) ions are implanted into the etched rear surface of the n− semiconductor substrate with a dose of 2.0×1012 cm−3 at an acceleration energy of 360 keV. Then, phosphorus ions are implanted with a dose of 1.0×1012 cm−3 at an acceleration energy of 720 keV.
In addition, boron ions are implanted into the etched rear surface of the n− semiconductor substrate with a dose of 7.0×1012 cm−3 at an acceleration energy of 45 keV. Then, furnace annealing is performed at a temperature of 450° C. for 5 hours to form the p+ collector layer 8 in the surface layer of the rear surface of the n− semiconductor substrate and to form the n buffer layer 21 in a region that is deeper than the p+ collector layer 8 so as to come into contact with the p+ collector layer 8. The peak impurity concentration and depth of the p+ collector layer 8 are, for example, 5.0×1017 cm−3 and 0.5 μm, respectively, similarly to Embodiment 1. Then, a collector electrode 9 which comes into contact with the p+ collector layer 8 is formed as a rear surface electrode. In this way, the PT-IGBT 20 illustrated in
As described above, according to Embodiment 2, in the PT-IGBT, hole carrier concentration in the vicinity of the p+ collector layer can be set to the same conditions as those in Embodiment 1. Therefore, it is possible to obtain the same effect as that in Embodiment 1. According to Embodiment 2, it is possible to reduce the final thickness of the n− semiconductor substrate, as compared to Embodiment 1.
Next, for the NPT-IGBT 10 (hereinafter, referred to as Example 1) with a rated breakdown voltage of 1200 V according to Embodiment 1, a mechanism in which the hole tail current was rapidly reduced in the turn-off state was verified by a device simulation. First, the relationship between the hole tail current and the impurity concentration of the p+ collector layer 8 will be described. As comparison, an NPT-IGBT (hereinafter, referred to as a comparative example) in which the impurity concentration of a p+ collector layer was higher than that in Example 1 was simulated by the same method as that in Example 1. The comparative example has the same structure as Example 1 except for the impurity concentration of the p+ collector layer.
Then, collector injection efficiency a when the NPT-IGBT was turned off was calculated by a simulation.
Then, the current waveform of a hole current component in the vicinity of the p+ collector layer 8 when the hole current was 13% of the rated current (hereinafter, referred to as the hole current that was 13% of the rated current) for the fall time was calculated by a device simulation.
In
As illustrated in
Next, the relationship between electron carrier concentration pn0 in the vicinity of the p+ collector layer 8 and a forward voltage VF applied to the pn junction between the p+ collector layer and the n− drift layer will be described.
As can be seen from
Next,
As illustrated in
The above-mentioned simulation results proved that the electron carrier concentration distribution depending on the forward voltage VF and the hole carrier concentration distribution in the on state determined the magnitude of the reduction C-1 in the hole carrier concentration in the vicinity of the p+ collector layer 8 which was required for the flow of the diffusion current from the n− drift layer 1 to the collector electrode 9. As described above, the electron carrier concentration distribution of the forward voltage VF and the hole carrier concentration distribution in the on state are mostly determined by the impurity concentration of the p+ collector layer 8. Therefore, it was verified that the impurity concentration of the p+ collector layer 8 was preferably reduced in order to reduce the hole tail current and then to reduce the tail current, during a high-speed switching operation.
(Impurity Concentration of p+ Collector Layer)
Next, the preferred impurity concentration range of the p+ collector layer 8 was verified.
Example 2 is the NPT-IGBT 10 with a planar gate structure according to Embodiment 1. Example 3 is the NPT-IGBT with a trench gate structure. Example 3 has the same structure as Example 2 except for the front surface structure. Example 4 is the NPT-IGBT with a planar gate structure in which the n buffer layer is provided between an n− drift layer and a p+ collector layer. The thickness and impurity concentration of the n buffer layer were 10 μm and 1×1015 cm−3, respectively. Example 4 has the same structure as Example 2 except for the n buffer layer.
As illustrated in
In this simulation, the hole carrier concentration in the vicinity of the p+ collector layer 8 was the hole carrier concentration of a region of the n− drift layer 1 which was provided at a depth of 0.3 μm or less from the pn junction 11 between the p+ collector layer 8 and the n− drift layer 1. The stored carrier concentration of the region of the n− drift layer 1 which was provided at the position deeper than the vicinity of the p+ collector layer 8 from the rear surface of the n− semiconductor substrate was the stored carrier concentration of a region of the n− drift layer 1 which was provided at a depth of 15 μm from the pn junction 11 between the p+ collector layer 8 and the n− drift layer 1. A distance Xj (=the thickness of the p+ collector layer 8) from the rear surface of the n− semiconductor substrate to the pn junction 11 was 0.5 μm.
As illustrated in
The above-mentioned various conditions used to calculate the simulation result illustrated in
Next, the relationship between the hole tail current and the gate resistance RgA for the fall time was verified by a device simulation.
Next, the relationship between the hole tail current and a turn-off time toff for the fall time was verified by a device simulation.
It was verified that, when the turn-off time toff was equal to or less than 0.38 μs (on the left side of a vertical solid line represented by reference numeral E-2), the hole tail current was substantially zero, as illustrated in
The invention is not limited to the above-described embodiments. For example, the thickness of the n− semiconductor substrate or the thickness and impurity concentration of each region may be changed. In each of the above-described embodiments, the first conductivity type is an n type and the second conductivity type is a p type. However, in the invention, the first conductivity type may be a p type and the second conductivity type may be an n type. In this case, the same effect as described above is obtained.
As described above, the semiconductor device according to the invention is useful for a power semiconductor device which is used in a power conversion device, such as an inverter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-126618 | Jun 2012 | JP | national |
This application is a continuation application, filed under 35 U.S.C. §111(a), of International Application PCT/JP2013/060254 filed on Apr. 3, 2013, and claims foreign priority benefit of Japanese Patent Application 2012-126618 filed on Jun. 1, 2012 in the Japanese Patent Office, the disclosures of both of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2013/060254 | Apr 2013 | US |
| Child | 14327288 | US |
