Semiconductor device

Abstract

To make it difficult to obtain a secret key from a power change or EM emission intercepted when an IC card encounters a power analysis attack or an electromagnetic wave analysis attack. An arithmetic circuit and a circuit for transmitting/receiving a signal to/from outside are included. The arithmetic circuit includes a central processing unit, an auxiliary arithmetic unit, a random number generator, and a read only memory. The read only memory stores a program for processing of blocking a side-channel attack in signal transmission/reception to/from outside. By additionally providing the random number generator and the auxiliary arithmetic unit, time change of physical data which leaks from an IC chip can be made more complex. This operation is executed by the program. Therefore, it takes time to obtain inside data from physical data intercepted by the third party, thereby security can be improved.

Description

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of a semiconductor device of Embodiment Mode 1.

FIGS. 2A and 2B are block diagrams each of a memory of a semiconductor device of Embodiment Mode 1.

FIG. 3 is a block diagram of a signal of Embodiment Mode 1.

FIG. 4 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 5 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 6 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 7 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 8 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 9 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 1.

FIG. 10 is a block diagram of an auxiliary arithmetic unit of Embodiment Mode 1.

FIG. 11 is a flow chart showing a side-channel attack blocking mechanism of Embodiment Mode 2.

FIG. 12 is a block diagram of a semiconductor device of Embodiment Mode 2.

FIGS. 13A to 13E are cross-sectional diagrams of a semiconductor device of Embodiment Mode 3.

FIGS. 14A and 14B are cross-sectional diagrams of a semiconductor device of Embodiment Mode 4.

FIG. 15 is a block diagram of a semiconductor device of Embodiment Mode 5.

FIGS. 16A to 16D are diagrams of antenna shapes of Embodiment Mode 6.

FIGS. 17A to 17C are diagrams of antenna shapes of Embodiment Mode 7.

FIGS. 18A and 18B are circuit diagrams of a semiconductor device of Embodiment Mode 8 and FIG. 18C is a diagram showing variations of threshold voltage of a TFT.

FIG. 19 is a diagram showing a mode of a random number generator of Embodiment Mode 8.

FIG. 20 is a diagram showing an example of use of a semiconductor device of Embodiment Mode 9.

Claims

1. A semiconductor device comprising: a circuit for transmitting and receiving a signal from an outside; andan arithmetic circuit for processing to block a side-channel attack by the signal from the outside, the arithmetic circuit comprising: a first memory in which a side-channel attack blocking program for processing to block the side-channel attack is stored;a central processing unit for reading the side-channel attack blocking program from the first memory and executing the side-channel attack blocking program;an auxiliary arithmetic unit for performing an inverse transformation process of data based on the signal by the side-channel attack blocking program;a random number generator for generating a random number for setting calculation time of the inverse transformation process; anda second memory in which the inversed data is stored.

2. A semiconductor device comprising: a circuit for transmitting and receiving a signal from an outside; andan arithmetic circuit for processing to block a side-channel attack by the signal from the outside, the arithmetic circuit comprising: a first memory in which a side-channel attack blocking program for processing to block a side-channel attack is stored;a central processing unit for reading the side-channel attack blocking program from the first memory and executing the side-channel attack blocking program so that an inverse transformation process of data based on the signal is performed;a random number generator for generating a random number for setting calculation time of the inverse transformation process; anda second memory in which the inversed data is stored.

3. The semiconductor device according to claim 1, wherein the signal from the outside comprises a frame start code, a flag code, a command code, a data code, a cyclic redundancy check code, and a frame end code.

4. The semiconductor device according to claim 2, wherein the signal from the outside comprises a frame start code, a flag code, a command code, a data code, a cyclic redundancy check code, and a frame end code.

5. The semiconductor device according to claim 1, wherein the side-channel attack blocking program comprises a first routine for judging the kind of the signal from the outside, and a second routine for judging the number of calculation of the inverse transformation process.

6. The semiconductor device according to claim 2, wherein the side-channel attack blocking program comprises a first routine for judging the kind of the signal from the outside, and a second routine for judging the number of calculation of the inverse transformation process.

7. The semiconductor device according to claim 1, wherein the arithmetic circuit comprises a controller including an interface, a control register, a code extracting circuit, and an encoding circuit.

8. The semiconductor device according to claim 2, wherein the arithmetic circuit comprises a controller including an interface, a control register, a code extracting circuit, and an encoding circuit.

9. The semiconductor device according to claim 1, wherein the circuit for transmitting and receiving the signal from the outside comprises an antenna, a resonant circuit, a power supply circuit, a reset circuit, a clock generating circuit, a demodulating circuit, a modulating circuit, and a power managing circuit.

10. The semiconductor device according to claim 2, wherein the circuit for transmitting and receiving the signal from the outside comprises an antenna, a resonant circuit, a power supply circuit, a reset circuit, a clock generating circuit, a demodulating circuit, a modulating circuit, and a power managing circuit.

11. The semiconductor device according to claim 1, wherein the random number generator comprises a memory cell array which is controlled by a decoder and a reading circuit including a first memory cell, andwherein a value of the random number is determined by a difference between a threshold voltage of the first memory cell and a threshold voltage of a second memory cell which is selected from the memory cell array.

12. The semiconductor device according to claim 2, wherein the random number generator comprises a memory cell array which is controlled by a decoder and a reading circuit including a first memory cell, andwherein a value of the random number is determined by a difference between a threshold voltage of the first memory cell and a threshold voltage of a second memory cell which is selected from the memory cell array.

13. An RFID IC chip having the semiconductor device according to claim 1.

14. An RFID IC chip having the semiconductor device according to claim 2.

15. A semiconductor device comprising: a memory in which a side-channel attack blocking program for processing to block a side-channel attack and a secret key are stored;a central processing unit for reading the side-channel attack blocking program from the first memory and executing the side-channel attack blocking program;an auxiliary arithmetic unit for performing an inverse transformation process of data based on the side-channel attack blocking program and the secret key; anda random number generator for generating a random number for setting calculation time of the inverse transformation process.

16. A semiconductor device comprising: a memory in which a side-channel attack blocking program for processing to block a side-channel attack and a secret key are stored;a central processing unit for reading the side-channel attack blocking program from the first memory and executing the side-channel attack blocking program so that an inverse transformation process of data is performed based on the side-channel attack blocking program and the secret key; anda random number generator for generating a random number for setting calculation time of the inverse transformation process.

17. The semiconductor device according to claim 15, wherein the side-channel attack blocking program comprises a first routine for judging the kind of the signal from the outside, and a second routine for judging the number of calculation of the inverse transformation process.

18. The semiconductor device according to claim 16, wherein the side-channel attack blocking program comprises a first routine for judging the kind of the signal from the outside, and a second routine for judging the number of calculation of the inverse transformation process.

19. The semiconductor device according to claim 15, wherein the random number generator comprises a memory cell array which is controlled by a decoder and a reading circuit including a first memory cell, andwherein a value of the random number is determined by a difference between a threshold voltage of the first memory cell and a threshold voltage of a second memory cell which is selected from the memory cell array.

20. The semiconductor device according to claim 16, wherein the random number generator comprises a memory cell array which is controlled by a decoder and a reading circuit including a first memory cell, andwherein a value of the random number is determined by a difference between a threshold voltage of the first memory cell and a threshold voltage of a second memory cell which is selected from the memory cell array.

21. An RFID IC chip having the semiconductor device according to claim 15.

22. An RFID IC chip having the semiconductor device according to claim 16.

23. The semiconductor device according to claim 1, wherein the first memory is a ROM.

24. The semiconductor device according to claim 2, wherein the first memory is a ROM.

25. The semiconductor device according to claim 15, wherein the memory is a ROM.

26. The semiconductor device according to claim 16, wherein the memory is a ROM.

27. The semiconductor device according to claim 1, wherein the second memory is a RAM.

28. The semiconductor device according to claim 2, wherein the second memory is a RAM.

29. A driving method of a semiconductor device comprising: transmitting data into an auxiliary unit;reading a random number from a random number generator;reading a secret key from a memory;transforming inversely the data based on the random number and the secret key in the auxiliary unit; andchanging an auxiliary arithmetic time by the random number.