This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-173787, filed on Sep. 18, 2018; the entire contents of which are incorporated herein by reference.
Embodiments relate to a semiconductor device.
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) may be formed in a semiconductor device by forming STI (Shallow Trench Isolation (an element-separating insulating film)) in an upper layer portion of a semiconductor substrate to partition an active area, and by providing a source region and a drain region inside the active area. It is desirable to increase the reliability of such a semiconductor device.
A semiconductor device according to one embodiment includes a semiconductor portion of a first conductivity type, an insulating portion provided in an upper layer portion of the semiconductor portion, a source region, a drain region and a gate electrode. The insulating portion surrounds an active area. The source region and the drain region are provided inside the active area and separated from each other along a first direction parallel to an upper surface of the semiconductor portion. The source region and the drain region are of a second conductivity type. The gate electrode is provided above the semiconductor portion. The gate electrode is disposed in a region directly above a region between the source region and the drain region, and disposed in a region directly above an end portion in a second direction of the active area. The second direction is orthogonal to the first direction.
A first embodiment will now be described.
As shown in
A STI 13 made of, for example, silicon oxide is provided in the upper layer portion of the epitaxial layer 11. When viewed from above, the configuration of at least a portion of the STI 13 is a frame-like configuration and partitions an active area 14. The active area 14 is a portion of the epitaxial layer 11 and is surrounded with the STI 13 when viewed from above. The upward direction is notated as a vertical direction V in the drawings.
A p-well 16 of the p-conductivity type is provided inside the active area 14. The p-well 16 is formed over substantially the entire region of the active area 14 and is disposed also below the STI 13.
Two source regions 17 of the n-conductivity type, one drain region 18 of the n-conductivity type, and two back gate regions 19 of the p+-conductivity type are provided in the upper layer portion of the p-well 16. The impurity concentrations of the source regions 17, the drain region 18, and the back gate regions 19 are higher than the impurity concentration of the p-well 16.
The configurations of the source regions 17, the drain region 18, and the back gate regions 19 when viewed from above (the vertical direction V) are band configurations extending in a gate-width direction W. In a gate-length direction L, the drain region 18 is disposed between the two source regions 17 and is separated from the source regions 17. The two back gate regions 19 are disposed on the outer sides of the two source regions 17 in the gate-length direction L. The back gate regions 19 contact the source regions 17.
The p-well 16, the source region 17, the drain region 18, and the back gate region 19 also are portions of the semiconductor portion 12. The vertical direction V, the gate-width direction W, and the gate-length direction L are orthogonal to each other. An upper surface 12a of the semiconductor portion 12 as an entirety is parallel to the gate-width direction W and the gate-length direction L. In
A gate electrode 20 is provided on the semiconductor portion 12. A gate insulating film 30 is provided between the semiconductor portion 12 and the gate electrode 20. In the gate electrode 20, a pair of first portions 21 and 22 that extend in the gate-length direction L and a pair of second portions 23 and 24 that extend in the gate-width direction W are formed as one body. “The first portion 21 extending in the gate-length direction L” means that the length in the gate-length direction L of the first portion 21 is longer than the length in the gate-width direction W and the length in the vertical direction V of the first portion 21.
The first portion 21 and the first portion 22 are separated from each other in the gate-width direction W. The second portions 23 and 24 are disposed between the first portion 21 and the first portion 22. The second portion 23 and the second portion 24 are separated from each other in the gate-length direction L. The two end portions in the gate-width direction W of the second portions 23 and 24 are connected to the first portions 21 and 22. Thereby, an opening 25 that is surrounded with the first portion 21, the first portion 22, the second portion 23, and the second portion 24 is formed in the gate electrode 20.
The drain region 18 is disposed inside the opening 25 when viewed from above. The source region 17 and the back gate region 19 are disposed between the first portion 21 and the first portion 22 on the two sides in the gate-length direction L of the second portion 23, the opening 25, and the second portion 24.
A MOSFET formed of the p-well 16, the source region 17, the drain region 18, the back gate region 19, the gate electrode 20, and the gate insulating film 30. In such a case, the portion of the p-well 16 positioned between the source region 17 and the drain region 18 is used to form a channel region 26. The source region 17 and the back gate region 19 are connected to a common contact (not illustrated). The drain region 18 is connected to a drain contact (not illustrated). The gate electrode 20 is connected to a gate contact (not illustrated). The contacts are provided on the semiconductor portion 12. In the semiconductor device 1, two MOSFETs are formed by disposing one drain region 18 between two source regions 17.
The second portions 23 and 24 of the gate electrode 20 are disposed in regions directly above the channel regions 26. The first portions 21 and 22 are disposed from regions directly above end portions 14a in the gate-width direction W of the active area 14 to regions directly above the STI 13. In other words, the first portions 21 and 22 jut from the regions directly above the STI 13 toward the regions directly above the end portions 14a of the active area 14.
As shown in
When viewed from above, an n-well 31 of the n-conductivity type is formed at the periphery of the p-well 16 in the semiconductor portion 12. The n-well 31 is disposed in a region directly under the STI 13 and contacts the lower surface of the STI 13. A portion of the n-well 31 pierces the STI 13 and is connected to a well contact (not illustrated). A deep n-well 32 of the n-conductivity type is provided below the n-well 31. A buried n-type layer 33 of the n-conductivity type is provided below the deep n-well 32 in a region directly under the active area 14. The buried n-type layer 33 is formed along the interface between the silicon substrate 10 and the epitaxial layer 11.
A box-shaped n-type region 34 is formed of the n-well 31, the deep n-well 32, and the buried n-type layer 33. The n-type region 34 surrounds surfaces of the active area 14 other than the upper surface of the active area 14, i.e., two side surfaces on the gate-length direction L side, two side surfaces on the gate-width direction W side, and the lower surface. The active area 14 is electrically isolated from the periphery by the STI 13 and the n-type region 34.
A method for manufacturing the semiconductor device according to the embodiment will now be described.
As shown in
Then, the gate insulating film 30 is formed at the upper surface of the epitaxial layer 11. Then, a polysilicon film is formed on the gate insulating film 30 and patterned with the gate insulating film 30. Thereby, the gate electrode 20 is formed. At this time, the first portions 21 and 22 of the gate electrode 20 are patterned to jut from the regions directly above the STI 13 toward the regions directly above the two end portions 14a in the gate-width direction W of the active area 14.
Continuing as shown in
At this time, the first portions 21 and 22 of the gate electrode 20 jut from the regions directly above the STI 13 toward the regions directly above the two end portions 14a of the active area 14; therefore, the impurities substantially are not implanted into the two end portions 14a; and the source region 17 and the drain region 18 are formed in regions separated from the STI 13.
Then, the back gate region 19 is formed by ion implantation. When forming the back gate region 19 as well, the first portions 21 and 22 of the gate electrode 20 cover the two end portions 14a of the active area 14; therefore, the impurity substantially is not implanted into the two end portions 14a. Therefore, in the gate-width direction W, the back gate region 19 is formed in a region separated from the STI 13. Thus, the semiconductor device 1 according to the embodiment is manufactured.
Effects of the embodiment will now be described.
In the embodiment as shown in
Although an example is shown in the embodiment in which two MOSFETs are provided, the number of the MOSFETs may be one. Also, three or more MOSFETs may be formed as illustrated in the second embodiment described below.
A comparative example will now be described.
In the semiconductor device 101 according to the comparative example as shown in
Accordingly, in the semiconductor device 101, the impurities for forming the source region 17, the drain region 18, and the back gate region 19 are implanted into the end portions 14a in the gate-width direction W of the active area 14, i.e., the vicinity of the STI 13; and crystal defects are introduced easily. In particular, crystal defects are introduced easily at the interface vicinity of the STI 13.
In the semiconductor device 101, the crystal defects are terminated by the bonding of hydrogen in sintering performed in the manufacturing processes, etc.; therefore, it is often that problems do not become apparent directly after the completion of the semiconductor device 101. However, when stress such as a high temperature, a high voltage, or the like is applied, the hydrogen may desorb from the crystal defects; and a leakage current that has the crystal defects as starting points may occur. Therefore, the reliability of the semiconductor device 101 is low.
A second embodiment will now be described.
The embodiment is an example in which many MOSFETs are formed in the semiconductor device.
In the semiconductor device 2 according to the embodiment as shown in
When viewed from above, the multiple source regions 17 are arranged to be separated from each other alternately along the gate-length direction L inside each of the openings 41. The drain region 18 is disposed in every other region between the mutually-adjacent source regions 17; and the back gate region 19 is disposed in every other region between the mutually-adjacent source regions 17. The back gate region 19 is disposed also on the outer side of the source region 17 on the outermost side. The drain region 18 is separated from the source regions 17 on the two sides of the drain region 18; and the region between the drain region 18 and the source region 17 is the channel region 26. The back gate region 19 contacts the source regions 17 on the two sides of the back gate region 19.
In the semiconductor device 2 as shown in
In the gate electrode 50, multiple openings 51 and 52 are arranged in a matrix configuration along the gate-width direction W and the gate-length direction L. The length in the gate-width direction W of the opening 51 is substantially equal to the length in the gate-width direction W of the opening 52. The length in the gate-length direction L of the opening 51 is shorter than the length in the gate-length direction L of the opening 52. The same types of openings are arranged in the gate-width direction W. The opening 51 and the opening 52 are arranged alternately in the gate-length direction L. One column that is made of the openings 51 and 52 arranged along the gate-length direction L corresponds to one opening 41 of the STI 43.
The drain region 18 is disposed inside the opening 51 when viewed from above. Two source regions 17 and one back gate region 19 that are disposed between the two source regions 17 are disposed inside the opening 52.
The portion of the gate electrode 50 extending along the gate-length direction L covers the greater part of the two end portions 14a in the gate-width direction W of the active area 14 and particularly covers the two sides in the gate-width direction W of each of the source region 17, the drain region 18, and the back gate region 19. Therefore, the source region 17, the drain region 18, and the back gate region 19 are separated from the STI 43. Also, the portions of the gate electrode 50 extending along the gate-width direction W are disposed in regions directly above the channel regions 26. On the other hand, the portions of the gate electrode 55 extending in the gate-width direction W cover two end portions 14b in the gate-length direction L of the active area 14.
In the embodiment as well, the greater part of the end portion 14a of the active area 14 is covered with the gate electrode 50. Also, the end portion 14b of the active area 14 is covered with the gate electrode 55. Thereby, little of the impurities for forming the source region 17, the drain region 18, and the back gate region 19 is implanted into the semiconductor portion 12 at the vicinity of the STI 43. As a result, the crystal defects are not introduced easily; and the reliability is high.
Otherwise, the configuration, the manufacturing method, and the effects of the embodiment are similar to those of the first embodiment.
The openings 41 of the STI 43 may be arranged in a matrix configuration along the gate-width direction W and the gate-length direction L.
Although an example is shown in the first and second embodiments in which an n-channel MOSFET is formed, a p-channel MOSFET may be formed.
According to the embodiments described above, a semiconductor device can be realized in which the reliability is high.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2018-173787 | Sep 2018 | JP | national |