Patent Application
20090243016
This patent application claims priority from Japanese Patent Application No. 2008-083799, filed 27 Mar. 2008, the entirety of which is incorporated herein by reference for all purposes.
The invention relates generally to a semiconductor and, more particularly, to a PIN photodiode.
A PIN photodiode is an element that converts incident light into a photoelectric current; it has a P-I-N structure wherein an Intrinsic layer (a high-resistance epitaxial layer or the like) is included between a P-type semiconductor and an N-type semiconductor. The principle of operation is that when light with greater energy than the energy band gap is irradiated on silicon (Si) having a reverse-biased PIN structure, electron-hole pairs are generated within the silicon crystal, and these pairs migrate as charge carriers: the electrons to the N-layer and the holes to the P-layer, thus outputting currents in opposite directions.
An example of a conventional photodiode can be seen at Japanese Patent Application No. 2001-320079.
A preferred embodiment of the present invention, accordingly, provides a semiconductor device. The semiconductor device comprises at least one photoreceptive element region formed in a semiconductor region, at least one circuit element region formed in a semiconductor region, and a multilayer wiring region formed on the semiconductor regions excluding the photoreceptive element region; wherein the multilayer wiring region includes a multilayer structure metal wiring layer electrically connected to a circuit element of the circuit element region, and a light-blocking wall that blocks light from the outside; wherein the light-blocking wall includes a multilayer structure metal layer that is arranged along the perimeter of the photoreceptive element region and is formed in the same step as the multilayer structure metal wiring layer.
The light-blocking wall can be arranged along the perimeter of the circuit element region or of a semiconductor chip. Furthermore, the multilayer wiring region can include at least one light-blocking metal wiring layer in the uppermost layer, with the light-blocking wall being arranged along the perimeter of the light-blocking metal wiring layer. Furthermore, the light-blocking wall can be formed with an intermittently separated hole shape, in which case multiple hole-configuration light-blocking walls are arranged as multiple rows in a zigzag form.
Preferably the light-blocking wall includes at least an upper metal layer, a lower metal layer, and a metal plug within a via hole formed in an insulation film between the upper and lower metal layers. Preferably the upper metal layer is connected to the light-blocking metal wiring layer of the uppermost layer by a plug.
In accordance with a preferred embodiment of the present invention, the entrance of unnecessary light into the circuit element region is prevented by providing a light-blocking wall along the perimeter of the photoreceptive element region, so that circuit malfunctions can be prevented. Furthermore, the light-blocking wall is fabricated using the same process, so that the light-blocking wall can be formed easily without increasing the manufacturing steps.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
A multilayer wiring region 210 that includes multilayer structure wiring layers with insulation films interposed therebetween formed on silicon substrate 110. A rectangular hole H is formed in multilayer wiring region 210 such that photoreceptive element region 120 is exposed. Rectangular light-blocking metal wiring layers 220 and 230 (patterned from aluminum (Al) or the like metal layer) and a light-blocking metal wiring layer 240 (in which a hole is formed corresponding to the outline of hole H of photoreceptive element region 120) are formed as the uppermost layer of multilayer wiring region 210. In addition, the chip surface, which includes light-blocking metal wiring layers 220, 230, and 240 and photoreceptive element region 120, is covered with a protective film of a silicon oxide, silicon nitride, or the like.
The light entering hole H passes through the protective film and irradiates the region 120 formed in the surface of the silicon substrate. When region 120 is a PIN photodiode, a reverse-bias voltage can applied to the region 120 to form a depletion region therein, and when light enters the depletion region, electron-hole pairs are generated. The electrons and holes migrate to the reverse-biased electrodes, and photoelectric current is generated. The currents are amplified by the circuit element region 130 and are output to the outside from a terminal (not shown).
A feature of the device 200 is that multilayer wiring region 210 is provided with a linear pattern of light-blocking walls 222, 232, and 242 to block light from the outside. Light-blocking wall 242 is arranged near the side wall of hole H such that it surrounds the perimeter of the region 120, which corresponds to the route of the light entering peripheral circuit region 130. Light-blocking wall 244 is arranged along the outline or the outer portion of light-blocking metal wiring layer 240. Light-blocking wall 222 is arranged along the outline or the outer portion of light-blocking metal wiring layer 220. Light-blocking wall 232 is arranged along the outline or the outer portion of light-blocking metal wiring layer 230. Portions of light-blocking walls 222, 232, and 244 also serve as light-blocking walls arranged along the perimeter of the chip.
Multilayer wiring region 210 is an example of metal wiring layers with a 4-layer structure. Preferably, the light-blocking walls 222, 232, and 244 include metal layers with a 4-layer structure just as with the metal wiring layers with a 4-layer structure. The light-blocking walls 222, 232, and 244 are formed using the same process as with the metal wiring layers, so that a new process is not required to form the light-blocking walls 222, 232, and 244; in other words, it is necessary to change only the wiring pattern when the metal wiring layers are formed and the mask pattern when the via hole is formed in the interlayer insulation film. Preferably, the metal wiring layers that comprise the light-blocking walls 222, 232, and 244 include a via contact or a plug that fills the via hole formed in the interlayer insulation film.
Preferably, the interlayer insulation films undergos a planarization process; for example, the films can be formed by applying a liquefied insulating substance such as BPSG or can be planarized by chemical mechanical planarization (CMP) or the like. In addition, the size and shape of the via hole formed in the interlayer insulation films can be selected appropriately depending on the material of the metal layer used, the film thickness of the interlayer insulation film, or the like. To form the metal layers of light-blocking walls in a linear pattern, it is preferable that copper (Cu) be used, due to its good filling characteristics, to generally prevent voids from occurring in the plug or the via contact. Furthermore, in the previous example, barrier metals BM1-BM3 were formed underlying the second through fourth metal layers; however, a barrier metal may be eliminated. Furthermore, in the previous example, the plug and the metal layer were formed in the same step; however, for example, if different multilayer wiring processes are used to form the plug formed in the via hole and the metal layer formed on the plug with different materials, then the metal layer and the plug of the light-blocking wall will exhibit the same changes.
Furthermore, as shown in
A light-blocking wall (as described above) that reflects light from the outside is formed in the multilayer wiring region; thus, for example, the light that irradiates outer edge 162 and the gap 160 between light-blocking metal layers 220, 230 and 240 is blocked by light-blocking walls 222, 232 and 244. Therefore, the entrance of light into circuit element region 130 can be generally prevented. Furthermore, most of the light entering hole H is received by photoreceptive element region 120, but the light that irradiates the side walls of hole H is blocked by light-blocking wall 242, so that the entrance of light into peripheral circuit region 130 can be prevented. Furthermore, light irradiating the chip surface is blocked by light-blocking metal wiring layers 220, 230 and 240 of the uppermost layer. Thus, circuit element malfunctions are prevented and the sensitivity of the photoreceptive element can be maintained at a high level.
Turning to
With the linear pattern of plugs shown in
With devices 100 and 300, one photoreceptive element region was formed on the silicon substrate; however, multiple photoreceptive elements or photoreceptive element regions can be formed, and light-blocking walls can be formed in the multilayer wiring region such that each photoreceptive element region is enclosed.
Furthermore, as described, the light-blocking walls were formed respectively at the perimeter of the photoreceptive element region, the perimeter of the peripheral circuit region, and the perimeter of the chip; however, it is not required that the light-blocking walls be formed in all of these positions; the light-shielding walls can be formed in some of these positions. Furthermore, the number of metal layers forming light-blocking walls was identical to the number of metal wiring layers of the multilayer wiring regions; however, there can be fewer light-blocking walls than metal wiring layers of the multilayer wiring regions. In this case, near the silicon substrate, it will be difficult for light to enter at a large oblique angle, so that there can be a light-blocking wall with a metal layer omitted adjacent to the silicon substrate.
Now, turning to
The semiconductor devices 200 and 300 are applicable to photoreceptive devices 430 and 440 of this type. Photoreceptive devices 430 and 440 include a PIN photodiode for the purpose of receiving the blue light, and devices 430 and 440 integrate on one silicon chip a circuit that amplifies or processes signals detected by the PIN photodiode. The integrated circuit includes multiple MOS transistors or the like.
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-083799 | Mar 2008 | JP | national |
