Patent Application
20160247917
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-034189, filed on Feb. 24, 2015, the entire contents of which are incorporated herein by reference.
The embodiments of the present invention relate to a semiconductor device.
In recent years, a TFET (Tunnel Field-Effect Transistor) using a quantum-mechanical effect of electrons has been developed. In the TFET, BTBT (Band To Band Tunneling) is generated between a source layer and a channel part by applying a voltage to a gate electrode. This brings the TFET to an on-state. In order to lower a power supply voltage to suppress power consumption in the TFET, variation in electrical characteristics (a threshold voltage, for example) of the TFET needs to be reduced. For example, in order to reduce variation in the threshold voltage, a suppression of parasitic BTBT to improve sub-threshold swing characteristics (hereinafter, also “SS characteristics”) of the TFET is demanded.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the embodiments, “an upper direction” or “a lower direction” refers to a relative direction when a direction of a surface of a semiconductor layer on which semiconductor elements are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction.
A semiconductor device according to an embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode includes a first gate part and a second gate part. The first gate part and the second gate part are provided on the semiconductor layer via the gate dielectric film. The first gate part and the second gate part have work functions respectively different from each other, and are electrically connected to each other. A drain layer of a first conductivity type is provided in the semiconductor layer on a side of one end of the gate electrode. A source layer of a second conductivity type is provided in the semiconductor layer on a side of the other end of the gate electrode and below the gate electrode. The source layer below the gate electrode has a substantially uniform impurity concentration.
The TFET 100 includes a BOX (Buried Oxide) layer 10, a semiconductor layer 20, a gate dielectric film 30, the gate electrode 40, the drain layer 50, the source layer 60, and a silicide layer 70.
The semiconductor layer 20 is a SOI (Silicon On Insulator) layer provided on the BOX layer 10. The semiconductor layer 20 can be a SOI layer of a SOI substrate or can be a SiGe layer of a SiGe—OI substrate, a Ge layer of a Ge—OI substrate, a silicon layer formed of a silicon substrate, or a semiconductor layer using a III-V compound semiconductor substrate. Alternatively, the semiconductor layer 20 can be a semiconductor layer epitaxially grown on an arbitrary substrate.
The gate dielectric film 30 is an insulating film provided on a surface of the semiconductor layer 20 and is formed of, for example, a silicon dioxide film or a dielectric material having a higher dielectric constant than that of the silicon dioxide film. The gate dielectric film 30 includes a first gate dielectric film 31 and a second gate dielectric film 32. The first gate dielectric film 31 and the second gate dielectric film 32 can be formed of the same material. While a film thickness Tox1 of the first gate dielectric film 31 is substantially equal to a film thickness Tox2 of the second gate dielectric film 32, the film thicknesses Tox1 and Tox2 can be slightly different from each other, as described later.
The gate electrode 40 includes a first gate part 41 and a second gate part 42. The first gate part 41 and the second gate part 42 are provided on the semiconductor layer 20 via the first gate dielectric film 31 and the second gate dielectric film 32, respectively (or with the first gate dielectric film 31 and the second gate dielectric film 32 interposed therebetween, respectively). The first gate part 41 and the second gate part 42 are adjacent to each other, and an insulating film 35 is provided between the first gate part 41 and the second gate part 42. The first gate part 41 and the second gate part 42 are electrically connected to each other by the silicide layer 70. While being used during formation of the first gate part 41 and the second gate part 42, the insulating film 35 is not required for characteristics of the TFET 100. The insulating film 35 is formed sufficiently thinly not to affect the characteristics (an on-resistance, for example) of the TFET 100.
The first gate part 41 is provided on the side of the source layer 60 and is formed of, for example, N-doped polysilicon. The second gate part 42 is provided on the side of the drain layer 50 and is formed of, for example, P-doped polysilicon. Therefore, the first gate part 41 and the second gate part 42 have different work functions. In the first embodiment, the second gate part 42 is larger in the work function than the first gate part 41. Accordingly, the TFET 100 according to the first embodiment is brought to a conduction state by BTBT occurring in a channel part CH below the first gate part 41 while suppressing BTBT parasitically occurring at an end E52 of the drain layer 50 below the second gate part 42. A gate length of the first gate part 41 is larger than that of the second gate part 42. This enables an enlargement of a facing area between a bottom surface of the first gate part 41 and a surface of the source layer 60. When the facing area between the bottom surface of the first gate part 41 and the surface of the source layer 60 is large, a current flowing in the channel part CH due to BTBT is increased, which leads to an improvement in the SS characteristics. A more detailed operation of the TFET 100 is explained later.
The N-type drain layer 50 includes an N+-type deep layer 51 and an N-type extension layer 52. The N-type drain layer 50 is provided in the semiconductor layer 20 on the side of one end E1 of the gate electrode 40. The extension layer 52 is shallower (thinner) than the deep layer 51 and is lower in the impurity concentration than the deep layer 51. The extension layer 52 is provided in a surface region of the semiconductor layer 20 in such a manner as to extend from the deep layer 51 to the gate electrode 40. Therefore, the end E52 of the extension layer 52 is located below the second gate part 42 and at least a part of a surface of the extension layer 52 faces a bottom surface of the second gate part 42. That is, when viewed from above the surface of the semiconductor layer 20, at least a part of the surface of the extension layer 52 overlaps with the bottom surface of the second gate part 42.
If the deep layer 51 extends to the end E1 of the gate electrode 40 without the extension layer 52 provided, a GIDL (Gate Induced Drain Leakage) current may occur during a standby (off) time and the SS characteristics may be degraded. In order to suppress such degradation in the SS characteristics, it is preferable to form the shallow (or thin) and low-concentration extension layer 52.
The P-type source layer 60 is provided in the semiconductor layer 20 on the side of the other end E2 of the gate electrode 40 and below the gate electrode 40. In the first embodiment, almost the whole of the bottom surface of the gate electrode 40 faces the source layer 60. That is, the source layer 60 is provided in the semiconductor layer 20 to extend from the other end E2 of the gate electrode 40 to a vicinity of the end E1 of the gate electrode 40 across a portion below the bottom surface of the gate electrode 40. Therefore, the channel part CH below the gate electrode 40 has the same conductivity type as that of the source layer 60 and an impurity concentration of the channel part CH is substantially equal to that of the source layer 60. That is, there is no junction part between the source layer 60 and the channel part CH and the concentration gradient is gentle. The source layer 60 and the channel part CH extend at substantially uniform impurity concentrations. Accordingly, the channel part CH is defined as a facing region between the bottom surface of the gate electrode 40 and the source layer 60. As described above, the TFET 100 is a so-called source junctionless TFET (hereinafter, also “SJL-TFET”) having no junction part on the source side.
The silicide layer 70 is provided on the gate electrode 40. The silicide layer 70 is, for example, a metal silicide obtained by a reaction between a metal such as Ni, Co, or Ti and silicon. The silicide layer (not shown in
Although not shown in
In the SJL-TFET, if an end of the drain layer is located below the gate electrode, BTBT is more likely to occur in a junction part between the end of the drain layer and a channel part (an inverted region) below the gate electrode than in the channel part. In this case, the SS characteristics are degraded.
On the other hand, if the end of the drain layer is offset from the gate electrode toward the drain layer to prevent the drain layer from facing the bottom surface of the gate electrode, BTBT occurs in the channel part below the gate electrode. However, if the end of the drain layer is separated too much from the gate electrode, an on-current flowing between the source and the drain becomes small or the on-current does not flow.
In the TFET 100 according to the first embodiment, the gate electrode 40 is thus divided into a plurality of parts and includes the first gate part 41 and the second gate part 42. The second gate part 42 is electrically shortcircuited with the first gate part 41 by the silicide layer 70. Therefore, the same gate voltage is applied to the first gate part 41 and the second gate part 42. However, in the first embodiment, the second gate part 42 is larger in the work function than the first gate part 41. Accordingly, an energy level in the semiconductor layer 20 below the second gate part 42 is shifted toward a vacuum level. Energy bands in the semiconductor layer 20 are explained with reference to energy band diagrams shown in
CBoff and VBoff shown by dashed lines in
It is assumed, for example, that 0 volt is applied to the source layer 60 and that a positive voltage (1 volt, for example) is applied to the drain layer 50. That is, when the TFET 100 is in an off-state, a reverse bias is applied to a PN junction part between the source layer 60 and the drain layer 50. When the TFET 100 is to be brought to an on-state, voltages of the same polarity are applied to the gate electrode 40 and the drain layer 50, respectively. That is, when the TFET 100 is to be brought to an on-state, a positive voltage is applied to the gate electrode 40 as mentioned below.
When an application voltage to the gate electrode 40 is lower than a threshold voltage, the TFET 100 is in an off-state. At that time, because the off maximum value EC1 of the extension layer 52 is sufficiently higher than the energy level VBoff of the valence band as shown in
When a positive voltage is applied to the gate electrode 40 with respect to a source voltage, the channel part CH starts depleting. Accordingly, the energy bands in the channel part CH below the gate electrode 40 are bent toward the valence band. When the energy bands become a state shown by CBon and VBon in
Energy bands near the end E52 of the extension layer 52 along the line A3-A2 in
In contrast thereto, as shown in
As described above, the TFET 100 according to the first embodiment can generate vertical BTBT in the channel part CH (hereinafter, also “BTBT in the channel part CH”) below the first gate part 41 while suppressing parasitic BTBT in the PN junction part (hereinafter, also “BTBT in the PN junction part”) between the source layer 60 (the channel part CH) and the drain layer 50 by setting the work function of the second gate part 42 to be larger than that of the first gate part 41. Accordingly, the SS characteristics of the TFET 100 are improved, as explained with reference to
As indicated by the line L0, in the TFET having a single gate electrode, BTBT in the PN junction part occurs when the gate voltage Vg is Vpara and then BTBT in the channel part CH occurs when the gate voltage Vg is Vth. Vpara is a threshold voltage of the BTBT in the PN junction part. Vth is a threshold voltage of the BTBT in the channel part CH. If the threshold voltage Vpara is lower than the threshold voltage Vth and the parasitic BTBT in the PN junction part occurs earlier than the BTBT in the channel part CH, the SS characteristics are degraded.
In contrast thereto, because the work function of the second gate part 42 is larger than that of the first gate part 41 in the TFET 100 according to the first embodiment, the threshold voltage Vpara becomes higher than the threshold voltage Vth and the BTBT in the channel part CH occurs earlier than the BTBT in the PN junction part as indicated by the line L1. That is, when the gate voltage Vg is increased and the gate voltage Vg becomes the threshold voltage Vth, the BTBT in the channel part CH occurs while the BTBT in the PN junction part is suppressed. Because the BTBT in the channel part CH can occur in the whole facing surface between the bottom surface of the first gate part 41 and the surface of the source layer 60, the BTBT in the channel part CH enables a larger current to flow as compared to the BTBT in the PN junction part. Therefore, as shown in
As described above, in the first embodiment, the end E52 of the extension layer 52 is located below the second gate part 42, and the surface of the extension layer 52 faces the bottom surface of the gate electrode 40. However, by setting the work function of the second gate part 42 to be larger than that of the first gate part 41, the threshold voltage Vpara can be set to be larger than the threshold voltage Vth. Accordingly, when the gate voltage is increased, the BTBT in the channel part CH occurs earlier than the BTBT in the PN junction part. The BTBT in the channel part CH occurs in the surface area of the source layer 60 facing the bottom surface of the first gate part 41. The BTBT in the channel part CH thus can occur in a wider area than the BTBT in the PN junction part. Therefore, a large drain current Id flows at voltages near the threshold voltage Vth shown in
The threshold voltage of the TFET 100 is not affected so much by the BTBT in the PN junction part and is determined by the BTBT in the channel part CH. That is, the BTBT in the channel part CH becomes dominant and the threshold voltage of the TFET 100 is determined by the threshold voltage Vth rather than the threshold voltage Vpara. Accordingly, even when the position of the end E52 of the extension layer 52 (the position of the PN junction part) varies, variation in the threshold voltage of the TFET 100 is suppressed. This enables to stabilize the threshold voltage and the SS characteristics of the TFET 100 regardless of the position of the end E52 of the extension layer 52. As a result, the power supply voltage and the power consumption of the TFET 100 can be reduced.
As described above, the film thickness Tox1 of the first gate dielectric film 31 can be substantially equal to or slightly different from the film thickness Tox2 of the second gate dielectric film 32. For example, the film thickness Tox2 can be larger than the film thickness Tox1. A larger film thickness Tox2 reduces an electric field applied from the second gate part 42 to the PN junction part between the source layer 60 and the drain layer 50. This further suppresses occurrence of the BTBT in the PN junction part between the source layer 60 and the drain layer 50. A leakage current (a gate leakage current) between the gate electrode 40 and the drain layer 50 is also reduced in an off-state of the TFET 100 due to the large film thickness Tox2. On the other hand, the film thickness Tox2 can be smaller than the film thickness Tox1 as long as the BTBT in the channel part CH occurs at a lower gate voltage than that causes the BTBT in the PN junction part.
A manufacturing method of the TFET 100 according to the first embodiment is explained next.
First, as shown in
The first gate dielectric film 31 can be a thermally-oxidized film obtained by thermally oxidizing the semiconductor layer 20 or can be a TEOS (Tetraethylorthosilicate) film, a silicon nitride film (Si3N4), SiON film, or a high dielectric film such as HfO2 formed by a CVD (Chemical Vapor Deposition) method.
Next, as shown in
Subsequently, a material of the first gate part 41 is deposited on the first gate dielectric film 31 and a material of the hard mask 45 is deposited on the material of the first gate part 41. The material of the first gate part 41 is formed of, for example, polysilicon or polysilicon germanium doped with N-type impurities such as phosphorous or arsenic. Alternatively, the material of the first gate part 41 can be formed by implanting ions of the N-type impurities after depositing polysilicon or polysilicon germanium. The material of the hard mask 45 is formed of, for example, an insulating film such as a silicon nitride film. Next, the material of the hard mask 45 is processed into a layout pattern of the first gate part 41 using a lithography technique and a RIE (Reactive Ion Etching) method. The material of the first gate part 41 and the first gate dielectric film 31 are processed by the RIE method using the hard mask 45 as a mask. A structure shown in
Subsequently, an insulating film such as a silicon nitride film is deposited on side surfaces of the first gate part 41 and a top surface of the hard mask 45 using the CVD method. Next, the insulating film is anisotropically etched using the RIE method, thereby leaving a spacer 47 on the side surfaces of the first gate part 41 as shown in
Subsequently, the source layer 60 is covered with a photoresist 49 using the lithography technique as shown in
After removal of the photoresist 49, an insulating film such as a TEOS film is further deposited on the spacer 47 and the hard mask 45 using the CVD method. Next, the insulating film is anisotropically etched using the RIE method, thereby further leaving a sidewall film 57 on side surfaces of the spacer 47 as shown in
Subsequently, as shown in
Next, as shown in
After removal of the photoresist 59, the spacer 47 and the hard mask 45 are etched using a heat phosphoric acid solution. The spacer 47 on the drain side is thereby removed as shown in
Subsequently, the second gate dielectric film 32 is formed on the semiconductor layer 20. The second gate dielectric film 32 can be a thermally-oxidized film obtained by thermally oxidizing the semiconductor layer 20 or can be a TEOS film, a silicon nitride film, SiON film, a high dielectric film, or the like formed by the CVD method similarly to the first gate dielectric film 31. Unless effects of the first embodiment are impaired, materials of the first gate dielectric film 31 and the second gate dielectric film 32 can be same or different from each other.
Next, as shown in
Subsequently, the material of the second gate part 42 is anisotropically etched using the RIE method. The second gate part 42 is thereby left on a side surface of the first gate part 41 on the drain side as shown in
Next, a material of a spacer 48 is deposited using the CVD method. The material of the spacer 48 is an insulating film such as a silicon dioxide film or a silicon nitride film. The material of the spacer 48 is then anisotropically etched using the RIE method. Accordingly, the spacer 48 is formed to cover a side surface of the second gate part 42, and portions of the second gate dielectric film 32 on the surface of the semiconductor layer 20 in the source layer 60 and the drain layer 50 are removed as shown in
Subsequently, a metal such as Ni, Co, or Ti is deposited on the first gate part 41, the second gate part 42, the source layer 60, and the drain layer 50 using a PVD (Physical Vapor Deposition) method. By reaction between the metal layer and silicon, the silicide layer 70 is formed on the first gate part 41, the second gate part 42, the source layer 60, and the drain layer 50 as shown in
An interlayer dielectric film, contacts, wires, and the like are then formed, whereby the TFET 100 according to the first embodiment is completed. Although the structure of the TFET 100 shown in
As described above, by setting the work function of the second gate part 42 to be larger than that of the first gate part 41, the TFET 100 according to the first embodiment can generate BTBT in the channel part CH while suppressing parasitic BTBT in the PN junction part. Accordingly, the SS characteristics are improved.
Furthermore, because the threshold voltage Vth of the BTBT in the channel part CH is lower than the threshold voltage Vpara of the BTBT in the PN junction part and the threshold voltage Vth becomes dominant, variation in the threshold voltage of the TFET 100 is suppressed even when the position of the end E52 of the extension layer 52 (the drain layer 50) varies. This enables to reduce the power supply voltage and the power consumption of the TFET 100.
In the TFET 200 according to the second embodiment, the drain layer 50 is offset from the gate electrode 40. Therefore, the electric field of a gate voltage is unlikely to be applied to the end E52 of the extension layer 52 and the BTBT in the PN junction part is unlikely to occur.
Meanwhile, the electric field of a gate voltage is also unlikely to be applied to a region (hereinafter, “offset region”) OS of the channel part CH between the end E1 of the gate electrode 40 and the end E52 of the extension layer 52. Therefore, if the work function of the second gate part 42 is as high as that of the first gate part 41, a depletion layer is unlikely to be formed in the offset region OS and an on-current is unlikely to flow when the gate voltage is increased.
In contrast thereto, in the second embodiment, a semiconductor material (N-type polysilicon, for example) having a relatively-low work function is used for the second gate part 42. Accordingly, energy bands in the channel part CH below the second gate part 42 and in the offset region OS near the channel part CH are previously shifted toward the valence band. This causes a depletion layer to be likely to extend in the offset region OS and the on-current to be likely to flow.
CBoff and VBoff shown by dashed lines in
Because the work function of the second gate part 42 is smaller than that of the first gate part 41, the energy bands CBoff and VBoff in the source layer 60 below the second gate part 42 are previously shifted toward the valence band as compared to those in the surface region of the source layer 60 below the first gate part 41 when the TFET 200 is in an off-state. That is, the energy bands CBoff and VBoff of the source layer 60 below the second gate part 42 are close to energy bands in the offset region OS.
When a positive voltage is applied to the gate electrode 40 with respect to the source voltage, the channel part CH starts depleting. Accordingly, the energy bands in the channel part CH below the first gate part 41 are bent toward the valence band as shown by CBon and VBon in
At this time, the energy bands in the offset region OS adjacent to the second gate part 42 are also sufficiently bent toward the valence band because the energy bands CBoff and VBoff in the source layer 60 below the second gate part 42 are previously shifted toward the valence band. Therefore, a depletion layer is easily formed in the offset region OS. This facilitates formation of a channel in the source layer 60 below the second gate part 42 and in the offset region OS. As shown by an arrow AR2 in
Meanwhile,
In contrast thereto, in the TFET 200 according to the second embodiment, because the work function of the second gate part 42 is smaller than that of the first gate part 41, the energy bands CBoff and VBoff in the surface area of the source layer 60 below the second gate part 42 are previously bent toward the valence band. Accordingly, when the gate voltage is increased, the energy bands can be sufficiently shifted toward the valence band in the source layer 60 (the channel part CH) below the second gate part 42 and in the offset region OS as shown in
Furthermore, in the second embodiment, the drain layer 50 is offset from the gate electrode 40 and the end E52 of the extension layer 52 is not provided below the gate electrode 40. Accordingly, the BTBT in the PN junction part is unlikely to occur and the TFET 200 can be reliably brought to an on-state by the BTBT in the channel part CH. Accordingly, the second embodiment can also achieve effects identical to those of the first embodiment.
The gate length of the second gate part 42 can be smaller or larger than that of the first gate part 41. When the gate length of the second gate part 42 is smaller than that of the first gate part 41, it is considered that almost all of the BTBT in the channel part CH occurs below the first gate part 41. When the gate length of the second gate part 42 is larger than that of the first gate part 41, it is considered that the BTBT in the channel part CH occurs below both the first gate part 41 and the second gate part 42. In either case, no problems occur because the BTBT in the PN junction part is suppressed and the BTBT in the channel part CH occurs in the channel part CH below the first gate part 41 and/or the second gate part 42.
A manufacturing method of the TFET 200 according to the second embodiment is explained next.
First, processes explained with reference to
Next, a material of the first gate part 41 is deposited on the first gate dielectric film 31. The first gate part 41 can have, for example, a MIPS (Metal Inserted Poly-Si Stack) structure. In this case, a material of a lower layer 41a of the first gate part 41 is formed of a metallic material such as TaN, TiN, or Ti. A material of an upper layer 41b of the first gate part 41 can be a semiconductor material such as polysilicon or a polysilicon germanium. In this case, a work function of the first gate part 41 is determined by the material of the lower layer 41a.
Subsequently, a material of the hard mask 45 is deposited on the material of the first gate part 41. The material of the hard mask 45 is formed of an insulating film such as a silicon nitride film. Next, the material of the hard mask 45 is processed into a layout pattern of the first gate part 41 using the lithography technique and the RIE method. The first gate part 41 and the first gate dielectric film 31 are processed by the RIE method using the hard mask 45 as a mask. A structure shown in
Subsequently, the second gate dielectric film 32 is formed on the semiconductor layer 20. The second gate dielectric film 32 can be a thermally-oxidized film obtained by thermally oxidizing the semiconductor layer 20 or can be a TEOS film, a silicon nitride film, SiON film, a high dielectric film, or the like formed by the CVD method similarly to the first gate dielectric film 31. Unless effects of the second embodiment are impaired, materials of the first gate dielectric film 31 and the second gate dielectric film 32 can be same or different.
Next, a material of the second gate part 42 is deposited on the second gate dielectric film 32 using the CVD method as shown in
Subsequently, the material of the second gate part 42 is anisotropically etched using the RIE method. The second gate part 42 is thereby left on both side surfaces of the first gate part 41 as shown in
Next, a material of a hard mask 53 is deposited using the CVD method as shown in
Subsequently, by using the lithography technique and the etching technique, the material of the hard mask 53 on the source side is removed while the material of the hard mask 53 on the drain side is left as shown in
Next, for example, when the second gate part 42 is polysilicon germanium, the material of the second gate part 42 is wet-etched with a mixed solution (SC1) of NH3 and H2O2, or the like, using the hard masks 53 and 45 as a mask. The material of the second gate part 42 on the source side is thereby removed while the material of the second gate part 42 on the drain side is left as shown in
Subsequently, the hard mask 53 is anisotropically etched using the RIE method. As shown in
Next, the source layer 60 is covered with the photoresist 49 using the lithography technique as shown in
Subsequently, ions of N-type impurities are implanted to the semiconductor layer 20 on the drain side using the photoresist 49, the spacer 57, and the like as a mask as shown in
Next, after removal of the photoresist 49, the hard mask 45 is removed using a heat phosphoric acid solution or the like. Subsequently, a metal is deposited on the first gate part 41, the second gate part 42, the source layer 60, and the drain layer 50 using the PVD method. By reaction between the metal layer and silicon, the silicide layer 70 is formed on the first gate part 41, the second gate part 42, the source layer 60, and the drain layer 50 as shown in
An interlayer dielectric film, contacts, wires, and the like are then formed, whereby the TFET 200 is completed. Although the structure of the TFET 200 shown in
As described above, in the second embodiment, the drain layer 50 is offset from the gate electrode 40, and the work function of the second gate part 42 is smaller than that of the first gate part 41. Accordingly, the TFET 200 causes a depletion layer to be likely to be formed in the offset region OS while suppressing the BTBT in the PN junction part. Furthermore, the BTBT of the channel part CH is likely to occur below the second gate part 42. As a result, the TFET 200 can become an on-state stably and enables a sufficient current to flow between the source and the drain.
The TFETs 100 and 200 according to the above embodiments can be formed at the same time as a MISFET (Metal Insulation Semiconductor FET) having improved analog characteristics or high-frequency characteristics and including a plurality of gate electrodes. For example, the manufacturing methods of the TFETs 100 and 200 according to the above embodiments can be easily adapted to a manufacturing method of a so-called split gate MISFET or DWF (Dual Work Function) MISFET. The TFETs 100 and 200 according to the above embodiments thus can suppress an increase in the cost by being manufactured in combination with the MISFET including plural gate electrodes.
While the N-TFETs are explained in the above embodiments, the embodiments can be easily applied also to a P-TFET by changing conductivity types of the impurities. The P-TFET becomes an on-state when a gate voltage is lower than a threshold voltage with reference to a source voltage and becomes an off-state when a gate voltage is higher than the threshold voltage. For example, in the case of a P-TFET in a CMOS inverter, a positive voltage is applied to the source and the P-TFET is brought to an on-state by setting the gate voltage to 0 volt and is brought to an off-state by setting the gate voltage to a power supply voltage (1 volt, for example). Even in such a P-TFET, the effects of the embodiments are not impaired. However, when the above embodiments are applied to the P-TFET, a magnitude relation between the work functions of the first gate part 41 and the second gate part 42 is opposite to that in the N-TFET. That is, when the structure of the TFET 100 according to the first embodiment is applied to a P-TFET, the work function of the second gate part 42 is smaller than that of the first gate part 41. When the structure of the TFET 200 according to the second embodiment is applied to a P-TFET, the work function of the second gate part 42 is larger than that of the first gate part 41.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-034189 | Feb 2015 | JP | national |
