This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2013-034711, filed on Feb. 25, 2013, the entire contents of which are incorporated herein by reference.
Embodiments described herein generally relate to a semiconductor device.
An ESD protection diode is connected between an input terminal and an output terminal of a semiconductor device to protect the semiconductor device from breakdown due to ESD (Electro Static Discharge).
Produced semiconductor devices each include an ESD protection diode only as a semiconductor element inside a chip, or an ESD protection diode and a semiconductor element to be protected inside a chip. As an area of a p-n junction diode increases, ESD tolerance of the ESD protection diode becomes higher.
Unfortunately, as the area of the p-n junction diode is increased to enhance the ESD tolerance, a chip area becomes larger to thereby increase production costs of chips.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
According to an embodiment, a semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, and a second electrode. The semiconductor substrate is of a first conductivity type. The first semiconductor layer is of a second conductivity type, provided on the semiconductor substrate. The second semiconductor layer is of a first conductivity type, reaches the semiconductor substrate from a surface of the first semiconductor layer, and surrounds the first semiconductor layer. The third semiconductor layer is of a second conductivity type, separated from the second semiconductor layer, surrounded by the second semiconductor layer, and has a higher concentration of second-conductivity-type impurities than the first semiconductor layer. The first electrode is connected to the semiconductor substrate. The second electrode is connected to the second semiconductor layer. In addition, a withstand voltage between the semiconductor substrate and the third semiconductor layer is lower than the withstand voltage between the second semiconductor layer and the third semiconductor layer.
Embodiments will be described with reference to drawings. The drawings are conceptual. A relationship between a shape and dimension of each portion and a proportionality factor among respective portions may not be necessarily the same as an actual one. Even when the same portions are drawn, their sizes or proportionality factors may be different from each other with respect to the drawings, and may be modified within the scope of the invention. Throughout the specification, a first conductivity type and a second conductivity type will be described as an n-type and a p-type, respectively, and vice versa. Although silicon exemplifies a semiconductor in the detailed description, silicon carbide (SiC) or nitride semiconductors including AlGaN may be employed. When n-type conductivity is denoted by n+, n, and n−, n-type impurity concentrations are assumed to become lower in this order. When p-type conductivity is denoted by p and p−, p-type impurity concentrations are assumed to become lower in this order. A semiconductor device in accordance with each embodiment includes an ESD protection diode only, or includes an ESD protection diode and another semiconductor element. The ESD protection diode only will be simply described as a substantial portion of each embodiment.
A semiconductor device in accordance with a first embodiment will be described with reference to
As shown in
The n−-type epitaxial layer 2 is an n-type semiconductor, and is epitaxially grown on the p-type semiconductor substrate 1. The n−-type epitaxial layer 2 has an n-type impurity concentration of 1×1013/cm3 to 1×1014/cm3, for example.
The p-type semiconductor layer 3 reaches the p-type semiconductor substrate 1, and surrounds the n−-type epitaxial layer 2. As shown in
The n+-type contact layer 4 is selectively provided to the n−-type epitaxial layer 2. The n+-type contact layer 4 is separated by the n−-type epitaxial layer 2 from the p-type semiconductor layer 3. As shown in
The p-type semiconductor layer 3 and the n+-type contact layer 4 are impurity diffused layers. The impurity diffused layers are made by injecting impurities to portions of the n−-type epitaxial layer 2, which is followed by heat treatment to cause the portions to be the p-type semiconductor layer 3 and the n+-type contact layer 4. The method of forming the p-type semiconductor layer 3 and the n+-type contact layer 4 is not limited to this. Alternatively, the p-type semiconductor layer 3 and the n+ type contact layer 4 may be formed such that the layers 3 and 4 are embedded in preliminarily removed portions of the n−-type epitaxial layer 2. Alternatively, the p-type semiconductor layer 3 may be a portion of the p-type semiconductor substrate 1.
A shortest separation distance between the n+-type contact layer 4 and the p-type semiconductor layer 3 is denoted as L1 on the surface of the n−-type epitaxial layer 2. When the center of the circular n+-type contact layer 4 coincides with the center of the circular n−-type epitaxial layer 2, the separation distance L1 between the n+-type contact layer 4 and the p-type semiconductor layer 3 is unchanged in any radial direction. In contrast, when the both centers do not coincide with each other, the separation distance L1 depends basically on a radial direction. In the embodiment, the centers of the two layers 3 and 4 are assumed to substantially coincide with each other.
L2 denotes a separation distance between the bottom of the n+-type contact layer 4 and the upper surface of the p-type semiconductor substrate 1. In the n+-type contact layer 4, the n-type impurity concentration decreases from the surface to bottom of the n+-type contact layer 4. The n-type impurity concentration of the n+-type contact layer 4 is the same as the n-type impurity concentration of the n−-type epitaxial layer 2 at the bottom of the n+-type contact layer 4. In the semiconductor device of the embodiment, the thickness of the n−-type epitaxial layer 2 and the shape of the n+-type contact layer 4 on the surface of the n−-type epitaxial layer 2 are set such that L1 is larger than L2, i.e., L1>L2.
The anode electrode A is electrically connected to the p-type semiconductor substrate 1. The anode electrode A is electrically connected to a back surface of the p-type semiconductor substrate 1. The back surface is on the opposite side of the p-type semiconductor substrate 1 from the n−-type epitaxial layer 2. Alternatively, the anode electrode A may be electrically connected to the p-type semiconductor substrate 1 through the p-type semiconductor layer 3 from the side of the n− type epitaxial layer 2. The cathode electrode C is electrically connected to the n+ type contact layer 4.
A breakdown occurs at a portion of the semiconductor device of the embodiment when a reverse bias voltage is applied between the anode electrode A and the cathode electrode C and when the portion with a shortest distance has a lowest withstand voltage between the p-type semiconductor layer 3 and the n+-type contact layer 4 or between the p-type semiconductor substrate 1 and the n+-type contact layer 4. Since the semiconductor device of the embodiment has a relation of L2<L1, the withstand voltage between the n+-type contact layer 4 and the p-type semiconductor substrate 1 is the lowest to cause a breakdown in a direction vertical to the n−-type epitaxial layer 2 (the direction will be referred to as the vertical direction hereinafter). In the semiconductor device of the embodiment, the withstand voltage between the p-type semiconductor substrate 1 and the n+-type contact layer 4 is lower than the withstand voltage between the p-type semiconductor layer 3 and the n+-type contact layer 4. As a result, a breakdown current flows toward the p-type semiconductor substrate 1 from the bottom of the n+-type contact layer 4.
The semiconductor device of the embodiment just has to include a sectional structure shown in
Also in the first modification, a relation of L2<L1 holds so that a withstand voltage between the p-type semiconductor substrate 1 and the n+-type contact layer 4 is lower than the withstand voltage between the p-type semiconductor layer 3 and the n+-type contact layer 4. As a result, a breakdown current flows toward the p-type semiconductor substrate 1 from the bottom of the n+-type contact layer 4. Whenever the ESD protection diode has a relation of L2<L1, which is a substantial portion of the semiconductor device of the embodiment, the ESD diode may have any structure shown by a plan view other than the plan views of
A breakdown can occur between the n+-type contact layer 4 and the p-type semiconductor layer 3 in the semiconductor device in accordance with the comparative example. As shown by the arrows in
In contrast, a relation of L1>L2 holds in the semiconductor device in accordance with the embodiment. A breakdown can occur in the vertical direction between the n+-type contact layer 4 and the p-type semiconductor substrate 1 in the semiconductor device of the embodiment. A breakdown current flows through the n−-type epitaxial layer 2 in the vertical direction from the bottom of the n+-type contact layer 4 to the p-type semiconductor substrate 1. The n+-type contact layer 4 has a bottom area larger than a sidewall area to thereby cause breakdown current density to be low. This enables the semiconductor device of the embodiment to enhance ESD tolerance of the ESD protection diode while maintaining the area that the ESD protection diode occupies in a chip.
In the semiconductor device of the second modification, current flows in a direction opposite to the current flowing in the semiconductor device of the first embodiment. The semiconductor device of the second modification differs from the semiconductor device of the first embodiment only in a current-flow direction. The semiconductor device of the second modification has the same operations and effects as the semiconductor device of the first embodiment.
A semiconductor device in accordance with a second embodiment will be described with reference to
As shown in
The semiconductor device of this embodiment has the trench 5 on the surface of the n−-type epitaxial layer 2 between the n+-type contact layer 4 and the p-type semiconductor layer 3. This trench serves as a capacitor with small capacitance. A reverse bias applied between the anode electrode A and the cathode electrode C is almost the same as the voltage between the n+-type contact layer 4 and the p-type semiconductor layer 3. Most of the reverse bias is applied across the trench 5.
As a result, few breakdowns occur at a p-n junction made up by the n−-type epitaxial layer 2 and the p-type semiconductor layer 3 in the horizontal direction. For this reason, in the semiconductor device of this embodiment without a relation of L2<L1, a breakdown occurs between the n+-type contact layer 4 and the p-type semiconductor substrate 1 in the vertical direction. As a result, a breakdown current flows from the bottom of the n+-type contact layer 4 through the n−-type epitaxial layer 2 to the p-type semiconductor substrate 1. The semiconductor device of the second embodiment enhances ESD tolerance of the ESD protection diode while maintaining the area that the ESD diode occupies in a chip as well as the semiconductor device of the first embodiment.
Without a limitation of L2<L1, the semiconductor device of the second embodiment causes a breakdown between the n+-type contact layer 4 and the p-type semiconductor substrate 1 in the vertical direction. The semiconductor device of the second embodiment enables the area of the n+-type contact layer 4 to be larger than the semiconductor device of the first embodiment. As a result, the semiconductor device of the second embodiment enables it to enhance the ESD tolerance of the ESD protection diode.
Unfortunately, an extremely short L1 causes a pathway from the bottom of the n+-type contact layer 4 to the p-type semiconductor layer 3 to be shorter than the distance L2. In this case, a breakdown will occur in the pathway. As L1 becomes shorter, the deeper trench 5 needs to be dug more deeply so that the pathway is longer than L2, thereby preventing the breakdown from occurring in the pathway. Alternatively, the trench 5 may be formed such that the trench 5 reaches the p-type semiconductor substrate 1 in order to cause a breakdown in the pathway from the bottom of the n+-type contact layer 4 to the p-type semiconductor substrate 1.
A semiconductor device in accordance with a third embodiment will be described with reference to
As shown in
The insulating film 6 allows it to prevent the semiconductor device of the third embodiment from short-circuiting inside the trench 5 by invasion of foreign substances. The semiconductor device of the third embodiment brings the same effects as well as the semiconductor device of the second embodiment in addition to the prevention of the short-circuiting.
A semiconductor device in accordance with a fourth embodiment will be described with reference to
The semiconductor device of the fourth embodiment includes an insulating film 6 that fills the trench 5. The fourth embodiment differs from the third embodiment in this point. The trench 5 filled with the insulating film 6 serves as a capacitor with large capacitance. The semiconductor device of the fourth embodiment brings the same effects as well as the semiconductor device of the third embodiment.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2013-034711 | Mar 2013 | JP | national |