Patent Application
20250159920
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-192904, filed on Nov. 13, 2023; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device.
For example, it is desired to improve the characteristics of semiconductor devices such as transistors.
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a compound member. The third electrode includes a first electrode portion. A position of the third electrode in a first direction from the first electrode to the second electrode is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N (0≤x1<1). The first semiconductor layer includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. A second direction from the first partial region to the first electrode crosses the first direction, A direction from the second partial region to the second electrode is along the second direction. A direction from the third partial region to the first electrode portion is along the second direction. A position of the fourth partial region in the first direction is between a position of the first partial region in the first direction and a position of the third partial region in the first direction. A position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and a position of the second partial region in the first direction. The second semiconductor layer includes Alx2Ga1-x2N (0<x2<1, x1<x2). The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion. A direction from the fourth partial region to the first semiconductor portion is along the second direction. A direction from the fifth partial region to the second semiconductor portion is along the second direction. The compound member includes Alz1Ga1-z1N (0<z1≤1, x2<z1). The compound member includes a first region, a second region, and a third region. The first region is between the fourth partial region and the first electrode portion in the first direction. The second region is between the first electrode portion and the fifth partial region in the first direction. The third region is between the third partial region and the first electrode portion. A first absolute value of a first difference between a (10-10) inter-plane spacing in the first region and a (10-10) inter-plane spacing in the fourth partial region is greater than a third absolute value of a third difference between a (10-10) inter-plane spacing in the third region and a (10-10) inter-plane spacing in the third partial region.
Various embodiments are described below with reference to the accompanying drawings.
The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and proportions may be illustrated differently among drawings, even for identical portions.
In the specification and drawings, components similar to those described previously or illustrated in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.
As shown in
The third electrode 53 includes a first electrode portion 53a. A first direction D1 from the first electrode 51 to the second electrode 52 is defined as an X-axis direction. One direction perpendicular to the X-axis direction is defined as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is defined as a Y-axis direction.
A position of the third electrode 53 in the first direction D1 is between a position of the first electrode 51 in the first direction D1 and a position of the second electrode 52 in the first direction D1. For example, the third electrode 53 is between the first electrode 51 and the second electrode 52 in the first direction D1. The first electrode 51, the second electrode 52, and the third electrode 53 may extend, for example, along a third direction D3 (for example, the Y-axis direction).
The first semiconductor layer 10 includes Alx1Ga1-x1N (0≤x1<1). The composition ratio x1 is, for example, not less than 0 and not more than 0.05. The first semiconductor layer 10 may be, for example, a GaN layer. The first semiconductor layer 10 may not include, for example, an impurity that provides conductivity.
The first semiconductor layer 10 includes a first partial region 11, a second partial region 12, a third partial region 13, a fourth partial region 14, and a fifth partial region 15. A second direction D2 from the first partial region 11 to the first electrode 51 crosses the first direction D1. The second direction D2 is, for example, the Z-axis direction. For example, the third direction D3 crosses a plane including the first direction D1 and the second direction D2.
A direction from the second partial region 12 to the second electrode 52 is along the second direction D2. A direction from the third partial region 13 to the first electrode portion 53a is along the second direction D2.
A position of the fourth partial region 14 in the first direction D1 is between a position of the first partial region 11 in the first direction D1 and a position of the third partial region 13 in the first direction D1. A position of the fifth partial region 15 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and a position of the second partial region 12 in the first direction D1.
The second semiconductor layer 20 includes Alx2Ga1-x2N (0<x2<1, x1<x2). The composition ratio x2 is, for example, not less than 0.15 and not more than 0.35. The second semiconductor layer 20 may be, for example, an AlGaN layer. The second semiconductor layer 20 may not need include, for example, an impurity that provides conductivity.
The second semiconductor layer 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. A direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. A direction from the fifth partial region 15 to the second semiconductor portion 22 is along the second direction D2.
The compound member 31 includes Alz1Ga1-z1N (0<z1≤1, x2<z1). The composition ratio z1 may be, for example, not less than 0.9 and not more than 1. The composition ratio z1 may be substantially 1, for example. The compound member 31 may be, for example, an AlN layer.
The compound member 31 includes a first region 31a, a second region 31b, and a third region 31c. The first region 31a is located between the fourth partial region 14 and the first electrode portion 53a in the first direction D1. The second region 31b is located between the first electrode portion 53a and the fifth partial region 15 in the first direction D1. The third region 31c is located between the third partial region 13 and the first electrode portion 53a in the second direction D2.
The first semiconductor layer 10, the second semiconductor layer 20, and the compound member 31 include crystals.
In the embodiment, current flowing between the first electrode 51 and the second electrode 52 is controlled by a potential of the third electrode 53. The potential of the third electrode 53 may be based on a potential of the first electrode 51.
The first electrode 51 functions, for example, as a source electrode. The second electrode 52 functions, for example, as a drain electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 110 is, for example, a transistor.
As shown in
As shown in
For example, the first region 31a and the fourth partial region 14 correspond to a side face of the recess. The second region 31b and the fifth partial region 15 correspond to other side face of the recess. The third partial region 13 and the third region 31c correspond to the bottom of the recess.
In the embodiment, a difference between the (10-10) inter-plane spacing in the first region 31a and a (10-10) inter-plane spacing in the fourth partial region 14 is defined as a first difference Δa1. A difference between the (10-10) inter-plane spacing in the third region 31c and a (10-10) inter-plane spacing in the third partial region 13 is defined as a third difference Δa3.
In the embodiment, a first absolute value of the first difference Δa1 is greater than a third absolute value of the third difference Δa3. The description “(10-10) plane” indicates that a “bar” is added to the number after the “-”.
In the portion corresponding to the side face of the recess, the difference in (10-10) inter-plane spacing (the first difference Δa1) between the compound member 31 and the first semiconductor layer 10 is large. In the portion corresponding to the bottom of the recess, the difference in (10-10) inter-plane spacing (the third difference Δa3) between the compound member 31 and the first semiconductor layer 10 is small.
The difference in crystal lattice length is small in the portion corresponding to the bottom of the recess. Thereby, for example, high crystallinity can be obtained in the third partial region 13. Thereby, it becomes easy to obtain high mobility. For example, low on-resistance can be obtained. According to the embodiment, a semiconductor device with improved characteristics can be provided.
On the other hand, the difference in crystal lattice length is large in the portion corresponding to the side face of the recess. For example, on the sides of the recess, the (10-10) inter-plane spacings do not match. Thereby, generation of carriers on the side of the recess is suppressed. Thereby, it becomes easier to obtain a high threshold voltage. For example, it becomes easier to stably obtain a high threshold voltage. According to the embodiment, a semiconductor device with improved characteristics can be provided.
In the embodiment, the second direction D2 crosses the (0001) plane of the crystal included in the first semiconductor layer 10. The angle between the second direction D2 and the (0001) plane is, for example, not less than 85 degrees and not more than 95 degrees. The first direction D1 may cross, for example, the (10-10) plane of the crystal included in the first semiconductor layer 10. The angle between the first direction D1 and the (10-10) plane is, for example, not less than 85 degrees and not more than 95.
As shown in
The compound member 31 may further include a sixth region 31f and a seventh region 31g. The first semiconductor portion 21 is provided between the fourth partial region 14 and the sixth region 31f. The second semiconductor portion 22 is provided between the fifth partial region 15 and the seventh region 31g.
As shown in
The first insulating member 41 may further include a fourth insulating region 41d and a fifth insulating region 41e. The fourth insulating region 41d is provided between the fourth region 31d and the first electrode portion 53a in the first direction D1. The fifth insulating region 41e is provided between the first electrode portion 53a and the fifth region 31e in the first direction D1.
The first insulating member 41 may further include a sixth insulating region 41f and a seventh insulating region 41g. The sixth region 31f is provided between the first semiconductor portion 21 and the sixth insulating region 41f. The seventh region 31g is provided between the second semiconductor portion 22 and the seventh insulating region 41g.
Hereinafter, examples of characteristics of semiconductor devices will be described.
As shown in
A distance along the first direction D1 between the second position 14q and the first region 31a is 10 nm.
As shown in
These figures illustrate evaluation results of the first sample SPL1. The vertical axes are the inter-plane spacing LS.
In
As shown in
As shown in
As shown in
Thus, in the first sample SPL1, the first absolute value of the first difference Δa1 is larger than the third difference Δa3. Thereby, it becomes easy to obtain high mobility. For example, low on-resistance can be obtained. For example, it becomes easier to stably obtain a high threshold voltage.
As shown in
As shown in
For example, it is considered that a large difference Δc3 with respect to the (0001) inter-plane spacing at the bottom of the recess effectively relieves the distortion and reduces the third difference Δa3 with respect to the (10-10) inter-plane spacing.
In the first sample SPL1, the difference Δc3 is larger than the difference Δc1. It is considered that the large difference Δc3 alleviates the distortion more effectively.
It is thought that the large first difference Δa1 regarding the (10-10) inter-plane spacing on the side faces of the recess will alleviate the strain and effectively reduce the third difference Δa3 regarding the (10-10) inter-plane spacing at the bottom of the recess.
Thus, in the embodiment, the absolute value of the difference Δc1 between the (0001) inter-plane spacing in the first region 31a and the (0001) inter-plane spacing in the fourth partial region 14 may be greater than the third absolute value of the third difference Δa3.
The absolute value of the difference Δc3 between the (0001) inter-plane spacing in the third region 31c and the (0001) inter-plane spacing in the third partial region 13 may be greater than the third absolute value of the third difference Δa3.
The relationship between the lattice spacings in the second region 31b and the fifth partial region 15 may be substantially the same as the relationship between the lattice spacings in the first region 31a and the fourth partial region 14.
For example, a difference between the (10-10) inter-plane spacing in the second region 31b and the (10-10) inter-plane spacing in the fifth partial region 15 is defined as a second difference. A second absolute value of the second difference is greater than the third absolute value of the third difference Δa3. The second difference may be substantially the same as the first difference Δa1.
For example, the absolute value of the difference between the (0001) inter-plane spacing in the second region 31b and the (0001) inter-plane spacing in the fifth partial region 15 may be greater than the third absolute value of the third difference Δa3.
In the first sample SPL1, the first absolute value of the first difference Δa1 is about 0.005 nm. In the embodiment, the first absolute value of the first difference Δa1 may be 0.003 nm or more. In the first sample SPL1, the third absolute value of the third difference Δa3 is less than or equal to 0.0001 nm. In the embodiment, the third absolute value of the third difference Δa3 may be less than 0.001 nm. In the embodiment, the third absolute value of the third difference Δa3 may be 0.0005 nm or less.
In the embodiment, for example, the first absolute value of the first difference Δa1 may be three times or more the third absolute value of the third difference Δa3. In one example, the first absolute value may be less than or equal to 1000 times the third absolute value.
In the embodiment, for example, the absolute value of the difference Δb1 between the (10-10) inter-plane spacing at the first position 14p and the (10-10) inter-plane spacing at the second position 14q is smaller than the first absolute value of the first difference Δa1 (see
In the embodiment, for example, the absolute value of the difference Δb3 between the (10-10) inter-plane spacing at the third position 13p and the (10-10) inter-plane spacing at the fourth position 13q is smaller than the first absolute value of the first difference Δa1 (see
These figures illustrate evaluation results of the second sample SPL2. The vertical axes are the inter-plane spacing LS.
In the first sample SPL1 described above, a part of the semiconductor layer is removed by dry etching to form a recess, and then an alkali wet treatment is performed. On the other hand, in the second sample SPL2, the above-mentioned alkali wet treatment is omitted.
As shown in
In such a second sample SPL2, the (10-10) inter-plane spacing in the fourth partial region 14 is, for convenience, the (10-10) inter-plane spacing at the first position 14p. In such a second sample SPL2, the (10-10) inter-plane spacing in the third partial region 13 is conveniently set to the (10-10) inter-plane spacing at the third position 13p.
In the second sample SPL2, the first difference Δa1 between the (10-10) inter-plane spacing in the first region 31a and the (10-10) inter-plane spacing in the fourth partial region 14 is approximately 0.002. In the second sample SPL2, the third difference Δa3 between the (10-10) inter-plane spacing in the third region 31c and the (10-10) inter-plane spacing in the third partial region 13 is about 0.001 nm. Therefore, also in the second sample SPL2, the first absolute value of the first difference Δa1 is larger than the third absolute value of the third difference Δa3. Therefore, it is considered that high mobility and high threshold values can be obtained.
However, in the second sample SPL2, the difference between the first difference Δa1 and the third difference Δa3 is small.
As already explained, in the first sample SPL1, the first difference Δa1 is about 0.005 nm, the third difference Δa3 is 0.0001 nm or less, and the difference between these values is large. In the first sample SPL1, higher mobility can be obtained compared to the second sample SPL2. Higher threshold values are stably obtained. In the embodiment, the first absolute value of the first difference Δa1 is preferably 0.002 nm or more. In the embodiment, the third absolute value of the third difference Δa3 is preferably less than 0.001 nm. The third absolute value of the third difference Δa3 is more preferably 0.0005 nm or less.
As shown in
As described above, in the second sample SPL2, the (10-10) inter-plane spacing greatly differs between the first position 14p and the second position 14q. In the second sample SPL2, the crystal quality in the fourth partial region 14 is considered to be lower than the crystal quality in the fourth partial region 14 in the first sample SPL1.
As shown in
As described above, in the second sample SPL2, the (10-10) inter-plane spacing greatly differs between the third position 13p and the fourth position 13q. In the second sample SPL2, the crystal quality in the third partial region 13 is considered to be lower than the crystal quality in the third partial region 13 in the first sample SPL1.
The inter-plane spacing (lattice spacing) as described above is obtained by, for example, optimizing the conditions of dry etching and wet etching at the time of forming the recess, the conditions of forming the compound member 31, and the like. For example, by setting the condition of the dry etching to low power, roughness of the surface after the dry etching is suppressed, and the inter-plane spacing as in the first sample SPL1 is easily obtained. For example, by optimizing the conditions of the wet etching, high flatness can be obtained, and the inter-plane spacing as in the first sample SPL1 can be easily obtained. By optimizing the temperature, the flow rate of the raw material gas, and the like in the formation of the compound member 31, the inter-plane spacing as in the first sample SPL1 is easily obtained.
These conditions may be optimized in consideration of characteristics unique to each of the dry etching apparatus, the wet etching apparatus, and the film forming apparatus. For example, by measuring the lattice spacing of a sample produced by changing the conditions of each apparatus, it is possible to determine appropriate conditions in each apparatus.
In the embodiment, the ratio of the third absolute value of the third difference Δa3 to the (10-10) inter-plane spacing in the third partial region 13 may be, for example, 0.001 or less. By the third difference Δa3 being small, for example, high crystallinity can be obtained in the third partial region 13. High mobility can be obtained.
In the embodiment, the first absolute value of the first difference Δa1 may be two times or more the third absolute value of the third difference Δa3. The first absolute value may be 50 times or less the third absolute value.
As shown in
The first region 31a includes a first region face 31aF facing the fourth partial region 14. In the embodiment, the first region face 31aF may be a nonpolar face or a semipolar face. The first region face 31aF may be, for example, an a-plane or an m-plane.
As shown in
The first electrode 51 is electrically connected to the first semiconductor portion 21, for example. The second electrode 52 is electrically connected to the second semiconductor portion 22, for example.
As shown in
In the embodiment, the thickness of the second semiconductor layer 20 along the second direction D2 may be, for example, not less than 10 nm and not more than 60 nm. It is easy to obtain the carrier region 10C being stable.
As shown in
As shown in
The first insulating member 41 includes, for example, at least one selected from the group consisting of silicon and aluminum, and at least one selected from the group consisting of oxygen and nitrogen. The first insulating member 41 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.
As shown in
On the other hand, the first region 31a includes a first region face 31aF facing the fourth partial region 14. An angle between a plane (for example, the X-Y plane) perpendicular to the second direction D2 and the first region face 31aF is defined as a first angle θ1. An angle between the plane and the first intermediate region face 31pF is defined as a second angle θ2. The first angle θ1 is larger than the second angle θ2. By the second angle θ2 being small and the first intermediate region face 31pF being inclined, for example, a high threshold voltage can be easily obtained.
For example, the first angle θ1 is not less than 88 degrees and mot more than 90 degrees. For example, the second angle θ2 may be not less than 30 degrees and not more than 60 degrees.
As shown in
In embodiments, information regarding length and thickness is obtained from electron microscopy images and the like. Information regarding the composition of the material can be obtained by SIMS (Secondary Ion Mass Spectrometry), EDX (Energy dispersive X-ray spectroscopy), or the like. Information regarding the lattice length such as the inter-plane spacing can be obtained by electron diffraction, X-ray diffraction, or an electron microscope image.
Embodiments may include the following Technical proposals:
A semiconductor device, comprising:
The semiconductor device according to Technical proposal 1, wherein
The semiconductor device according to Technical proposal 1 or 2, wherein
The semiconductor device according to any one of Technical proposals 1-3, wherein
The semiconductor device according to any one of Technical proposals 1-3, wherein
The semiconductor device according to any one of Technical proposals 1-4, wherein
The semiconductor device according to any one of Technical proposals 1-5, wherein
The semiconductor device according to any one of Technical proposals 1-6, wherein
The semiconductor device according to any one of Technical proposals 1-7, wherein
The semiconductor device according to any one of Technical proposals 1-9, wherein
The semiconductor device according to Technical proposal 10, wherein
The semiconductor device according to any one of Technical proposals 1-11, further comprising:
The semiconductor device according to any one of Technical proposals 1-3, wherein
The semiconductor device according to any one of Technical proposals 1-13, wherein
The semiconductor device according to any one of Technical proposals 1-13, wherein
The semiconductor device according to any one of Technical proposals 1-15, wherein
The semiconductor device according to any one of Technical proposals 1-16, wherein
The semiconductor device according to any one of Technical proposals 1-17, wherein
The semiconductor device according to any one of Technical proposals 1-18, wherein
The semiconductor device according to Technical proposal 19, wherein
According to the embodiment, a semiconductor device with improved characteristics can be provided.
In the specification of the application, “perpendicular” and “parallel” refer to not only strictly perpendicular and strictly parallel but also include, for example, the fluctuation due to manufacturing processes, etc. It is sufficient to be substantially perpendicular and substantially parallel.
Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in the semiconductor device such as electrodes, semiconductor layers, compound members, insulating members, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.
Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.
Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.
Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-192904 | Nov 2023 | JP | national |
