Patent Application
20240290861
This application claims the benefit of priority to Japanese Patent Application No. 2023-028476, filed on Feb. 27, 2023, the entire contents of which are incorporated herein by reference.
An embodiment of the present invention relates to a semiconductor device using an oxide semiconductor for a channel.
In recent years, a semiconductor device in which an oxide semiconductor is used for a channel instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been developed (for example, Japanese laid-open patent publication No. 2021-141338, Japanese laid-open patent publication No. 2014-099601, Japanese laid-open patent publication No. 2021-153196, Japanese laid-open patent publication No. 2018-006730, Japanese laid-open patent publication No. 2016-184771, and Japanese laid-open patent publication No. 2021-108405). The semiconductor device including such an oxide semiconductor can be formed with a simple structure and a low-temperature process, similar to a thin film transistor containing amorphous silicon. The semiconductor device containing the oxide semiconductor is known to have higher field-effect mobility than the semiconductor device containing amorphous silicon.
In the semiconductor device in which the oxide semiconductor is used for the channel, an electrical characteristic may vary due to electrons or holes being trapped in an insulating layer arranged above or below an oxide semiconductor layer in a stress test. In particular, there is a problem in that the electrical characteristics of the semiconductor device are shifted in a negative voltage direction by a reliability test in which a negative stress voltage is applied to a gate electrode of the semiconductor device while the semiconductor device is irradiated with light.
A semiconductor device according to an embodiment of the present invention includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.
Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that can be easily conceived by a person skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. For the sake of clarity of description, the drawings may be schematically represented with respect to widths, thicknesses, shapes, and the like of the respective portions in comparison with actual embodiments. However, the shape shown is merely an example and does not limit the interpretation of the present invention. In this specification and each of the drawings, the same symbols are assigned to the same components as those described previously with reference to the preceding drawings, and a detailed description thereof may be omitted as appropriate.
In the embodiments of the present invention, a direction from a substrate to an oxide semiconductor layer is referred to as “on” or “above”. Reversely, a direction from the oxide semiconductor layer to the substrate is referred to as “under” or “below”. As described above, for convenience of explanation, although the phrase “above (on)” or “below (under)” is used for explanation, for example, a vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a different direction from that shown in the drawing. In the following description, for example, the expression “the oxide semiconductor layer on the substrate” merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Above or below means a stacking order in a structure in which multiple layers are stacked, and in the case where it is expressed as a pixel electrode above a transistor, it may be a positional relationship where the transistor and the pixel electrode do not overlap each other in a plan view. On the other hand, in the case where it is expressed as a pixel electrode vertically above a transistor, it means a positional relationship where the transistor and the pixel electrode overlap each other in a plan view.
In this specification, the terms “film” and “layer” can optionally be interchanged each other.
“Display device” refers to a structure configured to display an image using electro-optic layers. For example, the term display device may refer to a display panel including the electro-optic layer, or it may refer to a structure in which other optical members (for example, polarizing member, backlight, touch panel, or the like) are attached to a display cell. The “electro-optic layer” can include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, as long as there is no technical contradiction. Therefore, although the embodiments described later will be described by exemplifying a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as the display device, the structure in the present embodiment can be applied to a display device including the other electro-optic layers described above.
The expressions “α includes A, B, or C”, “α includes any of A, B, or C”, and “α includes one selected from a group consisting of A, B, and C” do not exclude the case where α includes multiple combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.
In addition, the following embodiments may be combined with each other as long as there is no technical contradiction.
An object of an embodiment of the present invention is to suppress variation in electrical characteristics of a semiconductor device before and after a stress test.
A semiconductor device according to an embodiment of the present invention will be described with reference to
A configuration of a semiconductor device 10 according to an embodiment of the present invention will be described with reference to
As shown in
The gate electrode 105 is arranged on the substrate 100. The gate insulating layers 110 and 120 are arranged on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is arranged on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is arranged on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The oxide semiconductor layer 140 is patterned. Part of the metal oxide layer 130 extends outside the pattern of the oxide semiconductor layer 140 beyond the end portion of the oxide semiconductor layer 140. However, the metal oxide layer 130 may be patterned in the same planar shape as the oxide semiconductor layer 140.
The gate electrode 105 may be referred to as a “first gate electrode”. The gate insulating layers 110 and 120 and the metal oxide layer 130 may be collectively referred to as a “first insulating layer”. In this case, the gate insulating layer 110 may be referred to as a “first layer”, the gate insulating layer 120 may be referred to as a “second layer”, and the metal oxide layer 130 may be referred to as a “third layer”. As will be described in detail later, the gate insulating layer 110 is a layer containing silicon and nitrogen. The gate insulating layer 120 is a layer containing silicon and oxygen. The metal oxide layer 130 is a layer containing aluminum and oxygen.
A thickness of the gate insulating layer 110 is 10 nm or more and 190 nm or less, 10 nm or more and 150 nm or less, or 10 nm or more and 100 nm or less. A thickness of the gate insulating layer 120 is 10 nm or more and 100 nm or less, 10 nm or more and 75 nm or less, or 10 nm or more and 50 nm or less. A total thickness of the gate insulating layers 110 and 120 is 300 nm or less, 200 nm or less, or 150 nm or less. As will be described in detail later, by setting thicknesses of the gate insulating layers 110 and 120 and the metal oxide layer 130 within the ranges described above, reliability of the semiconductor device 10 in the stress test is improved.
The thickness of the metal oxide layer 130 is 1 nm or more and 10 nm or less, 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. A ratio of the thickness of the metal oxide layer 130 with respect to a thickness of the oxide semiconductor layer 140 is 1/30 or more and ⅔ or less, 1/30 or more and 4/30 or less, or 1/30 or more and 1/10 or less.
In other words, the gate insulating layer 120 is arranged between the substrate 100 and the metal oxide layer 130. In other words, the metal oxide layer 130 is in contact with each of the gate insulating layer 120 and the oxide semiconductor layer 140 between the gate insulating layer 120 and the oxide semiconductor layer 140. Although details will be described later, the gate insulating layer 120 is an insulating layer containing oxygen. Specifically, the gate insulating layer 120 is an insulating layer having a function of releasing oxygen by heat treatment at 600° C. or lower. Oxygen released from the gate insulating layer 120 by the heat treatment repairs oxygen vacancies formed in the oxide semiconductor layer 140.
In the present embodiment, no semiconductor layer or oxide semiconductor layer is arranged between the metal oxide layer 130 and the substrate 100.
In the present embodiment, although a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is exemplified, the configuration is not limited to this configuration. Another layer may be arranged between the gate insulating layer 120 and the metal oxide layer 130. Another layer may be arranged between the metal oxide layer 130 and the oxide semiconductor layer 140.
The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is arranged between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. A surface of main surfaces of the oxide semiconductor layer 140 that is in contact with the gate insulating layer 150 is referred to as an upper surface 141. A surface of the main surfaces of the oxide semiconductor layer 140 that is in contact with the metal oxide layer 130 is referred to as an lower surface 142. A surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are arranged above the gate insulating layer 150 and the gate electrode 160. Openings 171 and 173 that reach the oxide semiconductor layer 140 are arranged in the insulating layers 170 and 180. The source electrode 201 is arranged inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is arranged inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.
The gate electrode 160 may be referred to as a “second gate electrode”. The gate insulating layer 150 may be referred to as a “second insulating layer”.
The gate electrode 105 has a function as a bottom-gate of the semiconductor device 10 and a function as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities that diffuse from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom-gate. The metal oxide layer 130 is a layer containing a metal oxide containing aluminum as the main component, and has a function as a gas barrier property film for shielding a gas such as oxygen and hydrogen. Furthermore, the metal oxide layer 130 has a function of suppressing that holes move from the oxide semiconductor layer 140 to the gate insulating layer 120 in a stress tests.
The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region that overlaps the gate electrode 160 in a plan view. The second region A2 is a region that does not overlap the gate electrode 160 but overlaps the oxide semiconductor layer 140 in a plan view. The third region A3 is a region that does not overlap both the gate electrode 160 and the oxide semiconductor layer 140 in a plan view.
Although a configuration that a thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is the same as a thickness of the gate insulating layer 150 in the first region A1, the configuration is not limited to this configuration. For example, the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 may be smaller than the thickness of the gate insulating layer 150 in the first region A1. In other words, the thickness of the gate insulating layer 150 in the region not overlapping the gate electrode 160 in a plan view may be smaller than the thickness of the gate insulating layer 150 in the region overlapping the gate electrode 160.
The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D are regions corresponding to the second region A2. The channel region CH is a region corresponding to the first region A1. In a plan view, an end portion in the channel region CH is consistent with an end portion of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH have semiconductor properties. Each of the oxide semiconductor layer 140 in the source region S and the drain region D has conductive properties. That is, carrier concentrations of the oxide semiconductor layer 140 in the source region S and the drain region D are higher than a carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 contacts the oxide semiconductor layer 140 in the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may be a single-layer structure or a stacked structure.
The gate electrode 160 has a function as a top-gate of the semiconductor device 10 and a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has a function as a gate insulating layer for the top-gate. The gate insulating layer 150 may has a function of releasing oxygen by a heat treatment in a manufacturing process similar to the gate insulating layer 120. The insulating layers 170 and 180 insulate the gate electrode 160 and the source-drain electrode 200 and have a function of reducing parasitic capacitance therebetween. Operations of the semiconductor device 10 are controlled mainly by a voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case of using the gate electrode 105 simply as a light-shielding film, a specific voltage is not supplied to the gate electrode 105, and a potential of the gate electrode 105 may be in a floating. That is, the gate electrode 105 may simply be referred to as a “light-shielding film.” In the case mentioned above, the shielding film may be an insulator.
In the present embodiment, although a configuration using a dual-gate transistor in which the gate electrode is arranged both above and below the oxide semiconductor layer as the semiconductor device 10 is exemplified, the configuration is not limited to this configuration. For example, a bottom-gate transistor in which the gate electrode is arranged only below the oxide semiconductor layer or a top-gate transistor in which the gate electrode is arranged only above the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is merely an embodiment, and the present invention is not limited to the above configuration.
Referring to
In the present embodiment, although a configuration in which all of the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130 is exemplified, the present invention is not limited to this configuration. For example, part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, all of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered with the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered with the metal oxide layer 130. That is, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered with the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.
In the present embodiment, although a configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are arranged in the gate insulating layer 150 is exemplified, the configuration is not limited to this configuration. The gate insulating layer 150 may be patterned in a shape that is different from the shape in which the openings 171 and 173 are arranged. For example, the gate insulating layer 150 may be patterned to expose all or part of the oxide semiconductor layer 140 in the source region S and the drain region D. That is, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.
In
A rigid substrate having translucency, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like, is used as the substrate 100. In the case where the substrate 100 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acryl substrate, a siloxane substrate, or a fluororesin substrate is used as the substrate 100. In the case where the substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100. In particular, in the case where the semiconductor device 10 is a top-emission display, since the substrate 100 does not need to be transparent, impurities that deteriorate the translucency of the substrate 100 may be used. In the case where the semiconductor device 10 is used for an integrated circuit that is not a display device, a substrate without translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless substrate is used as the substrate 100.
Common metal materials are used for the light-shielding layer 105, the gate electrode 160, and the source-drain electrode 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as these members. The materials described above may be used in a single layer or a stacked layer as the light-shielding layer 105, the gate electrode 160, and the source-drain electrode 200. A material other than the metal materials described above may be used as a light-shielding layer instead of the gate insulating layer 105 if conductivity is not required. For example, a black matrix such as a black resin may be used as the light-shielding layer. The light-shielding layer 105 may be a single-layer structure or a stacked structure. For example, the light-shielding layer 105 may be a stacked structure of a red color filter, a green color filter, and a blue color filter.
Common insulating materials are used as the gate insulating layer 110, 120, and the insulating layers 170 and 180. For example, inorganic insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) are used as the gate insulating layer 120 and the insulating layer 180. Inorganic insulating layers such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx), and aluminum nitride oxide (AlNxOy) are used as the gate insulating layer 110 and the insulating layer 170. However, an inorganic insulating layer such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum oxynitride (AlOxNy) may be used as the insulating layer 170. An inorganic insulating layer such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx), and aluminum nitride oxide (AlNxOy) may be used as the insulating layer 180.
Among the insulating layers described above, the insulating layer containing oxygen is used as the gate insulating layer 150. For example, an inorganic insulating layer such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) are used as the gate insulating layer 150.
An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. That is, an oxide insulating layer containing excess oxygen is used as the gate insulating layer 120. For example, a temperature of heat treatment at which the gate insulating layer 120 releases oxygen is 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, for example, the gate insulating layer 120 releases oxygen at a heat treatment temperature performed in a manufacturing process of the semiconductor device 10 in the case where a glass substrate is used as the substrate 100. Similar to the gate insulating layer 120, an insulating layer having a function of releasing oxygen by heat treatment may be used for at least one of the insulating layers 170 and 180.
An insulating layer with few defects is used as the gate insulating layer 150. For example, in the case where a composition ratio of oxygen in the gate insulating layer 150 is compared with a composition ratio of oxygen in an insulating layer (hereinafter referred to as “other insulating layer”) having a composition similar to that of the gate insulating layer 150, the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in that other insulating layer. Specifically, in the case where silicon oxide (SiOx) is used for each of the gate insulating layer 150 and the insulating layer 180, the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is close to the stoichiometric ratio of silicon oxide as compared with the composition ratio of oxygen in the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by the electron-spin resonance (ESR) may be used as the gate insulating layer 150.
SiOxNyand AlOxNy described above are a silicon compound and an aluminum compound containing nitrogen (N) in a ratio (x>y) smaller than that of oxygen (O). SiNxOyand AlNxOy are a silicon compound and an aluminum compound containing oxygen in a ratio (x>y) smaller than that of nitrogen.
A metal oxide containing aluminum as the main component is used as the metal oxide layer 130. For example, an inorganic insulating layer such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx) is used as the metal oxide layer 130. The “metal oxide layer 130 containing aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer 130 is 1% or more of the total amount of the metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the total amount of the metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.
A metal oxide having semiconductor properties may be used as the oxide semiconductor layer 140. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used as the oxide semiconductor layer 140. For example, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 may be used as the oxide semiconductor layer 140. However, the oxide semiconductor containing In, Ga, Zn and O used in the present embodiment is not limited to the above-described composition. An oxide semiconductor having a composition other than the above may be used as the oxide semiconductor. For example, an oxide semiconductor layer having a higher ratio of In than those described above may be used to improve mobility. On the other hand, in order to increase the bandgap and reduce the effect of photoirradiation, an oxide semiconductor layer having a larger ratio of Ga than those described above may be used.
For example, an oxide semiconductor containing two or more metals including indium (In) may be used as the oxide semiconductor layer 140 in which the ratio of In is larger than that described above. In this case, the ratio of indium with respect to the entire the oxide semiconductor layer 140 may be 50% or more. Gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids may be used as the oxide semiconductor layer 140 in addition to indium. Elements other than those described above may be used as the oxide semiconductor layer 140.
Other elements may be added to the oxide semiconductor containing In, Ga, Zn, and O as the oxide semiconductor layer 140, and metal elements such as Al, Sn may be added. In addition to the above oxide semiconductor, an oxide semiconductor (IGO) containing In, Ga, an oxide semiconductor (IZO) containing In, Zn, an oxide semiconductor (ITZO) containing In, Sn, Zn, an oxide semiconductor containing In, W may be used as the oxide semiconductor layer 140.
In the case where the ratio of the indium element is large, the oxide semiconductor layer 140 is likely to crystallize. As described above, in the oxide semiconductor layer 140, the oxide semiconductor layer 140 having a polycrystalline structure can be obtained by using a material in which the ratio of the indium element with respect to the total metal element is 50% or more. The oxide semiconductor layer 140 preferably contains gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not inhibited by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.
Although a detailed method of manufacturing the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed using a sputtering method. A composition of the oxide semiconductor layer 140 formed by the sputtering method depends on a composition of a sputtering target. Even though the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target is substantially consistent with the composition of the oxide semiconductor layer 140. In this case, the composition of the metal element of the oxide semiconductor layer 140 can be specified based on the composition of the metal element of the sputtering target.
In the case where the oxide semiconductor layer 140 has a polycrystalline structure, a composition of the oxide semiconductor layer may be specified using X-ray diffraction (X-ray Diffraction: XRD). Specifically, a composition of the metal element of the oxide semiconductor layer can be specified based on the crystalline structure and the lattice constant of the oxide semiconductor layer obtained by the XRD method. Furthermore, the composition of the metal element of the oxide semiconductor layer 140 can also be identified using fluorescent X-ray analysis, Electron Probe Micro Analyzer (EPMA) analysis, or the like. However, the oxygen element contained in the oxide semiconductor layer 140 may not be specified by these methods because the oxygen element varies depending on the sputtering process conditions.
As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. The oxide semiconductor having a polycrystalline structure can be manufactured using a Poly-OS (Poly-crystalline Oxide Semiconductor) technique. In the following, the oxide semiconductor having the polycrystalline structure may be described as the Poly-OS when distinguished from the oxide semiconductor having the amorphous structure.
Electrical characteristics of the semiconductor device 10 will be described with reference to
In the semiconductor device 10, a silicon nitride film is used as the gate insulating layer 110, a silicon oxide film is used as the gate insulating layer 120, and a silicon oxide film is used as the gate insulating layer 150. The gate insulating layer 110 is denoted as “UC-SiN”. The gate insulating layer 120 is denoted as “SiO”. The gate insulating layer 150 is denoted as “GI-SiO”. Aluminum oxide is used as the metal oxide layer 130.
The thicknesses of the gate insulating layers 110 and 120 (SiO/UC-SiN Thickness) are 50 nm/100 nm, 100 nm/200 nm, or 200 nm/300 nm. The film thickness of the gate insulating layer 150 (GI-SiO Thickness) with respect to each of film thickness of the SiO/UC-SiN is 75 nm, 100 nm, 125 nm, or 150 nm.
Measurement conditions of the electrical characteristics shown in
The horizontal line of the solid line shown in
The reliability of the semiconductor device 10 will be described with reference to
Conditions for the PBTS test are as follows.
Conditions for the NBTIS test are as follows.
In
As shown in
As shown in
According to the present embodiment, the thickness of the gate insulating layer 110 containing silicon and nitrogen is 10 nm or more and 190 nm or less, the thickness of the gate insulating layer 120 containing silicon and oxygen is 10 nm or more and 100 nm or less, the total thickness of the gate insulating layers 110 and 120 is 200 nm or less, and the thickness of the metal oxide layer 130 containing aluminum and oxygen is 1 nm or more and 10 nm or less, and thus, dramatic improvement has been confirmed particularly in the NBTIS test.
In the NBTIS test, −20 V gate voltage is applied to the gate electrodes 105 and 160 as described above. Therefore, holes generated in the oxide semiconductor layer 140 by the light irradiation are attracted to either of the gate electrodes 105 and 160. Here, in the case where the thicknesses of the gate insulating layers 110 and 120 are small, an influence of an electric field generated by the gate electrode 105 on the oxide semiconductor layer 140 is relatively strong. As a result, it is considered that most of the holes generated in the oxide semiconductor layer 140 are attracted to the gate electrode 105. In a conventional transistor, a hole is trapped by a gate insulating layer in a bottom-gate side, which causes a negative shift in a threshold voltage of a transistor characteristic in the NBTIS test. On the other hand, in the present embodiment, since the metal oxide layer 130 is arranged below the oxide semiconductor layer 140, it is difficult for the holes generated in the oxide semiconductor layer 140 to reach the gate insulating layer 120, and it is considered that an amount of holes trapped in the gate insulating layer 120 is reduced.
A method for manufacturing a semiconductor device 10 according to an embodiment of the present invention will be described with reference to
As shown in
Using silicon nitride as the gate insulating layer 110 allows the gate insulating layer 110 to block impurities that diffuse, for example, from the substrate 100 toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide having a physical property of releasing oxygen by heat treatment.
As shown in
For example, the thickness of the oxide semiconductor layer 140 is 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 15 nm or more and 40 nm or less. In the present embodiment, the thickness of the oxide semiconductor layer 140 is 15 nm. The oxide semiconductor layer 140 before the heat treatment (OS anneal) described later is amorphous.
In the case where the oxide semiconductor layer 140 is crystallized by the OS anneal described later, the oxide semiconductor layer 140 after the deposition and before the OS anneal is preferably in an amorphous state (a state of low crystalline components of the oxide semiconductor are fewer). That is, deposition conditions of the oxide semiconductor layer 140 are preferred to be a condition such that the oxide semiconductor layer 140 immediately after the deposition does not crystallize as much as possible. For example, in the case where the oxide semiconductor layer 140 is deposited by the sputtering method, the oxide semiconductor layer 140 is deposited in a state where temperature of the object to be deposited (the substrate 100 and structures formed thereon) is controlled.
In the case where the deposition is performed on the object to be deposited by the sputtering method, ions generated in the plasma and atoms recoiled by a sputtering target collide with the object to be deposited. Therefore, the temperature of the object to be deposited rises with the deposition process. When the temperature of the object to be deposited rises during the deposition process, microcrystals are occurred in the oxide semiconductor layer 140 immediately after the deposition process. There is a possibility that the microcrystals inhibit crystallization by subsequent OS anneal. For example, in order to control the temperature of the object to be deposited as described above, deposition may be performed while cooling the object to be deposited. For example, the object to be deposited may be cooled from a surface opposite to a deposited surface so that the temperature of the deposited surface of the object to be deposited (hereinafter, referred to as “deposition temperature”) is 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. As described above, depositing the oxide semiconductor layer 140 while cooling the object to be deposited makes it possible to deposit the oxide semiconductor layer 140 with few crystalline components in a state immediately after the deposition. An oxygen partial pressure in the deposition conditions of the oxide semiconductor layer 140 is 2% or more and 20% or less, 3% or more and 15% or less, or 3% or more and 10% or less.
As shown in
The pattern of the oxide semiconductor layer 140 is formed, and then heat treatment (OS anneal) is performed on the oxide semiconductor layer 140 (“Annealing OS” in step S1004 of
As shown in
Heat treatment (oxidation anneal) for supplying oxygen to the oxide semiconductor layer 140 is performed in a state where the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 (“Annealing for Oxidation” in step S1006 of
In order to increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer containing aluminum as the main component may be formed on the gate insulating layer 150 by the sputtering method, and then oxidation annealing may be performed in that state. The use of aluminum oxide, which has a high barrier property, as the metal oxide layer makes it possible to suppress the oxygen implanted into the gate insulating layer 150 at the time of oxidation annealing from being diffused outward. Oxygen implanted into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140 by forming the metal oxide layer and the oxidation annealing.
As shown in
As shown in
In the oxide semiconductor layer 140 in the second region A2 that does not overlap the gate electrode 160, oxygen defects are generated by ion implantation. The oxide semiconductor layer 140 in the second region A2 is reduced in resistance by trapping hydrogen in the generated oxygen defects. On the other hand, in the oxide semiconductor layer 140 in the first region A1 overlapping the gate electrode 160, impurities are not implanted, so that no oxygen defects are generated and resistance in the first region A1 is not lowered. Through the above steps, the channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and the source region S and the drain region D are formed in the oxide semiconductor layer 140 in the second region A2.
Dangling bond defects DB are generated in the gate insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3 by the ion implantation. A location and an amount of the dangling bond defects DB can be controlled by adjusting process parameters (for example, dose amount, acceleration voltage, plasma power, and the like) of the ion implantation. In order to sufficiently decrease the resistance values of the oxide semiconductor layer 140 in the source region S and the drain region D, impurity concentration in a vicinity of an upper surface of the oxide semiconductor layer 140 can be adjusted to 1×1019/cm3 or more by adjusting the process parameters. On the other hand, in the case where an insulating layer containing silicon and nitrogen is used as the gate insulating layer 110, when impurities are implanted into the gate insulating layer 110 at a high concentration, hydrogen generated in the gate insulating layer 110 reaches the oxide semiconductor layer 140, which adversely affects the electrical characteristics of the semiconductor device 10. Therefore, impurity concentration in a vicinity of an upper surface of the gate insulating layer 110 can be adjusted to 1×1019/cm3 or less.
As shown in
As shown in
A display device using a semiconductor device according to an embodiment of the present invention will be described with reference to
A seal region 24 where the seal portion 310 is arranged is a region surrounding the liquid crystal region 22. The FPC 330 is arranged in a terminal region 26. The terminal region 26 is a region where the array substrate 300 is exposed from the counter substrate 320 and is arranged outside the seal region 24. Outside the seal region 24 means regions outside the region where the seal portion 310 is arranged and a region surrounded by the seal portion 310. The IC chip 340 is arranged on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.
A source wiring 304 extends from the source driver circuit 302 in the direction D1 and is connected to the plurality of pixel circuits 301 arranged in the direction D1. A gate wiring 305 extends from the gate driver circuit 303 in the direction D2 and is connected to the plurality of pixel circuits 301 arranged in the direction D2.
A terminal portion 306 is arranged in the terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by the connection wiring 307. Since the FPC 330 is connected to the terminal portion 306, an external device which is connected to the FPC 330 and the display device 20 are connected, and each pixel circuit 301 arranged in the display device 20 is driven by a signal from the external device.
The semiconductor device 10 shown in the first embodiment is used as a transistor included in the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303.
An insulating layer 360 is arranged on the source electrode 201 and the drain electrode 203. A common electrode 370 arranged in common for the plurality of pixels is arranged on the insulating layer 360. An insulating layer 380 is arranged on the common electrode 370. An opening 381 is arranged in the insulating layers 360 and 380. A pixel electrode 390 is arranged on the insulating layer 380 and within the opening 381. The pixel electrode 390 is connected to the drain electrode 203.
A display device using a semiconductor device according to an embodiment of the present invention will be explained with reference to
As shown in
In the second embodiment and third embodiment, although the configuration in which the semiconductor device explained in the first embodiment was applied to a liquid crystal display device and an organic EL display device was exemplified, the semiconductor device may be applied to display devices (for example, a self-luminous display device or an electronic paper display device other than an organic EL display device) other than these display devices. In addition, the semiconductor device described above can be applied without any particular limitation from a small sized display device to a large sized display device.
Each of the embodiments described above as an embodiment of the present invention can be appropriately combined and implemented as long as no contradiction is caused. In addition, the addition, deletion, or design change of components, or the addition, deletion, or condition change of processes as appropriate by those skilled in the art based on a semiconductor device and a display device of each embodiment are also included in the scope of the present invention as long as they are provided with the gist of the present invention.
Further, it is understood that, even if the effect is different from those provided by each of the above-described embodiments, the effect obvious from the description in the specification or easily predicted by persons ordinarily skilled in the art is apparently derived from the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-028476 | Feb 2023 | JP | national |
