SEMICONDUCTOR DEVICE

Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The first semiconductor region includes a first region. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction. The third semiconductor region is located between the first and second semiconductor regions. A length in the second direction of a lower portion of the third semiconductor region is greater than a length in the second direction of an upper portion of the third semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the gate electrode. The fifth semiconductor region is located on the second semiconductor region.

Description

Claims

1. A semiconductor device, comprising: a first electrode;a first semiconductor region located on the first electrode, the first semiconductor region including a first region of a first conductivity type;a gate electrode located on the first semiconductor region with a gate insulating layer interposed;a second semiconductor region facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the first semiconductor region, the second semiconductor region being of a second conductivity type;a third semiconductor region located between the first semiconductor region and the second semiconductor region in the first direction, the third semiconductor region being of the second conductivity type, a length in the second direction of a lower portion of the third semiconductor region being greater than a length in the second direction of an upper portion of the third semiconductor region;a fourth semiconductor region located between the third semiconductor region and the gate electrode, the fourth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the fourth semiconductor region being greater than a first-conductivity-type impurity concentration of the first region;a fifth semiconductor region located on the second semiconductor region, the fifth semiconductor region being of the first conductivity type; anda second electrode located on the second and fifth semiconductor regions.

2. The device according to claim 1, wherein the second semiconductor region includes: a first portion separated from the gate insulating layer in the second direction;a second portion located between the gate insulating layer and the first portion and positioned on the fourth semiconductor region, anda second-conductivity-type impurity concentration of the second portion is less than a second-conductivity-type impurity concentration of the first portion.

3. The device according to claim 2, wherein the second-conductivity-type impurity concentration of the second portion is less than a second-conductivity-type impurity concentration of the third semiconductor region.

4. The device according to claim 1, wherein the third semiconductor region includes: a third portion separated from the gate insulating layer in the second direction; anda fourth portion located between the gate insulating layer and the third portion and positioned on the fourth semiconductor region, anda first-conductivity-type impurity concentration of the fourth portion is greater than a first-conductivity-type impurity concentration of the third portion.

5. The device according to claim 4, wherein the third semiconductor region further includes a fifth portion,the third portion and the fourth portion are positioned between the gate insulating layer and the fifth portion in the second direction, anda first-conductivity-type impurity concentration of the fifth portion is greater than the first-conductivity-type impurity concentration of the third portion.

6. The device according to claim 1, wherein the first semiconductor region further includes a second region of the second conductivity type, andthe first region and the second region are alternately arranged in the second direction.

7. The device according to claim 6, wherein the third semiconductor region contacts one of a plurality of the second regions, andthe fourth semiconductor region contacts one of a plurality of the first regions.

8. The device according to claim 1, wherein a lower end of the third semiconductor region is positioned lower than a lower end of the gate electrode.

9. The device according to claim 1, wherein a portion of the third semiconductor region is positioned under the gate insulating layer.