The present disclosure relates to a semiconductor device.
As a type of semiconductor laser, a surface-emitting laser such as a vertical cavity surface emitting laser (VCSEL) is known. In general, in a light emitting device utilizing a surface-emitting laser, a plurality of light emitting elements is provided in a two-dimensional array on a front surface or a back surface of a substrate.
There are cases where a semiconductor device such as a light emitting device includes a lower wiring, an insulation film, and an upper wiring in this order on a substrate. For example, a light emitting device may be manufactured by forming a plurality of light emitting elements on a certain substrate, forming a lower wiring, an insulation film, and an upper wiring in this order on another substrate, and mounting the former substrate on the latter substrate.
For such a semiconductor device, it is possible to reduce parasitic capacitance between the lower wiring and the upper wiring by providing a cavity in the insulation film between the lower wiring and the upper wiring. However, it is difficult to provide a cavity in the insulation film. Therefore, it is desirable that the parasitic capacitance between these wirings can be easily reduced.
Therefore, the present disclosure provides a semiconductor device capable of easily reducing parasitic capacitance between wirings.
A semiconductor device according to a first aspect of the present disclosure includes a first substrate, a lower wiring provided on the first substrate, a plurality of upper wirings provided on the lower wiring via an insulation film, and a second substrate provided on the upper wirings via a plurality of elements, in which the upper wirings include a first wiring and a second wiring adjacent to each other in a first direction, the elements on the first wiring and the elements on the second wiring are connected in series to each other, and a first opening is provided in the lower wiring or provided so as to be sandwiched between the lower wirings in a second direction different from the first direction, or a second opening is provided in the upper wirings or provided so as to be sandwiched between the upper wirings in the second direction. Hence, for example, it is possible to easily reduce parasitic capacitance between the wirings by providing the first opening in the lower wiring or between the lower wirings, or by providing the second opening in the upper wirings or between the upper wirings.
Furthermore, in the first aspect, the elements on the first wiring may be connected in parallel to each other, and the elements on the second wiring may be connected in parallel to each other. Hence, for example, it is possible to connect the elements in parallel on the first wiring and on the second wiring, while connecting the elements in series between the first wiring and the second wiring.
Furthermore, in the first aspect, the elements may be light emitting elements provided on the second substrate. Hence, for example, it is possible to easily reduce parasitic capacitance between the wirings in a light emitting device.
Furthermore, in the first aspect, light emitted from the light emitting elements may pass through the second substrate from a lower surface to upper surface of the second substrate, and may be emitted from the second substrate. Hence, for example, it is possible to easily reduce parasitic capacitance between the wirings in a back-side emission type light emitting device.
Furthermore, in the first aspect, the lower wiring may be used such that current flows in the first direction, and the upper wirings may be used such that current flows in a direction opposite to the first direction. Hence, for example, it is possible to cause a magnetic field generated around the upper wirings and a magnetic field generated around the lower wiring to cancel each other out.
Furthermore, in the first aspect, an opening extending in the first direction may be provided as the first or second opening. Hence, for example, it is possible to implement a structure in which current easily flows in the first direction in the lower wiring even if the first opening is provided, or a structure in which current easily flows in the direction opposite to the first direction in the upper wirings even if the second opening is provided.
Furthermore, in the first aspect, a plurality of openings extending in the first direction and adjacent to each other in the second direction may be provided as the first or second openings. Hence, for example, it is possible to implement a structure in which current easily flows in the first direction in the lower wiring even if a plurality of openings is provided as the first openings, or a structure in which current easily flows in the direction opposite to the first direction in the upper wirings even if a plurality of openings is provided as the second openings.
Furthermore, in the first aspect, the lower wiring or the upper wirings may include a plurality of first parts extending in the first direction and a plurality of second parts extending in the second direction, and each of the plurality of openings may be provided between the first parts adjacent to each other in the second direction. Hence, for example, it is possible to implement a structure in which current easily flows in the first direction even if a plurality of openings is provided in one lower wiring, or a structure in which current easily flows in the direction opposite to the first direction even if a plurality of openings is provided in one upper wiring.
Furthermore, in the first aspect, a width of the upper wirings in the second direction may be the same as a width of the lower wiring in the second direction. Hence, for example, it is possible to cause a magnetic field generated around the upper wirings and a magnetic field generated around the lower wiring to suitably cancel each other out.
Furthermore, in the first aspect, a width of the upper wirings in the second direction may be wider than a width of the lower wiring in the second direction.
Hence, for example, it is possible to implement a structure suitable as compared with a case where the width of the upper wirings in the second direction is narrower than the width of the lower wiring in the second direction.
Furthermore, in the first aspect, a width of the upper wirings in the second direction may be 90% to 110% of a width of the lower wiring in the second direction. Hence, for example, it is possible to obtain substantially the same effect as in a case where these widths are the same.
Furthermore, in the first aspect, the first opening may be provided in the lower wiring or provided so as to be sandwiched between the lower wirings in the second direction, and the second opening may be provided in the upper wirings or provided so as to be sandwiched between the upper wirings in the second direction. Hence, for example, it is possible to increase a degree of freedom in designing the wiring as compared with a case where only either the first opening or the second opening is provided.
Furthermore, in the first aspect, the first opening may be provided at a position facing the upper wirings vertically, and the second opening may be provided at a position facing the lower wiring vertically. Hence, for example, it is possible to further reduce parasitic capacitance between the wirings.
Furthermore, in the first aspect, a plurality of openings extending in the first direction may be provided as the first opening, the lower wiring may include a plurality of first parts extending in the first direction and a plurality of second parts extending in the second direction, and each of the plurality of openings may be provided between the first parts adjacent to each other in the second direction. Hence, for example, it is possible to implement a structure in which current easily flows in the first direction in the lower wiring even if a plurality of openings is provided as the first openings.
Furthermore, in the first aspect, a plurality of openings extending in the first direction may be provided as the second openings, and each of the plurality of openings may be provided between the upper wirings adjacent to each other in the second direction. Hence, for example, it is possible to implement a structure in which current easily flows in a direction opposite to the first direction in the upper wirings even if a plurality of openings is provided as the second openings.
Furthermore, in the first aspect, a width of the first or second opening in the second direction may be one tenth or less of a width of the upper wirings in the second direction. Hence, for example, it is possible to further reduce parasitic capacitance between the wirings.
Furthermore, in the first aspect, the plurality of first parts may include first parts having different widths in the second direction. Hence, for example, it is possible to increase a degree of freedom in designing wirings as compared with a case where the widths of all the first parts in the second direction are the same.
Furthermore, in the first aspect, a plurality of openings disposed in a two-dimensional array may be provided as the first or second opening. Hence, for example, it is possible to reduce parasitic capacitance between the wirings by using a large number of openings.
Furthermore, in the first aspect, as the first or second opening, only one opening may be provided in the upper wirings or in the lower wiring, or only one opening may be provided so as to be sandwiched between the upper wirings in the second direction or between the lower wirings in the second direction. Hence, for example, it is possible to reduce parasitic capacitance between the wirings by using one opening.
Furthermore, in the first aspect, the first substrate may include a semiconductor substrate including silicon (Si), and the second substrate may include a semiconductor substrate including gallium (Ga) and arsenic (As). Hence, for example, it is possible to provide a circuit on an inexpensive Si substrate with the elements provided on a high-performance GaAs substrate.
Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings.
The distance measurement device in
The light emitting device 1 includes a light emission unit 11, a drive circuit 12, a power supply circuit 13, and a light-emitting side optical system 14. The imaging device 2 includes an image sensor 21, an image processing unit 22, and an imaging-side optical system 23. The control device 3 includes a distance measurement unit 31.
The light emission unit 11 emits laser light for irradiating the subject. As will be described later, the light emission unit 11 of the present embodiment includes a plurality of light emitting elements disposed in a two-dimensional array, and each light emitting element has a vertical-cavity surface-emitting laser (VCSEL) structure. The subject is irradiated with light emitted from these light emitting elements. As illustrated in
The drive circuit 12 is an electric circuit that drives the light emission unit 11. The power supply circuit 13 is an electric circuit that generates power supply voltage of the drive circuit 12. In the distance measurement device in
The light-emitting side optical system 14 includes various optical elements, and irradiates the subject with light from the light emission unit 11 via these optical elements. Similarly, the imaging-side optical system 23 includes various optical elements, and receives light from the subject via these optical elements.
The image sensor 21 receives the light from the subject via the imaging-side optical system 23, and converts the light into an electric signal by photoelectric conversion. The image sensor 21 is, for example, a charge-coupled device (CCD) sensor or a complementary metal-oxide semiconductor (CMOS) sensor. The image sensor 21 of the present embodiment converts the above-described electronic signal from an analog signal to a digital signal with analog to digital (A/D) conversion, and outputs an image signal as a digital signal to the image processing unit 22. Furthermore, the image sensor 21 of the present embodiment outputs a frame synchronization signal to the drive circuit 12, and the drive circuit 12 causes the light emission unit 11 to emit light at a timing corresponding to a frame period in the image sensor 21 on the basis of the frame synchronization signal.
The image processing unit 22 performs various types of image processing on the image signal output from the image sensor 21. The image processing unit 22 includes, for example, an image processing processor such as a digital signal processor (DSP).
The control device 3 controls various operations of the distance measurement device in
The distance measurement unit 31 measures the distance to the subject on the basis of the image signal output from the image sensor 21 and subjected to the image processing by the image processing unit 22. The distance measurement unit 31 employs, for example, a structured light (STL) method or a Time of Flight (ToF) method as a distance measurement method. The distance measurement unit 31 may further measure a distance between the distance measurement device and the subject for each portion of the subject on the basis of the above-described image signal to identify a three-dimensional shape of the subject.
A of
A of
In A of
The wiring 44 is provided on a front surface, back surface, inside, or the like of the mounting board 43, and electrically connects the LD chip 41 and the LDD board 42. The wiring 44 is, for example, a printed wiring provided on the front surface or back surface of the mounting board 43, or a via interconnection penetrating the mounting board 43.
B of
In B of
C of
In C of
Hereinafter, the light emitting device 1 of the present embodiment will be described as having the structure of the third example illustrated in C of
Hereinafter, the structure of the light emitting device 1 of the present embodiment will be described with reference to A of
As illustrated in A of
The substrate 51 is, for example, a semiconductor substrate such as a gallium arsenide (GaAs) substrate. In A of
The laminated film 52 includes a plurality of layers laminated on the front surface (lower surface) of the substrate 51. Examples of these layers include an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a light reflection layer, an insulation layer provided with a light exit window, and the like. The laminated film 52 includes a plurality of mesa parts M protruding in the −Z direction. Some of these mesa parts M are the plurality of light emitting elements 53.
The light emitting elements 53 are provided on a front surface of a substrate 52 as a part of the laminated film 52. The light emitting elements 53 of the present embodiment have a VCSEL structure and emit light in the +Z direction. As illustrated in
The anode electrodes 54 are formed on lower surfaces of the light emitting elements 53. The cathode electrodes 55 are formed on lower surfaces of the mesa parts M other than the light emitting elements 53, and extends from the lower surfaces of the mesa parts M to a lower surface of the laminated film 52 between the mesa parts M. Each of the light emitting elements 53 emits light when current flows between a corresponding anode electrode 54 and a corresponding cathode electrode 55.
The substrate 61 is, for example, a semiconductor substrate such as a silicon (Si) substrate. In A of
The GND wiring 64, the insulation film 65, the signal wirings 63, and the connection pads 62 are formed in this order on the substrate 61. The GND wiring 64 is formed on the substrate 61 and is used to supply GND voltage. The signal wirings 63 are formed on the GND wiring 64 via the insulation film 65, and are used to supply signal voltage. The GND wiring 64 and the signal wirings 63 are electrically insulated from each other by the insulation film 65. The GND wiring 64 and the signal wirings 63 are, for example, Au (gold) wiring. The insulation film 65 is, for example, a silicon oxide film. The connection pads 62 are formed on the signal wirings 63 and are electrically connected to the signal wirings 63.
A of
Furthermore, A of
In the present embodiment, the direction of the current flowing through the signal wirings 63 and the direction of the current flowing through the GND wiring 64 are opposite to each other. Hence, it is possible to cause a magnetic field generated around the signal wirings 63 and a magnetic field generated around the GND wiring 64 to cancel each other out.
As described above, the LD chip 41 of the present embodiment is mounted on the circuit board 46 via the bump 45. Specifically, the signal wirings 63 are formed on the substrate 61, the connection pads 62 are formed on the signal wirings 63, and further, the mesa parts M are disposed on the connection pads 62 via the bump 45, and the substrate 51 is disposed on the mesa parts M. Each of the mesa parts M is disposed on the bump 45 via an anode electrode 54 or a cathode electrode 55. Therefore, the light emitting elements 53 are electrically connected to the signal wirings 63 via the anode electrodes 54, the bump 45, and the connection pads 62 (refer to
Meanwhile, the insulating substrate 47 includes wirings 72 to 75 on the ceramic substrate 71. The LDD board 42 is disposed on the wirings 72, 73, and is electrically connected to the signal wirings 63 via the wiring 72 and the bonding wires 49, and to the GND wiring 64 via the wiring 73 and the bonding wires 49. The capacitor 48 is disposed on the wirings 74, 75, and is electrically connected to the signal wirings 63 via the wiring 74 and the bonding wires 49, and to the GND wiring 64 via the wiring 75 and the bonding wires 49.
As described above, the LDD board 42 of the present embodiment includes the drive circuit 12 that drives the light emission unit 11. The drive circuit 12 in the LDD board 42 can drive the light emitting elements 53 in the LD chip 41 via the signal wirings 63 or the like.
Next, with reference to A of
A of
The light emitting elements 53 of the light emitting element group D1 are provided on one same signal wiring 63, and the signal wiring 63 and another signal wiring 63 on the left thereof are connected in parallel to each other. These signal wirings 63 are an example of first and second wirings adjacent to each other according to the present disclosure. A similar applies to the light emitting element groups D2, D3. The light emitting elements 53 of the light emitting element group D2 are provided on one same signal wiring 63, and the signal wiring 63 and another signal wiring 63 on the left thereof are connected in parallel to each other. The light emitting elements 53 of the light emitting element group D3 are provided on one same signal wiring 63, and the signal wiring 63 and another signal wiring 63 on the left thereof are connected in parallel to each other.
Meanwhile, the light emitting elements 53 of the light emitting element group D1 and the light emitting elements 53 of the light emitting element group D2 are connected in series to each other by the signal wiring 63 below the light emitting element group D2. Similarly, the light emitting elements 53 of the light emitting element group D2 and the light emitting elements 53 of the light emitting element group D3 are connected in series to each other by the signal wiring 63 below the light emitting element group D3.
Thus, in the light emitting device 1 of the present embodiment, the light emitting elements 53 of the same light emitting element group, that is, the light emitting elements 53 on the same signal wiring 63 are connected in parallel to each other. Meanwhile, the light emitting elements 53 of different light emitting element groups, that is, the light emitting elements 53 on different signal wirings 63 are connected in series to each other.
A of
The light emitting device 1 of the present comparative example includes components identical to the components of the light emitting device 1 of the present embodiment. However, a circuit board 46 of the present comparative example includes only one signal wiring 63, and all mesa parts M of an LD chip 41 of the present comparative example are disposed on the signal wiring 63. Therefore, in the light emitting device 1 of the present comparative example, all light emitting elements 53 of the LD chip 41 are connected in parallel to each other. For example, the light emitting elements 53 of a light emitting element group D1, the light emitting elements 53 of a light emitting element group D2, and the light emitting elements 53 of a light emitting element group D3 are connected in parallel to each other by the signal wiring 63.
A of
B of
C of
As illustrated in B of
The circuit board 46 of the present embodiment further includes one GND wiring 64 as illustrated in C of
As illustrated in C of
According to the present embodiment, it is possible to easily reduce the parasitic capacitances C1 to C3 by forming the openings P in the GND wiring 64. The parasitic capacitances C1 to C3 can be reduced, for example, by forming a cavity in the insulation film 65. However, it is difficult to perform a process of forming a cavity in the insulation film 65. Meanwhile, because a process of forming openings P in the GND wiring 64 can be performed with, for example, general photolithography and etching, the openings P can be easily formed. Therefore, according to the present embodiment, it is possible to easily reduce the parasitic capacitances C1 to C3 by forming the openings P in the GND wiring 64.
Because the openings P of the present embodiment are formed to extend in the X direction, the GND wiring 64 of the present embodiment includes the first parts 64a extending in the X direction. Therefore, according to the present embodiment, current can flow in the +X direction in the GND wiring 64 even if the openings P are formed in the GND wiring 64. Thus, it is desirable that the openings P have a shape extending in the X direction, but may not have a shape extending in the X direction as will be described later.
A of
In the present embodiment, the width W1 of each of the signal wirings 63 is the same as the width W2 of the GND wiring 64 (W1=W2). Hence, it is possible to cause a magnetic field generated around the signal wirings 63 and a magnetic field generated around the GND wiring 64 to suitably cancel each other out. For example, it is possible to cause these magnetic fields to cancel each other out so that these combined magnetic fields become closer to zero.
However, such an effect can be obtained even if there is some difference between the width W1 and the width W2. For example, it is desirable that the width W1 of each of the signal wirings is 90% to 110% of the width W2 of the GND wiring (W2×0.9≤W1≤W2×1.1). Hence, it is possible to obtain substantially the same effect as a case where the width W1 and the width W2 are the same. Note that, in a case where the width W1 and the width W2 are different, it is more desirable to have the width W1 broader than the width W2 (W1>W2), than to have the width W1 narrower than the width W2 (W1<W2).
The width Wa of each of the first parts 64a and the width Wb of each of the openings P may be set to arbitrary values. In the present embodiment, the widths Wa of all the first parts 64a of the GND wiring 64 are set to the same value, and the widths Wb of all the openings P in the GND wiring 64 are set to the same value.
Next, the first embodiment is compared with second and third comparative examples with reference to
Signal wirings 63 of the present comparative example has a shape identical to the shape of the signal wirings 63 of the first embodiment. Meanwhile, while the GND wiring 64 of the first embodiment has the openings P, a GND wiring 64 of the present comparative example has no opening P. Therefore, in the present comparative example, a large parasitic capacitance is generated between the signal wirings 63 and the GND wiring 64.
In general, a capacitance C between two electrodes is given by C=εS/d. Here, d represents a distance between the electrodes, S represents an area of each electrode, and ε represents permittivity of a material between the electrodes. Therefore, parasitic capacitance between the signal wirings 63 and the GND wiring 64 can be reduced, for example, by reducing an area of the signal wirings 63 or an area of the GND wiring 64.
Signal wirings 63 and GND wiring 64 of the present comparative example have shapes substantially identical to shapes of the signal wirings 63 and GND wiring 64 of the second comparative example, respectively. However, in the present comparative example, a width W2 of the GND wiring 64 is narrower than a width W1 of the signal wirings 63. Hence, parasitic capacitances in the present comparative example are smaller than the parasitic capacitances in the second comparative example. This is because an area of the GND wiring 64 decreases as the width W2 of the GND wiring 64 decreases.
Similarly to C of
As described above, according to the present comparative example, parasitic capacitances C1 to C3 can be reduced as compared with a case of the second comparative example. However, if the width W2 of the GND wiring 64 is reduced as in the present comparative example, a large parasitic inductance L is generated between the LDD board 42 and the light emitting element groups D1 to D3. This is because a magnetic field generated around the signal wirings 63 and a magnetic field generated around the GND wiring 64 cancel each other out less. Such a parasitic inductance L may interfere with operation of a drive circuit 12 (
Therefore, in the present embodiment, the openings P are provided in the GND wiring 64 while the width W2 of the GND wiring 64 is set to be the same as the width W1 of the signal wirings 63. Hence, it is possible to reduce the parasitic capacitances C1 to C3 while reducing an increase in the parasitic inductance L. Similarly to the case of the second comparative example, the parasitic capacitances C1 to C3 of the present embodiment are reduced by the area of the GND wiring 64 decreasing. Meanwhile, similarly to the first comparative example, the parasitic inductance L of the present embodiment is reduced by setting the width W2 the same as the width W1. Hence, it is possible to achieve both a reduction in the parasitic capacitances C1 to C3 and a reduction in the parasitic inductance L.
As described above, the circuit board 46 of the present embodiment includes the openings P provided in the GND wiring 64. Therefore, according to the present embodiment, it is possible to easily reduce the parasitic capacitances C1 to C3 between the signal wirings 63 and the GND wiring 64.
Hereinafter, circuit boards 46 and GND wirings 64 of second to eighth embodiments will be described. The second to eighth embodiments are modifications of the first embodiment, and the second to eighth embodiments will be described focusing on differences from the first embodiment. Similarly to the circuit board 46 and GND wiring 64 of the first embodiment, a circuit board 46 and GND wiring 64 of any one of the second to eighth embodiments are provided in a light emitting device 1 as illustrated in A of
The circuit board 46 of the present embodiment includes a plurality of signal wirings 63 having a shape different from a shape of the signal wirings 63 of the first embodiment, and one GND wiring 64 having a shape identical to a shape of the GND wiring 64 of the first embodiment. These signal wirings 63 are adjacent to each other in an X direction and a Y direction as illustrated in B of
According to the present embodiment, by forming the openings P between the signal wirings 63, it is possible to easily reduce parasitic capacitances C1 to C3, similarly to a case of forming the openings P in the GND wiring 64. Furthermore, according to the present embodiment, the openings P can be formed between the signal wirings 63 and can be formed in the GND wiring 64, and therefore, it is possible to increase a degree of freedom in designing the signal wirings 63 and the GND wiring 64.
Because the openings P of the present embodiment are formed to extend in the X direction, each of the signal wirings 63 of the present embodiment has a shape extending in the X direction, and the GND wiring 64 of the present embodiment includes the first parts 64a extending in the X direction. Therefore, according to the present embodiment, current can flow in the −X direction in the signal wirings 63 even if the openings P are formed between the signal wirings 63, and current can flow in the +X direction in the GND wiring 64 even if the openings P are formed in the GND wiring 64. Thus, it is desirable that the openings P have a shape extending in the X direction, but may not have a shape extending in the X direction as will be described later.
Furthermore, as illustrated in A of
A of
B of
Note that each of the openings P between the signal wirings 63 illustrated in B of
As described above, a circuit board 46 of the present embodiment includes the openings P provided between the signal wirings 63 in addition to the openings P provided in the GND wiring 64. Therefore, according to the present embodiment, the parasitic capacitances C1 to C3 between the signal wirings 63 and the GND wiring 64 can be further reduced, and a degree of freedom in designing the signal wirings 63 and the GND wiring 64 can be increased.
The circuit board 46 of the present embodiment includes a plurality of signal wirings 63 having a shape identical to the shape of the signal wirings 63 of the first embodiment, and one GND wiring 64 having a shape substantially identical to the shape of the GND wiring 64 of the first embodiment. However, in the present embodiment, a width Wb of the openings P in the GND wiring 64 is set to one tenth or less of a width W1 of the signal wirings 63 (Wb≤W1/10).
As a result of a simulation, it has been found that parasitic capacitances C1 to C3 can be effectively reduced by forming openings P in the GND wiring 64 such that the width Wb is one tenth or less of the width W1. Therefore, the width Wb in the present embodiment is set to one tenth or less of the width W1. This condition may be applied to a case where the openings P are formed between the GND wirings 64, in the signal wirings 63, or between the signal wirings 63.
Note that the width W1 of the signal wirings 63 is the same as a width W2 of the GND wiring 64 in the present embodiment, but may be different from the width W2 of the GND wiring 64. For example, the width W1 may be 90% to 110% of the width W2, or may be wider than the width W2.
The circuit board 46 of the present embodiment includes a plurality of signal wirings 63 having a shape identical to the shape of the signal wirings 63 of the first embodiment, and one GND wiring 64 having a shape substantially identical to the shape of the GND wiring 64 of the first embodiment. However, the GND wiring 64 of the present embodiment includes first parts 64a having different widths Wa as the above-described first parts 64a. Thus, in the GND wiring 64 of the present embodiment, the widths Wa of all the first parts 64a may not have the same value. Hence, it is possible to increase a degree of freedom in designing the GND wiring 64 as compared with a case where the widths Wa of all the first parts 64a are the same.
Note that, similarly to the GND wiring 64 of the present embodiment, each of the signal wirings 63 of the second embodiment may also include the first parts 63a having different widths in the Y direction. Hence, it is possible to increase a degree of freedom in designing each of the signal wirings 63 as compared with a case where the widths of all the first parts 63a are the same.
The circuit board 46 of the present embodiment includes a plurality of signal wirings 63 having a shape different from a shape of the signal wirings 63 of the first embodiment, and one GND wiring 64 having a shape identical to a shape of the GND wiring 64 of the first embodiment. Specifically, as illustrated in C of
Note that, similarly to the GND wiring 64 of the present embodiment, each of the signal wirings 63 of the second embodiment may also include a plurality of openings P disposed in a two-dimensional array. Hence, it is possible to provide a large number of small openings P in each of the signal wirings 63.
A of
B of
C of
Note that the openings P of any one of the sixth to eighth embodiments may be applied to each of the signal wirings 63 of the second embodiment. Hence, it is possible to provide a large number of small openings P in each of the signal wirings 63 or to provide a large single opening P in each of the signal wirings 63.
Note that the light emitting devices 1 of the first to eighth embodiments are used as a light source of a distance measurement device, but may be used in another mode. For example, the light emitting devices 1 of these embodiments may be used as a light source of an optical apparatus such as a printer, or may be used as a lighting device.
Although the embodiments according to the present disclosure have been described above, these embodiments may be implemented with various modifications without departing from the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.
Note that the present disclosure can also have the following configurations.
(1)
A semiconductor device including
(2)
The semiconductor device according to (1),
(3)
The semiconductor device according to (1), in which the elements include light emitting elements provided on the second substrate.
(4)
The light emitting device according to (3), in which light emitted from the light emitting elements passes through the second substrate from a lower surface to upper surface of the second substrate, and is emitted from the second substrate.
(5)
The semiconductor device according to (1),
(6)
The semiconductor device according to (1), in which an opening extending in the first direction is provided as the first or second opening.
(7)
The semiconductor device according to (1), in which a plurality of openings extending in the first direction and adjacent to each other in the second direction is provided as the first or second openings.
(8)
The semiconductor device according to (7),
(9)
The semiconductor device according to (1), in which a width of the upper wirings in the second direction is the same as a width of the lower wiring in the second direction.
(10)
The semiconductor device according to (1), in which a width of the upper wirings in the second direction is wider than a width of the lower wiring in the second direction.
(11)
The semiconductor device according to (1), in which a width of the upper wirings in the second direction is 90% to 110% of a width of the lower wiring in the second direction.
(12)
The semiconductor device according to (1), in which the first opening is provided in the lower wiring or provided so as to be sandwiched between the lower wirings in the second direction, and the second opening is provided in the upper wirings or provided so as to be sandwiched between the upper wirings in the second direction.
(13)
The semiconductor device according to (12),
(14)
The semiconductor device according to (12),
(15)
The semiconductor device according to (12),
(16)
The semiconductor device according to (1), in which a width of the first or second opening in the second direction is one tenth or less of a width of the upper wirings in the second direction.
(17)
The semiconductor device according to (8), in which the plurality of first parts includes first parts having different widths in the second direction.
(18)
The semiconductor device according to (1), in which a plurality of openings disposed in a two-dimensional array is provided as the first or second opening.
(19)
The semiconductor device according to (1), in which, as the first or second opening, only one opening is provided in the upper wirings or in the lower wiring, or only one opening is provided so as to be sandwiched between the upper wirings in the second direction or between the lower wirings in the second direction.
(20)
The light emitting device according to (1), in which the first substrate includes a semiconductor substrate including silicon (Si), and
Number | Date | Country | Kind |
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2020-192546 | Nov 2020 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP2021/035810 | 9/29/2021 | WO |