TREA

Semiconductor device

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Information

  • Patent Grant
  • D476959
  • Patent Number
    D476,959
  • Date Filed
    Wednesday, July 31, 2002
    21 years ago
  • Date Issued
    Tuesday, July 8, 2003
    21 years ago
Information
Abstract
Description




FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;




FIG. 2 is a front elevational view thereof;




FIG. 3 is a rear elevational view thereof;




FIG. 4 is a top plan view thereof;




FIG. 5 is a bottom plan view thereof;




FIG. 6 is a right side elevational view thereof; and,




FIG. 7 is a left side elevational view thereof.



Claims
  • The ornamental design for a semiconductor device, as shown and described.
US Referenced Citations (8)
Number Name Date Kind
5369551 Gore et al. Nov 1994 A
D357672 Terasawa et al. Apr 1995 S
D389808 Yamada et al. Jan 1998 S
D396450 Nishiura et al. Jul 1998 S
D396847 Nakayama et al. Aug 1998 S
5991162 Saso Nov 1999 A
D453746 Kato et al. Feb 2002 S
6355877 Watanabe Mar 2002 B1
Non-Patent Literature Citations (1)
Entry
J. Yamada, et al., “Next Generation High Power Dual IGBT Module with CSTBT Chip and New Packgage Concept”, Official Proceedings International Conferences ZM Communications GmbH, PCIM 2002, Power Electronics, May 14-16, 2002, 11 pages.