Patent Grant
10872907
The technical field relates to a semiconductor device.
Patent Document 1 discloses parallel connection of a first transistor and a second transistor.
Each of Patent Document 2 and Patent Document 3 discloses a transistor including an oxide semiconductor layer between two gate electrodes.
An object is to solve at least one problem selected from a first problem, a second problem, a third problem, and a fourth problem.
<First Problem>
With the parallel connection of the first transistor and the second transistor, the number of the oxide semiconductor layers is increased.
<Second Problem>
The parasitic capacitance effects on the driving of the transistor.
<Third Problem>
A novel semiconductor device is required.
<Fourth Problem>
The fourth problem is at least one problem selected from a plurality of problems apparent from this specification.
The number of oxide semiconductor layers can be reduced when one oxide semiconductor layer has a first channel formation region and a second channel formation region.
One of two conductive layers has an opening.
When the other of the two conductive layers has a region overlapping with the opening, the parasitic capacitance is low.
<Opening>
For example, the opening is a missing part.
For example, the opening is a hole.
For example, an opening 45 shown in
For example, the opening 45 shower
For example, an opening 75 shown in
For example, the opening 75 shown in
For example, the missing part can be referred to as a gap.
For example, a linear shape of an edge of the missing part is an opened shape.
A linear shape of an edge of the hole is a closed shape.
<Example of Disclosed Invention>
The semiconductor device includes a first conductive layer.
The semiconductor device includes a first insulating layer over the first conductor layer.
The semiconductor device includes an oxide semiconductor layer over the first insulating layer.
The semiconductor device includes a second conductive layer over the oxide semiconductor layer.
The semiconductor device includes a third conductive layer over the oxide semiconductor layer.
The semiconductor device includes a second insulating layer over the second conductive layer and the third conductive layer.
The semiconductor device includes a fourth conductive layer over the second insulating layer.
The semiconductor device includes a fifth conductive layer over the second insulating layer.
The semiconductor device includes a third insulating layer over the fourth conductive layer and the fifth conductive layer.
The semiconductor device includes a sixth conductive layer over the third insulating layer.
The oxide semiconductor layer as a first channel formation region of a first transistor.
The oxide semiconductor layer has a second channel formation region of a second transistor.
The first conductive layer has a function of a first gate electrode of the first transistor.
The first conductive layer has a function of a second gate electrode of the second transistor.
The second conductive layer has a function of one of a source electrode and a drain electrode of the first transistor.
The second conductive layer has a function of one of a source electrode and a drain electrode of the second transistor.
The third conductive layer has a function of the other of the source electrode and the drain electrode of the first transistor.
The third conductive layer has a function of the other of the source electrode and the drain electrode of the second transistor.
The fourth conductive layer has a function of a third gate electrode of the first transistor.
The fourth conductive layer has a function of a fourth gate electrode of the second transistor.
The second conductive layer has a first opening.
The fourth conductive layer has a second opening.
The third conductive layer has a region overlapping with the first opening and a region overlapping with the second opening.
The sixth conductive layer is electrically connected to the third conductive layer with the fifth conductive layer.
The fifth conductive layer has a region overlapping with the first opening and a region overlapping with the second opening.
<Fifth Conductive Layer, Sixth Conductive Layer>
When the sixth conductive layer is formed over the third insulating layer, the degree of freedom of shape of the sixth conductive layer can be high.
For example, the sixth conductive layer is a pixel electrode.
The sixth conductive layer is electrically connected to the fourth conductive layer with the fifth conductive layer.
With the fifth conductive layer, the probability of disconnection of the sixth conductive layer can be decreased.
The number of oxide semiconductor layers is decreased.
The parasitic capacitance is low.
A novel semiconductor device is provided.
The problems apparent from the content of this specification can be solved.
Embodiments will be described with drawings.
Contents described in the embodiments are each just one example.
The interpretation of the invention should not be limited to only the contents of the embodiments.
In the embodiments, portions shown by the same reference numerals are not explained repeatedly.
In the drawings, the same reference numeral may be used in the same part.
In the drawings, the same hatching may be used in the same part.
In the drawings, the same reference numeral may be used in the similar part.
In the drawings, the same hatching may be used in the similar part.
The contents of the embodiment can be combined with the contents of the other embodiment.
An example of the semiconductor device can be described with reference to
<Example of Circuit>
A terminal T1 is electrically connected to one of a source electrode and a drain electrode of the transistor Tr1.
The terminal T1 is electrically connected to one of a source electrode and a drain electrode of the transistor Tr2.
The one of the source electrode and the drain electrode of the transistor Tr1 is electrically connected to the one of the source electrode and the drain electrode of the transistor Tr2.
A terminal T2 is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr1.
The terminal T2 is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr2.
The other of the source electrode and the drain electrode of the transistor Tr1 is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr2.
A terminal T3 is electrically connected to a first gate electrode of the transistor Tr1.
The terminal T3 is electrically connected to a second gate electrode of the transistor Tr2.
The first gate electrode of the transistor Tr1 is electrically connected to the second gate electrode of the transistor Tr2.
A terminal T4 is electrically connected to a third gate electrode of the transistor Tr1.
The terminal T4 is electrically connected to the fourth gate electrode of the transistor Tr2.
The third gate electrode of the transistor Tr1 is electrically connected to the fourth gate electrode of the transistor Tr2.
The terminal T1 is electrically connected to the terminal T2 through a first channel formation region of the transistor Tr1.
The terminal T1 is electrically connected to the terminal T2 through a second channel formation region of the transistor Tr2.
For example, the terminal T3 can be electrically connected to the terminal T4.
For example, the terminal T3 can be electrically isolated from the terminal T4.
<Cross-Sectional View>
An example of a semiconductor device is described with reference to
There is a substrate 10.
A conductive layer 21 is placed over the substrate 10.
An insulating layer 30 is placed over the conductive layer 21.
An oxide semiconductor layer 31 is placed over the insulating layer 30.
A conductive layer 41 is placed over the oxide semiconductor layer 31.
A conductive layer 42 is placed over the oxide semiconductor layer 31.
For example, the conductive layer 41 and the conductive layer 42 can be formed through a step of etching one conductive layer.
An insulating layer 60 is placed over the conductive layer 41 and the conductive layer 42.
A conductive layer 71 is placed over the insulating layer 60.
A conductive layer 72 is formed over the insulating layer 60.
An insulating layer 80 is placed over the conductive layer 71 and the conductive layer 72.
A conductive layer 91 is placed over the insulating layer 80.
For example,
The conductive layer 21 has a region capable of functioning as the first gate electrode of the transistor Tr1.
The conductive layer 21 has a region capable of functioning as the second gate electrode of the transistor Tr2.
The insulating layer 30 has a region capable of functioning as a first gate insulating layer of the transistor Tr1.
The insulating layer 30 has a region capable of functioning as a second gate insulating layer of the transistor Tr2.
The oxide semiconductor layer 31 has a region overlapping with the conductive layer 21.
The oxide semiconductor layer 31 has the first channel formation region of the transistor Tr1.
The oxide semiconductor layer 31 has a second channel formation region of the transistor Tr2.
In the transistor Tr1, the first gate insulating layer is placed between the first gate electrode and the first channel formation region.
In the transistor Tr2, the second gate insulating layer is placed between the second gate electrode and the second channel formation region.
The conductive layer 41 has a region overlapping with the oxide semiconductor layer 31.
The conductive layer 42 has a region overlapping with the oxide semiconductor layer 31.
The conductive layer 41 has a region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr1.
The conductive layer 41 has a region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr2.
The conductive layer 41 has an opening 45 between the “region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr1” and the “region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr2”.
The conductive layer 42 has a region overlapping with the opening 45.
The conductive layer 42 has a region capable of functioning as the other of the source electrode and the drain electrode of the transistor Tr1.
The conductive layer 42 has a region capable of functioning as the other f the source electrode and the drain electrode of the transistor Tr2.
The insulating layer 60 has a region capable of functioning as a third gate insulating layer of the transistor Tr1.
The insulating layer 60 has a region capable of functioning as a fourth gate insulating layer of the transistor Tr2.
The insulating layer 60 has an opening 65.
The conductive layer 71 has a region overlapping with the oxide semiconductor layer 31.
The conductive layer 71 has a region overlapping with the conductive layer 41.
The conductive layer 71 has a region overlapping with the conductive layer 42.
The conductive layer 71 has a region capable of functioning as the third gate electrode of the transistor Tr1.
The conductive layer 71 has a region capable of functioning as the fourth gate electrode of the transistor Tr2.
The conductive layer 71 has an opening 75 between the “region capable of functioning as the third gate electrode of the transistor Tr1” and the “region capable of functioning as the fourth gate electrode of the transistor Tr2”.
The conductive layer 72 has a region overlapping with the opening 75.
The conductive layer 72 is electrically connected to the conductive layer 42 through the opening 65.
The insulating layer 80 has an opening 85.
The conductive layer 91 is electrically connected to the conductive layer 72 through the opening 85.
For example, the conductive layer 91 has a region capable of a function of an electrode or a wiring.
For example, the electrode is a pixel electrode.
<Conductive Layer 21, Conductive Layer 71>
The conductive layer 21 can be electrically connected to the conductive layer 71.
The conductive layer 21 can be electrically isolated from the conductive layer 71.
<Top-Gate Transistor>
A top-gate transistor can be employed.
For example, formation of the conductive layer 21 and the insulating layer 30 can be skipped.
For example, the conductive layer 21 can be in a floating state.
The conductive layer 21 in a floating state has a function of blocking impurities from the substrate 10.
<Example>
For example, a structure without the opening 65 can be employed.
For example, formation of the conductive layer 72 can be skipped.
For example, a structure without the opening 75 can be employed.
For example, formation of the insulating layer 80 can be skipped.
For example, formation of the conductive layer 91 can be skipped.
<Number of Oxide Semiconductor Layers>
When the oxide semiconductor layer 31 has the first channel formation region and the second channel formation region, the number of oxide semiconductor layers can be small.
<Parasitic Capacitance>
For example, a structure without the opening 75 can be employed.
Without the opening 75, the amount of parasitic capacitance between the conductive layer 42 and the conductive layer 71 is increased.
In
<Degree of Freedom>
When the conductive layer 91 is formed over the insulating layer 80, the degree of freedom of shape of the conductive layer 91 can be high.
<Disconnection>
When the conductive layer is in contact with two surfaces, the distance between the two surfaces is reduced, so that the probability of disconnection of the conductive layer can be decreased.
For example, formation of the conductive layer 72 can be skipped.
Without the conductive layer 72, the conductive layer 91 is in contact with a surface of the insulating layer 60 and a surface of the insulating layer 80.
When the conductive layer 72 is formed as illustrated in
The “distance between the surface of the conductive layer 72 and the surface of the insulating layer 80” is shorter than the “distance between the surface of the insulating layer 60 and the surface of the insulating layer 80”.
With the conductive layer 72, the probability of disconnection of the conductive layer 91 can be decreased.
An example of a semiconductor device is described with reference to
<Outline>
An example of a cross section along A-B in
A structure shown in
A structure shown in
A structure shown in
<1. Cross-Sectional View>
An example of a cross section along C-D in
A conductive layer 43 is placed over the insulating layer 30.
For example, the conductive layer 41, the conductive layer 42, and the conductive layer 43 can be formed through a step of etching one conductive layer.
The insulating layer 30 has an opening 35a.
The insulating layer 60 has an opening 65a.
The conductive layer 71 is electrically connected to the conductive layer 43 through the opening 65a.
The conductive layer 43 is electrically connected to the conductive layer 21 through the opening 35a.
The conductive layer 71 is electrically connected to the conductive layer 21.
With the conductive layer 43, the probability of disconnection of the conductive layer 71 can be reduced.
The conductive layer 71 can be electrically isolated from the conductive layer 21.
A structure without the conductive layer 43 can be employed.
<2. Cross-Sectional View>
For example, the structure shown in
A conductive layer 44 is placed over the insulating layer 30.
For example, the conductive layer 41, the conductive layer 42, and the conductive layer 44 can be formed through a step of etching one conductive layer.
A conductive layer 73 is placed over the insulating layer 60.
For example, the conductive layer 71, the conductive layer 72, and the conductive layer 73 can be formed through a step of etching one conductive layer.
A conductive layer 92 is placed over the insulating layer 80.
For example, the conductive layer 91 and the conductive layer 92 can be formed through a step of etching one conductive layer.
The insulating layer 30 has an opening 36a.
The insulating layer 60 has an opening 66a.
The insulating layer 80 has an opening 85a.
The insulating layer 80 has an opening 86a.
The conductive layer 92 is electrically connected to the conductive layer 71 through the opening 85a.
The conductive layer 92 is electrically connected to the conductive layer 73 through the opening 86a.
The conductive layer 73 is electrically connected to the conductive layer 44 through the opening 66a.
The conductive layer 44 is electrically connected to the conductive layer 21 through the opening 36a.
With the conductive layer 44, the probability of disconnection of the conductive layer 73 or the conductive layer 92 can be reduced.
With the conductive layer 73, the probability of disconnection of the conductive layer 92 can be reduced.
Formation of the conductive layer 44 can be skipped.
Formation of the conductive layer 73 can be skipped.
<Opening>
For example, the opening 45 shown in
For example, the opening 45 shown
For example, the opening 75 shown in
For example, the opening 75 shown in
For example, the opening 65 shown in
For example, the opening 85 shown in
For example, the opening 35a shown in
For example, the opening 36a shown in
For example, the opening 85a shown in
For example, the opening 86a shown in
The opening can be a missing part instead of a hole.
The opening can be a hole instead of a missing part.
Note that this embodiment can be applied to Embodiment 1.
For example, as illustrated in
For example, as illustrated in
The conductive layer 71a is electrically connected to the conductive layer 71b.
The conductive layer 41a is electrically connected to the conductive layer 41b.
For example, the conductive layer 71a has a region capable of functioning as the third gate electrode of the transistor Tr1 in
For example, the conductive layer 71b has a region capable of functioning as the fourth gate electrode of the transistor Tr2 in
For example, the conductive layer 41a has a region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr1 in
For example, the conductive layer 41b has a region capable of functioning as one of the source electrode and the drain electrode of the transistor Tr2 in
<Conductive Layer 21, Conductive Layer 71a, Conductive Layer 71b>
In
In
For example, as illustrated in
In
For example, as illustrated in
For example, as illustrated in
In
For example, as illustrated in
For example, as illustrated in
In
For example, as illustrated in
For example, as illustrated in
For example, as illustrated in
For example, as illustrated in
For example, the conductive layer 21 and the conductive layer 120 can be formed through a step of etching one conductive layer.
For example, the conductive layer 42 and the conductive layer 140 can be formed through a step of etching one conductive layer.
For example, the conductive layer 91 and the conductive layer 190 can be formed through a step of etching one conductive layer.
For example, as illustrated in
In
In
For example, as illustrated in
In
In
A layout shown in
Layouts shown in
<Conductive Layer 41a, Conductive Layer 41b, Conductive Layer 42>
In
In
For example, as illustrated in
For example, as illustrated in
For example, as illustrated in
In
In
In
For example, the conductive layer 21 and the conductive layer 220 can be formed through a step of etching one conductive layer.
For example, the conductive layer 72 and the conductive layer 270 can be formed through a step of etching one conductive layer.
For example, the conductive layer 91 and the conductive layer 290 can be formed through a step of etching one conductive layer.
The concept of each of structures shown in
For example, in
For example, in
For example, in
For example, in
This embodiment can be applied to Embodiment 1 and Embodiment 2.
For formation of the opening 65, the surface of the conductive layer 42 can be removed.
For example, as illustrated in
In
For example, the region 48a can also be referred to as a hollow.
For example, in
Since the conductive layer 42 has a hollow, an area where the conductive layer 42 and the conductive layer 72 are in contact with each other can be increased.
Without the conductive layer 72, an area where the conductive layer 42 and the conductive layer 91 are in contact with each other can be increased.
When an area where two conductive layers are in contact with each other is increased, the contact resistance by the two conductive layers can be decreased.
This embodiment can be applied to Embodiment 1 to Embodiment 3.
An oxide region can be formed between the oxide semiconductor layer 31 and the insulating layer 60.
<
For example, in
For example, in
For example, in
For example, in
For example, in
The conductive layer 41 has a region in contact with the oxide semiconductor layer 31.
The conductive layer 42 has a region in contact with the oxide semiconductor layer 31.
<
For example, in
For example, in
For example, in
<1. Oxide Region>
For example, the oxide region 99a can be a region of a first oxide layer.
For example, the oxide region 99b can be a region of a second oxide layer.
For example, the oxide region 99c can be a region of a third oxide layer.
<2. Oxide Region>
For example, one oxide layer includes the oxide region 99a, the oxide region 99b, and the oxide region 99c.
<Oxide Layer>
For example, the oxide layer is an oxide insulating layer.
For example, the oxide layer is an oxide semiconductor layer with a band gap larger than that of the oxide semiconductor layer 31.
For example, since the oxide layer includes oxygen, the oxide layer has a function of supplying oxygen to the oxide semiconductor layer 31.
For example, with supply of oxygen, the amount of oxygen vacancies in the oxide semiconductor layer 31 can be reduced.
<Oxide Region 99a>
The oxide region 99a is placed between the conductive layer 21 and the conductive layer 42.
With the oxide region 99a, the amount of parasitic capacitance between the conductive layer 21 and the conductive layer 42 can be reduced.
<Oxide Region 99b>
The oxide region 99b is placed between the first channel formation region and the insulating layer 60.
<Oxide Region 99c>
The oxide region 99c is placed between the second channel formation region and the insulating layer 60.
This embodiment can be applied to Embodiment 1 to Embodiment 4.
For example, the semiconductor device can be selected from a display device, a memory device, a processor, an RFID, and the like.
This embodiment can be applied to Embodiment 1 to Embodiment 5.
In this embodiment, a layer and a material are described.
Materials described in this embodiment are each just an example.
<Layer>
For example, a layer is a single film or a stacked film.
The single film includes one film.
The stacked film includes plural films.
For example, the stacked film has at least a first film and a second film.
For example, the material of the first film is different from that of the second film.
For example, the material of the first film is the same as that of the second film.
For example, each of the materials of the first film and the second film can be selected from materials exemplified in this embodiment.
<Material>
For example, the substrate can be selected from a glass substrate, a plastic substrate, a semiconductor substrate, or the like.
For example, the conductive layer can be a layer including a metal or the like.
For example, the metal can be selected from Al, Ti, Cu, W, Cr, Mo, In, Sn, Zn, or the like.
For example, the insulating layer can be selected from an oxide insulating layer, a nitride insulating layer, an organic insulating layer, or the like.
For example, the oxide insulating layer can include silicon oxide, aluminum oxide, gallium oxide, hafnium oxide, or the like.
For example, the nitride insulating layer can have silicon nitride, aluminum nitride, or the like.
For example, the organic insulating layer can include acrylic, polyimide, siloxane, or the like.
For example, the oxide semiconductor layer can include In, Sn, Zn, Ga, or the like.
For example, the oxide semiconductor layer can be selected from indium oxide, tin oxide, zinc oxide, or the like.
For example, the oxide semiconductor layer can be selected from indium zinc oxide, zinc tin oxide, or the like.
For example, the oxide semiconductor layer can include In, M, and Zn.
For example, the element M can be selected from typical metals, transition metals, or the like.
For example, the transition metal can be Ti, Hf, lanthanoid, actinoid, or the like.
<Crystal Region>
Because the oxide semiconductor layer has a c-axis-aligned crystalline (CAAC) region along the direction X, the density of the oxide semiconductor layer is increased.
By the increased density of the oxide semiconductor layer, H2O can be prevented from entering the oxide semiconductor layer.
For example, the direction X is a direction perpendicular to the surface of the oxide semiconductor layer.
For example, the angle between the c axis and the surface of the oxide semiconductor layer is 90 degrees.
For example, the direction X is a direction that is substantially perpendicular to the surface of the oxide semiconductor layer.
For example, the angle between the c axis and the surface of the oxide semiconductor layer is from 80 degrees to 100 degrees inclusive.
<Stacked Film>
For example, the oxide semiconductor layer has an oxide semiconductor film A and an oxide semiconductor film B.
For example, the oxide semiconductor film B is placed over the oxide semiconductor film A.
For example, the oxide semiconductor layer has the oxide semiconductor film A, the oxide semiconductor film B, and an oxide semiconductor film C.
For example, the oxide semiconductor film B is placed over the oxide semiconductor film A.
For example, the oxide semiconductor film C is placed below the oxide semiconductor film A.
For example, each of the oxide semiconductor A, the oxide semiconductor B, and the oxide semiconductor C include In, Ga, and Zn.
For example, “the proportion of gallium contained in the oxide semiconductor film B or the proportion of indium contained in the oxide semiconductor film B” is higher than the proportion of gallium contained in the oxide semiconductor film A or the proportion of indium contained in the oxide semiconductor film A”.
For example, “the proportion of zinc contained in the oxide semiconductor film B or the proportion of indium contained in the oxide semiconductor film B” is higher than “the proportion of zinc contained in the oxide semiconductor film A or the proportion of indium contained in the oxide semiconductor film A”.
For example, “the proportion of gallium contained in the oxide semiconductor film C or the proportion of indium contained in the oxide semiconductor film C” is higher than “the proportion of gallium contained in the oxide semiconductor film A or the proportion of indium contained in the oxide semiconductor film A”.
For example, “the proportion of zinc contained in the oxide semiconductor film C or the proportion of indium contained in the oxide semiconductor film C” is higher than “the proportion of zinc contained in the oxide semiconductor film A or the proportion of indium contained in the oxide semiconductor film A”.
For example, in the oxide semiconductor film A, the element M can be used instead of Ga.
For example, in the oxide semiconductor film B, the element M can be used instead of Ga.
For example, in the oxide semiconductor film C, the element M can be used instead of Ga.
For example, the element M can be selected from typical metals, transition metals, and the like.
When the proportion of In in the oxide semiconductor film is lower than that of M or Zn, the band gap of the oxide semiconductor film is increased.
When the oxide semiconductor layer is a stacked film, a channel is formed in an oxide semiconductor film having the smallest band gap.
For example, when the oxide semiconductor layer includes the oxide semiconductor film A and the oxide semiconductor film B, a channel is formed in the oxide semiconductor film A.
For example, when the oxide semiconductor layer includes the oxide semiconductor film A, the oxide semiconductor film B, and the oxide semiconductor film C, a channel is formed in the oxide semiconductor film A.
The channel formed in the oxide semiconductor film A is apart from defects at the interface with a gate insulating layer.
The reliability of the transistor is improved by distancing its channel from such defects.
<Semiconductor Layer>
For example, a silicon semiconductor layer may be used instead of the oxide semiconductor layer.
The semiconductor layer generally includes a silicon semiconductor layer and an oxide semiconductor layer.
This embodiment can be applied to Embodiment 1 to Embodiment 6.
This application is based on Japanese Patent Application serial no. 2013-154537 filed with Japan Patent Office on Jul. 25, 2013, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-154537 | Jul 2013 | JP | national |
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| Number | Date | Country | |
|---|---|---|---|
| 20200091201 A1 | Mar 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14337575 | Jul 2014 | US |
| Child | 16689134 | US |
