International Electron Devices Meeting, 1990, San Francisco, California, Dec. 9-12. 1990 pp. 18.3.1-18.3.4. |
"256 kbit CMOS EPROM HN27C256", Hideaki Takahashi et al., 8297 Hitachi Review, vol. 34, No. 6, Dec., 1985, pp. 295-298. |
"A 5.9um.sup.2 Super Low Power SRAM Cell Using a New Phase-Shift Lithography" T. Yamanaka et al., IEDM 1990, pp. 477-480. |
"A Large Cell-Ratio and Low Node Leak 16M-bit SRAM Cell Using Ratio-Gate Transistors", K. Yuzuriha et al., IEDM 1991, pp. 485-488. |
T. Yamanaka et al., "A 5.9 .mu.m.sup.2 Super Low Power SRAM Cell Using a New Phase-Shift Lithography," International Electron Devices Meeting, San Francisco, CA, Dec. 9-12, 1990, Dec. 9, 1990, No. 90, Institute of Electrical and Electronics Engineers, pp. 477-480. |
Manabu Ando et al., "A 0.1-.mu. A Standby Current, Ground-Bounce-Immune 1 Mbit CMOS SRAM," IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1, 1989, pp. 1708-1712. |
T. Yamanaka et al., "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immnnity," Electron Devices, San Francisco, CA, Dec. 11-14, 1988, Institute of Electrical and Electronics Engineers, No. 1988, Dec. 11, 1988, pp. 48-51. |