Claims
- 1. A semiconductor integrated circuit device comprising:
- a plurality of insulated gate field-effect transistors each having source and drain regions of a first conductivity type disposed in a substrate of a second conductivity type, opposite said first conductivity type, and a gate electrode overlying a region between the source and drain regions, said plurality of transistors being arranged in the form of a matrix of rows and columns of transistors, the transistors of each row being connected in series through their source and drain paths, wherein said plurality includes both enhancement type transistors and depletion type transistors, and
- a plurality of wirings corresponding to said columns of transistors, the gate electrodes of transistors of each column being connected in common to the corresponding wiring.
- 2. A semiconductor integrated circuit device according to claim 1, wherein each of said gate electrodes is formed of polycrystalline silicon.
- 3. A semiconductor integrated circuit device according to claim 2, wherein the polycrystalline silicon gate electrodes of the transistors of each column are formed of the same continuous polycrystalline silicon electrode.
- 4. A semiconductor integrated circuit device according to claim 1, wherein channel regions of said first conductivity type are formed at said regions between said source and drain regions of said depletion type transistors by ion implantation so as to provide conductive paths between said source and drain regions.
- 5. A semiconductor integrated circuit device according to claim 4, wherein each ion-implanted channel region extends from the surface of the substrate to a depth less than that of the source and drain regions and overlaps the source and drain regions.
- 6. A semiconductor integrated circuit device comprising:
- (a) a plurality of conductive layers electrically separated from each other and being substantially arranged in parallel with each other on an insulating layer lying on a semiconductor substrate of a first conductivity type;
- (b) a plurality of diffused regions of a second conductivity type opposite to said first conductivity type being arranged in parallel with each other in said semiconductor substrate and extending so as to cross respective ones of said conductive layers; and wherein
- (c) each of the crossed portions of the conductive layers and the diffused regions acts as MOSFET device, selected ones of said plural MOSFETs being depletion type MOSFETs, and the others of said plural MOSFETS being enhancement type MOSFETs.
Priority Claims (1)
Number |
Date |
Country |
Kind |
49/103927 |
Sep 1974 |
JPX |
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Parent Case Info
This is a continuation of U.S. patent application, Ser. No. 611,891, filed Sept. 10, 1975 now abandoned, of which this application claims all benefits.
US Referenced Citations (3)
Continuations (1)
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Number |
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Parent |
611891 |
Sep 1975 |
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