Patent Application
20250151257
The present application claims the benefit of priority to China Application No. 202311461867.2, filed on Nov. 2, 2023, the content of which is incorporated herein by reference in its entirety.
The present application relates to the field of semiconductor design and fabrication, and particularly to semiconductor devices, fabrication methods of the semiconductor devices and memory systems.
A dynamic random access memory (DRAM) is one of the important memory components in an electronic system. Taking the DRAM as an example, a semiconductor device may comprise memory cells composed of capacitors and transistors, wherein a plurality of memory cells may be arranged in a form of a two-dimensional array. Furthermore, in order to further reduce a size of the two-dimensional array, the transistor may comprise a vertical gate transistor (VGT). In such a structure, a source and a drain of the transistor are formed at two ends of a channel of the transistor respectively in an extending direction, and a gate structure of the transistor is formed on at least one side of the channel.
Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limitative implementations made with reference to the following drawings. Among the drawings:
In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the drawings. It is understood that, these detailed descriptions are only descriptions of example implementations of the present application, and are not intended to limit the scope of the present application in any manner. Like reference numbers denote like elements throughout the specification. The expression “and/or” includes any or all combinations of one or more of listed associated items.
It is to be noted that, in the specification, the expressions such as first, second, third and the like, are only used to distinguish one feature from another feature, instead of representing any limitation to the features, particularly instead of representing any sequential order. Thus, without departing from the teaching of the present application, a first word line structure discussed in the present application may be also called a second word line structure, and vice versa.
For ease of illustration, the thicknesses, sizes and shapes of components have been slightly adjusted in the drawings. The drawings are merely examples and are not drawn to scale precisely. As used herein, terms “approximately”, “about”, and the like, are used to represent approximation, instead of representing degrees, and are intended to describe inherent deviations in measured values or calculated values as recognized by those of ordinary skill in the art.
It should be also understood that, expressions, such as “comprise”, “comprising”, “have”, “include”, and/or “including”, etc., are open-ended expressions, rather than close-ended expressions in the specification. They represent the existence of the stated features, elements and/or components, but do not exclude the existence of one or more other features, elements, components and/or combinations thereof. Moreover, the expression, such as “at least one of . . . ”, appearing before a list of listed features, modifies the whole list of features, rather than an individual element therein. Furthermore, the term “may” is used to represent “one or more implementations of the present application” when describing the implementations of the present application. Moreover, the term “exemplary” is intended to refer to an example or illustration.
Unless otherwise defined, all phraseologies (including engineering terms and technical terms) as used herein have the same meanings as those generally understood by those of ordinary skill in the art to which the present application pertains. It should be further understood that, terms as defined in common dictionaries should be interpreted as having meanings that are consistent with their meanings in the context of the related art, and should not be interpreted in an idealized or overly formal sense unless otherwise stated expressly in the present application.
It is to be noted that, implementations and features in the implementations of the present application may be mutually combined in the case of no conflicts. In addition, unless otherwise defined expressly or conflicting with the context, specific steps included in a method as set forth in the present application are not necessarily limited to the described order, but may be carried out in any order or in parallel.
Furthermore, “connected” or “joined”, when used in the present application, may represent direct contact or indirect contact between respective components, unless otherwise expressly defined or derived from the context.
The present application will be detailed below by reference to the drawings and in conjunction with the implementations.
With rapid development of semiconductor technology, how to optimize the overall performance of the semiconductor device, simplify the fabrication process and reduce the process cost is one of the important research directions in the industry.
Some implementations of the present application provide a semiconductor device.
As shown in
According to the semiconductor device provided by at least one implementation of the present application, the semiconductor device may comprise the word line structure and a plurality of semiconductor pillars arranged in an array, wherein the plurality of semiconductor pillars are arranged in rows to form rows of semiconductor pillars, the word line structure is disposed between the adjacent rows of semiconductor pillars and comprises the first word line structure and the second word line structure spaced apart from each other, and the adjacent rows of semiconductor pillars are connected with one of the first word line structure and the second word line structure respectively. Since sub-word line structures (which may be understood as the first word line structure and the second word line structure) connecting the adjacent rows of semiconductor pillars are spaced from each other, occurrences of short circuit between the sub-word line structures may be reduced, and the electrical performance of the semiconductor device can be improved.
In some related technologies, after forming a trench accommodating the word line structure, it is difficult to form a flat surface at the bottom of the trench due to limitations of an etching process. Therefore, filling (e.g., an FCVD process) and multiple times of back etching are required to be performed on the bottom of the trench to construct a trench with a flat bottom face. After the formation of the trench with the flat bottom face, an initial word line structure may be formed on sidewalls and the bottom face of the trench. Subsequently, a portion of the initial word line structure at the bottom face of the trench is removed from a front side of an intermediate structure using a process such as punch etching, etc., to break the initial word line structure apart into two word line structures on the opposite sidewalls of the trench. However, in the above process, in an operation of performing filling and multiple times of back-etching on the trench, the process cost is high and the control is difficult. In addition, in an operation of removing the portion of the initial word line structure at the bottom face of the trench using, for example, punch etching, the process window is small, and it is difficult to completely break the initial word line structure apart at the bottom of the trench, which may cause a short circuit to occur at an electrical connection of the two word line structures and affect the electrical performance of the final semiconductor device.
In order to at least partially solve the above technical problem, according to at least one implementation of the present application, the word line structure is disposed between the adjacent rows of semiconductor pillars, and comprises sub-word line structures spaced apart from each other, and the adjacent rows of semiconductor pillars are connected with one of the sub-word line structures respectively. Since the sub-word line structures connected with the adjacent rows of semiconductor pillars are spaced from each other, occurrences of short circuit between the sub-word line structures may be reduced, and the electrical performance of the semiconductor device can be improved.
In an example, by taking the dynamic random access memory as an example, the semiconductor device may comprise a plurality of memory cells composed of capacitors and transistors, wherein the plurality of memory cells may be arranged in a form of a two-dimensional array. In order to further reduce a size of the two-dimensional array, the transistor may comprise a vertical gate transistor. In such a structure, an extending direction of a channel of the transistor is perpendicular to a surface of a substrate, and a source and a drain may be respectively formed at two ends in the extending direction, and a gate structure of the transistor may be formed on a side of the channel.
In one implementation of the present application, a vertical transistor such as a vertical Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), etc. may replace a conventional planar transistor as a pass transistor of the memory cell to reduce the footprint, coupling capacitance and interconnect routing complexity of the pass transistor. In some implementations, different from the planar transistor with an active area formed in the substrate, the vertical transistor may comprise the semiconductor pillar 100 extending vertically above the substrate (not shown) along the z direction. The semiconductor pillar 100 may extend above a top surface of the substrate, not only exposing a top surface of the semiconductor pillar 100, but also exposing one or more side faces of the semiconductor pillar 100, for example, the first side face 101 and the second side face 102.
In an example, a cross-sectional shape of the semiconductor pillar 100 in a plane (e.g., an x-y plane, wherein the x direction, y direction and z direction are perpendicular to one another) perpendicular to the z direction may comprise at least one of a rectangular shape, a trapezoidal shape, a circular shape or an oval shape. For example, a shape of the semiconductor pillar 100 may be a hexahedral shape, and comprise four side faces.
In other words, the semiconductor pillar 100 may have a cubic shape to expose four side faces thereof. However, it is understood by those skilled in the art that the semiconductor pillar 100 may have any suitable three-dimensional shape, for example, a polyhedron shape or a cylinder shape. A cross-section of the semiconductor pillar 100 in the plane perpendicular to the z direction may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an oval shape or any other suitable shape. It is to be understood that, consistent with the scope of the present application, for the semiconductor pillar having the cross-section of the circular shape or the oval shape in the above-mentioned plane, the semiconductor pillar may be still considered as having a plurality of side faces, such that the gate structure is in contact with one of the side faces of the semiconductor pillar. As described below with respect to the fabrication process, the semiconductor pillar 100 may be formed from the substrate by, for example, an etching or epitaxial process, and thus may have the same semiconductor material as the substrate.
As an alternative, a material of the substrate may include, but is not limited to, silicon (e.g., monocrystalline silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI) or any other suitable semiconductor materials. For example, the substrate may be a silicon substrate. Accordingly, the semiconductor pillar 100 may comprise at least one of the above-mentioned materials.
The vertical transistor may comprise a gate structure in contact with one side face (e.g., the first side face 101 or the second side face 102) of the semiconductor pillar 100. It may be understood that the gate structure and the word line structure 200 may be a continuous conductive structure, and the gate structure may be regarded as an extension of the word line structure 200 to couple to the semiconductor pillar 100; or the word line structure 200 may be regarded as an extension of the gate structure to couple to a peripheral circuit (not shown).
For example, in the case where the semiconductor pillar 100 comprises four side faces, the first side face 101 and the second side face 102 are two opposite side faces of the semiconductor pillar 100 in the y direction, and the word line structure 200 (which may be also understood as the gate structure) may be located on the first side face 101 or the second side face 102.
In some implementations, the vertical transistor may also comprise a source (not shown) and a drain (not shown) respectively formed at two ends of the semiconductor pillar 100 in the z direction, which may be understood as doped areas of the semiconductor pillar 100, and may be also called a source electrode and a drain electrode. It is to be noted that, the source may be disposed below the semiconductor pillar 100, and the drain may be disposed above the semiconductor pillar 100. However, according to actual needs, the source may be also disposed above the semiconductor pillar 100, and the drain may be disposed below the semiconductor pillar 100, which is not limited by the present application.
As an alternative, the source and the drain may be doped with any suitable P-type dopant that may comprise any one or a combination of boron (B) or gallium (Ga). As another alternative, the source and the drain may be doped with any suitable N-type dopant that may comprise any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source and the drain may be separated by the gate structure in the z direction. In other words, the gate structure is formed between the source and the drain along the z direction. Therefore, when a gate voltage applied to the gate structure is higher than a threshold voltage of the vertical transistor, the channel of the vertical transistor can be formed in the semiconductor pillar 100 between the source and the drain along the z direction (which may be understood as the gate control capability of the gate structure).
In one implementation of the present application, the word line structure 200 may comprise a word line dielectric layer 230 and a word line conductor layer, wherein the word line dielectric layer 230 is located between the semiconductor pillar 100 and the word line conductor layer. In an example, the word line conductor layer may further comprise a word line adhesion layer 220 and a word line metal layer 210.
For example, the word line structure 200 may comprise the word line dielectric layer 230 on the semiconductor pillar 100. Furthermore, the word line structure 200 may further comprise the word line adhesion layer 220 over the word line dielectric layer 230 and in contact with the word line dielectric layer 230, and the word line metal layer 210 over the word line adhesion layer 220 and in contact with the word line adhesion layer 220. In other words, the word line adhesion layer 220 is located between the word line dielectric layer 230 and the word line metal layer 210.
The word line dielectric layer 230 may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the word line dielectric layer 230 may comprise silicon oxide. Furthermore, the word line adhesion layer 220 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. Additionally, the word line metal layer 210 may comprise any suitable conductive material, for example, the word line metal layer 210 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The word line adhesion layer 220 may be used to block diffusion of metal materials in the word line metal layer 210, and may be also used to improve adhesion between the word line metal layer 210 and the word line dielectric layer 230.
In an example, as shown in
In other words, according to at least one implementation of the present application, the semiconductor device 1000 comprises the first word line structure 201, the second word line structure 202 and the semiconductor pillars 100 arranged in an array, wherein the first word line structure 201 and the second word line structure 202 each comprises the lower end faces 212 close to bottom ends of the semiconductor pillars 100 and the upper end faces 211 close to top ends of the semiconductor pillars 100. In an example, the upper end faces 211 of the plurality of first word line structures 201 and the upper end faces 211 of the plurality of second word line structures 202 are flush relative to the same reference plane in the z direction. In an example, the lower end faces 212 of the plurality of first word line structures 201 and the lower end faces 212 of the plurality of second word line structures 202 are flush relative to the same reference plane in the z direction. In an example, the upper end faces 211 of the plurality of first word line structures 201 and the upper end faces 211 of the plurality of second word line structures 202 are flush relative to the same reference plane in the z direction, and the lower end faces 212 of the plurality of first word line structures 201 and the lower end faces 212 of the plurality of second word line structures 202 are flush relative to the same reference plane in the z direction. It is to be noted that, due to the limitation of the process, the error range relative to the same reference plane described above may be between −10% to 10%.
As described above, in some examples, after a trench for accommodating the word line structure is formed, it is usually difficult to form a flat plane at the bottom of the trench due to limitations of an etching process. Furthermore, since a shape of an initial word line structure formed previously tends to a formation state of a sidewall and a bottom face of the trench, the cross-sectional shape of the initial word line structure in the x-y plane is not regular, and extending lengths of the plurality of initial word line structures in the z direction are not consistent.
In order to at least partially solve the above technical problems, according to at least one implementation of the present application, the word line structure is formed by removing part of the initial word line structure from a backside opposite to a front side of an intermediate structure, and an uneven portion of the initial word line structure on the bottom face of the trench is removed, so that the cross-section of the finally formed word line structure in the x-y plane may be formed as a regular rectangular shape, and the extending lengths of the plurality of word line structures in the z direction can be the same. The contents related to a fabrication method of a semiconductor device will be described in detail below in conjunction with the drawings.
Thus, in at least one implementation of the present application, at least one of the upper end faces and the lower end faces of the different first word line structures and the different second word line structures is flush relative to the reference plane in the z direction. This can improve the consistency of the word line structure, enhance the gate control capability of the word line structure (which may be understood as the gate structure), and improve the switching speed of the word line structure and the reliability of the semiconductor device.
It may be understood that, the lower end faces of the plurality of first word line structures and the lower end faces of the plurality of second word line structures being flush relative to the same reference plane in the z direction may be understood as lower end faces of the word line conductor layers of the plurality of first word line structures and lower end faces of the word line conductor layers of the plurality of second word line structures being flush relative to the same reference plane in the z direction. The upper end faces of the plurality of first word line structures and the upper end faces of the plurality of second word line structures being flush relative to the same reference plane in the z direction may be understood as upper end faces of the word line conductor layers of the plurality of first word line structures and upper end faces of the word line conductor layers of the plurality of second word line structures being flush relative to the same reference plane in the z direction.
With reference to
In an example, a cross-sectional shape of the third word line structure 203 in a plane (the y-z plane) perpendicular to the x direction comprises an L shape. As an alternative, the third word line structure 203 may be connected with a peripheral circuit (not shown) of the semiconductor device 1000, for example, with an electrode of the peripheral circuit through a vertical interconnect via (VIA).
It is to be noted that, the semiconductor pillar 100 comprises two ends that are opposite in the z direction, and the ends of the plurality of semiconductor pillars 100 in the z direction may be connected with each other through, for example, a bit line extending in the y direction. The word line dielectric layer 230 of the first word line structure 201 is located on the first side face 101 of the semiconductor pillar 100. The word line dielectric layer 230 of the second word line structure 202 is located on the second side face 102 of the semiconductor pillar 100. A word line dielectric layer 230 of the third word line structure 203 is located on the side face of the semiconductor pillar 100 and a surface of a portion where the adjacent semiconductor pillars 100 are connected with each other in the y direction.
In other words, the second sub-portion 203-2 of the third word line structure 203 extends along the y direction, and comprises the word line dielectric layer 230 and a word line conductor layer extending along the y direction, wherein the word line dielectric layer 230 and the word line conductor layer are sequentially formed on the surface of the portion where the adjacent semiconductor pillars 100 are connected with each other in the y direction.
Furthermore, with reference to
In other words, the isolation structure 400 may comprise a first isolation structure 401 and a second isolation structure 402. In an example, the semiconductor device 1000 may comprise the first isolation structure 401 that is located between the first word line structure 201 and the third word line structure 203 in the x direction. In an example, the semiconductor device 1000 may comprise the second isolation structure 402 that is located between the second word line structure 202 and the third word line structure 203 in the x direction. In an example, the semiconductor device 1000 may comprise the first isolation structure 401 and the second isolation structure 402, wherein the first isolation structure 401 is located between the first word line structure 201 and the third word line structure 203 in the x direction, and the second isolation structure 402 is located between the second word line structure 202 and the third word line structure 203 in the x direction.
In an example, the isolation structure 400 may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the isolation structure 400 may comprise silicon oxide.
In an example, withe reference to
The third word line structure 203 and the isolation structure 400 may form an isolation region U completely separating the first word line structure 201 and the second word line structure 202 in the semiconductor device 1000, wherein the isolation region U may effectively separate the first word line structure 201 and the second word line structure 202, which effectively reduces occurrences of short circuit between the word line structures and enhances an effect of improving the electrical performance of the semiconductor device.
Furthermore, the isolation region U may further comprise three sub-regions sequentially arranged along the x direction, wherein the first sub-region U1 and the third sub-region U3 are located on two sides of the second sub-region U2, and the third word line structure 203 is disposed in the second sub-region U2. The isolation structure 400 may be disposed in at least one of the first sub-region U1 or the third sub-region U3. The first sub-region U1 is closer to an edge of the semiconductor device 1000 than the second sub-region U2 and the third sub-region U3.
Furthermore, in order to reduce interference between the adjacent word line structures 200 in the semiconductor device 1000, the semiconductor device 1000 further comprises a back gate structure 300 that extends along the x direction, and the back gate structure 300 and the word line structures 200 are distributed alternately in the y direction.
The back gate structure 300 may comprise a back gate dielectric layer on a sidewall of the semiconductor pillar 100, and a back gate conductive layer 310 over the back gate dielectric layer and in contact with the back gate dielectric layer. By applying a reference voltage (e.g., a ground voltage) to the back gate conductive layer 310, the interference between the adjacent word line structures 200 in the semiconductor device 1000 may be reduced.
In an example, the back gate dielectric layer may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the back gate dielectric layer may comprise silicon oxide. Furthermore, the back gate conductive layer 310 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.
In order to simplify the fabrication process and save the production cost, the back gate dielectric layer may be formed in a fabrication process of forming the word line dielectric layer 230, and the word line dielectric layer 230 and the back gate dielectric layer may be fabricated using the same material. In other words, the word line dielectric layer 230 and the back gate dielectric layer may comprise an insulation material layer fabricated by the same material.
Likewise, in order to simplify the fabrication process and save the production cost, the back gate conductive layer 310 and the word line adhesion layer 220 may be fabricated using the same material. In other words, the word line adhesion layer 220 and the back gate conductive layer 310 may comprise a conductive material layer of the same material.
Furthermore, in one implementation of the present application, the back gate structure 300 comprises two ends (a first end 301 and a second end 302) opposite in the x direction. The first end 301 and the second end 302 are disposed opposite to the isolation structure 400 on two sides of the semiconductor pillar 100 in the y direction. For example,
In an example, with reference to
Since the back gate structure extends along the x direction and are distributed alternately with the word line structures in the y direction, in some related technologies, a lead-out line of the back gate structure (the lead-out line may be connected to the reference voltage) and a lead-out line of the word line structure are distributed alternately in the y direction as well, which will result in a small process window for both lead-out lines. If both lead-out lines are connected together accidentally, a short circuit will occur, which may affect the overall performance of the final semiconductor device.
In order to at least partially solve the above technical problem, according to at least one implementation of the present application, the ground structure is disposed within the isolation region, and is connected with the end of the back gate structure extending into the isolation region. On this basis, the end of the back gate structure is disposed opposite to the isolation structure on the two sides of the semiconductor pillar in the y direction. In other words, the end of the back gate structure is not adjacent to the first word line structure or the second word line structure. As such, the lead-out line of the first word line structure or the second word line structure and the lead-out line of the back gate structure are located in different portions in the x-y plane respectively. The process windows of both lead-out lines are enlarged. In addition, the possibility of accidental connection of both lead-out lines is reduced, and the overall performance of the semiconductor device is improved.
In addition, as shown in
In an example, as shown in
In other words, according to at least one implementation of the present application, the semiconductor device comprises the word line structure, the back gate structure and the semiconductor pillars arranged in an array, wherein the back gate structure comprises the bottom end face close to the bottom end of the semiconductor pillar and the top end face close to the top end of the semiconductor pillar. In an example, the top end faces of the plurality of back gate structures are flush relative to the same reference plane in the z direction. In an example, the bottom end faces of the plurality of back gate structures are flush relative to the same reference plane in the z direction. In an example, the top end faces of the plurality of back gate structures are flush relative to the same reference plane in the z direction, and the bottom end faces of the plurality of back gate structures are flush relative to the same reference plane in the z direction. It is to be noted that, due to the limitation of the process, the error range relative to the same reference plane described above may be between −10% to 10%.
At least one of the top end faces and the bottom end faces of the different back gate structures is flush relative to the reference plane in the z direction, which improves the consistency of the back gate structures and can enhance the connection stability of the back gate structures with a reference voltage output end.
It may be understood that, the back gate conductive layer of the back gate structure may comprise a bottom end face and a top end face that are opposite in the z direction. The bottom end faces of the plurality of back gate structures being flush relative to the same reference plane in the z direction may be understood as the bottom end faces of the back gate conductive layers of the different back gate structures being flush relative to the same reference plane in the z direction. The top end faces of the plurality of back gate structures being flush relative to the same reference plane in the z direction may be understood as the top end faces of the back gate conductive layers of the different back gate structures being flush relative to the same reference plane in the z direction.
Furthermore, as shown in
It may be understood that, the lower end face 212 of the first word line structure 201 and the lower end face 212 of the second word line structure 202 being lower than the bottom end face 312 of the back gate structure 300 in the z direction may be understood as the lower end faces of the word line conductor layers of the plurality of first word line structures 201 and the lower end faces of the word line conductor layers of the plurality of second word line structures 202 being lower than the bottom end face of the back gate conductive layer of the back gate structure 300 in the z direction; and the upper end faces 211 of the first word line structures 201 and the upper end faces 211 of the second word line structures 202 being higher than the top end face 311 of the back gate structure 300 in the z direction may be understood as the upper end faces of the word line conductor layers of the plurality of first word line structures 201 and the upper end faces of the word line conductor layers of the plurality of second word line structures 202 being higher than the top end face of the back gate conductive layer of the back gate structure 300 in the z direction.
Furthermore, as shown in
Furthermore, as an alternative, as described below in detail in conjunction with the drawings, a plurality of portions of the covering dielectric layer 600 located in different positions in the semiconductor device 1000 may be formed in different fabrication operations of the semiconductor device respectively, and since the same material is used for fabrication, the plurality of portions described above have no obvious boundary therebetween.
As such, according to the semiconductor device provided by at least one implementation of the present application, the semiconductor device may comprise the word line structure and a plurality of semiconductor pillars arranged in an array, wherein the plurality of semiconductor pillars are arranged in rows to form rows of semiconductor pillars, the word line structure is disposed between the adjacent rows of semiconductor pillars and comprises the first word line structure and the second word line structure spaced apart from each other, and the adjacent rows of semiconductor pillars are connected with one of the first word line structure and the second word line structure respectively. Since sub-word line structures (which may be understood as the first word line structure and the second word line structure) connecting the adjacent rows of semiconductor pillars are spaced from each other, occurrences of short circuit between the sub-word line structures may be reduced, and the electrical performance of the semiconductor device can be improved.
Some implementations of the present application provide a manufacturing method of a semiconductor device.
As shown in
Particular processes of various operations of the above-mentioned fabrication method 2000 in Example 1 will be illustrated in detail in conjunction with
As shown in
In an example, in one implementation of the present application, a material of fabricating the substrate (not shown) may be selected from any suitable semiconductor materials, which, for example, may include monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or III-V compounds, such as gallium arsenide, etc. As an alternative, monocrystalline silicon may be selected for the substrate.
In one implementation of the present application, the substrate may be, for example, a composite substrate for supporting a device structure thereon. A plurality of layers fabricated from different materials may be sequentially disposed through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, to form the substrate.
In one implementation of the present application, the substrate may comprise a substrate sacrificial layer. In an example, the substrate sacrificial layer may comprise a single layer, multiple layers or a suitable composite layer. For example, the substrate sacrificial layer may comprise one or more of any of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an alternative, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another alternative, the substrate sacrificial layer may comprise a dielectric layer, a sacrificial layer and a dielectric layer disposed sequentially, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. As yet another alternative, the substrate sacrificial layer may comprise one or more of any of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may comprise monocrystalline silicon or polysilicon. In an example, in one implementation of the present application, an example material of forming the sacrificial layer may comprise polysilicon.
Furthermore, part of a region of the substrate may also form a well region formed by doping an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may comprise any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some implementations of the present application, the well region may be fabricated by selecting the same dopant, or fabricated by selecting different dopants, and further, a doping concentration of the well region may be the same or may be different, which is not limited by the present application.
After the formation of the substrate, for example, a dry etching process or a combination of a dry etching process and a wet etching process may be used for formation. Furthermore, other manufacturing processes, for example, a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., may be also performed to remove part of the substrate to form a plurality of openings (not shown) distributed as being spaced apart along the x direction, wherein the remaining of the substrate is also distributed as being spaced apart in the x direction to form the plurality of semiconductor layers 113. Thereafter, the plurality of openings may be filled through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof to form the separation layer 112. The separation layer 112 may be formed using any suitable dielectric materials. In an example, the separation layer 112 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric.
As shown in
The plurality of semiconductor pillars 100 are arranged in an array in an x-y plane, wherein the plurality of semiconductor pillars 100 are arranged in rows in the x direction, for example, a first row of semiconductor pillars 100-1 and a second row of semiconductor pillars 100-2. Furthermore, the plurality of rows of semiconductor pillars are arranged as being spaced apart in the y direction.
In an example, extending lengths of the plurality of first trenches 114 in the z direction may be different. Likewise, extending lengths of the plurality of second trenches 115 in the z direction may be different. As described above, initial word line structures and initial back gate structures will be subsequently formed in the first trenches and the second trenches, such that extend lengths of the plurality of initial word line structures in the z direction may be also different, and extending lengths of the plurality of initial back gate structures in the z direction may be also different. By removing part of the initial word line structures and part of the initial back gate structures from a backside opposite to the first side, word line structures having flush surfaces in the z direction on the backside and back gate structures having flush surfaces in the z direction on the backside may be formed, thereby improving the structural consistency of memory cells in the semiconductor device and the impact of a structure difference on the performance of the semiconductor device. As described above, the extending lengths of the plurality of initial word line structures in the z direction and the extending lengths of the plurality of initial back gate structures in the z direction are allowed to be different, which can reduce the difficulty of the etching process and increase the process window of fabricating the semiconductor device.
As shown in
In an example, the fabrication method 2000 of the semiconductor device further comprises forming an initial back gate structure 300′ extending along the x direction in a fabrication process of forming the initial word line structure 200′, wherein the initial word line structure 200′ and the initial back gate structure 300′ are disposed on two sides of a row of the semiconductor pillars along the y direction. It is to be noted that, the initial back gate structure may be also formed in a different fabrication process from the initial word line structure, which is not limited by the present application.
In one implementation of the present application, forming the initial word line structure 200′ comprises: forming the initial word line structure 200′ in the first trench 114 through one or more thin film deposition processes that may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, wherein a first isolation layer 230′ is formed on a sidewall and a bottom of the first trench 104; and sequentially forming an initial gate adhesion layer 220′ and an initial gate metal layer 210′ on a surface of the first isolation layer 230′. The initial gate adhesion layer 220′ and the initial gate metal layer 210′ may be referred to as a first conductive layer.
In an example, the first isolation layer 230′ may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the first isolation layer 230′ may comprise silicon oxide. Furthermore, the initial gate adhesion layer 220′ may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the initial gate metal layer 210′ may comprise any suitable conductive material, for example, the gate metal layer 220 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The initial gate adhesion layer 220′ is used to block diffusion of metal materials in the initial gate metal layer 210′, and is further used to improve adhesion between the initial gate metal layer 210′ and the first isolation layer 230′.
In an example, a cross-sectional shape of the initial word line structure 200′ in the x-y plane may comprise at least one of a rectangular shape, a trapezoidal shape, a circular shape or an oval shape.
In an example, after the formation of the initial word line structure 200′, at least the remaining space of the first trench 114 may be also filled with a dielectric filling layer 240. The dielectric filling layer 240 may fill the remaining space of the first trench 114 and cover part of a surface of the formed initial word line structure 200′. The dielectric filling layer 240 may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. In an example, the dielectric filling layer 240 and the first isolation layer 230′ may be fabricated from the same material.
In one implementation of the present application, forming the initial back gate structure 300′ comprises: forming the initial back gate structure 300′ in the second trench 115 through one or more thin film deposition process that may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, wherein an initial back gate dielectric layer 320′ is formed on a sidewall and a bottom of the second trench 115; and the remaining space of the second trench 105 is filled with an initial back gate conductive layer 310′.
In an example, the initial back gate dielectric layer 320′ may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the initial back gate dielectric layer 320′ may comprise silicon oxide. Furthermore, the initial back gate conductive layer 310′ may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.
As described above, in order to simplify the fabrication process and save the production cost, the initial back gate structure 300′ may be formed in a fabrication process of forming the initial word line structure 200′. In an example, the initial back gate dielectric layer 320′ may be formed in the fabrication process of forming the initial word line dielectric layer 230′, and the initial word line dielectric layer 230′ and the initial back gate dielectric layer 320′ are fabricated using the same material. In other words, the initial word line dielectric layer 230′ and the initial back gate dielectric layer 320′ may comprise insulation material layers fabricated from the same material. Likewise, in order to simplify the fabrication process and save the production cost, the initial back gate conductive layer 310′ and the initial gate adhesion layer 220′ may be fabricated using the same material. In other words, the initial gate adhesion layer 220′ and the initial back gate conductive layer 310′ may comprise conductive material layers of the same material.
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In an example, as shown in
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In an example, as shown in
Furthermore, as shown in
As shown in
In an example, the isolation structure 400 may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric.
Furthermore, in one implementation of the present application, the isolation structure 400 has a higher etching selectivity ratio than the first isolation layer 230′ (as shown in
As shown in
Through the above operations, the remaining first isolation layer 230′ of the initial first word line structure 201′ forms a word line dielectric layer 230 of the first word line structure 201; and the remaining first isolation layer 230′ of the initial second word line structure 202′ forms a word line dielectric layer 230 of the second word line structure 202. The remaining first conductive layer of the initial first word line structure 201′ forms a word line conductor layer of the first word line structure 201, and the remaining first conductive layer of the initial second word line structure 202′ forms a word line conductor layer of the second word line structure 202. A lower end face of the word line conductor layer of the first word line structure 201 is higher than a lower end face of the word line dielectric layer 230 of the first word line structure 201 in the z direction; and a lower end face of the word line conductor layer of the second word line structure 202 is higher than a lower end face of the word line dielectric layer 230 of the second word line structure.
In an example, as shown in
As shown in
Through the above operations, the remaining first isolation layer 230′ of the initial first word line structure 201′ forms a word line dielectric layer 230 of the first word line structure 201; and the remaining first isolation layer 230′ of the initial second word line structure 202′ forms a word line dielectric layer 230 of the second word line structure 202. The remaining first conductive layer of the initial first word line structure 201′ forms a word line conductor layer of the first word line structure 201, and the remaining first conductive layer of the initial second word line structure 202′ forms a word line conductor layer of the second word line structure 202. The word line conductor layer of the first word line structure 201 and the word line conductor layer of the second word line structure 202 may each comprise a word line adhesion layer 220 and a word line metal layer 210.
Furthermore, with reference to
In an example, as shown in
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In an example, both the first covering dielectric layer 600-1 and the second covering dielectric layer 600-2 may comprise any suitable dielectric material, for example, an oxide. In an example, both the first covering dielectric layer 600-1 and the second covering dielectric layer 600-2 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, both the first covering dielectric layer 600-1 and the second covering dielectric layer 600-2 may comprise silicon oxide.
Furthermore, as shown in
Furthermore, when materials for fabricating the first covering dielectric layer 600-1, the second covering dielectric layer 600-2, the third covering dielectric layer 600-3 and the second separation layer 112″ are the same, the first covering dielectric layer 600-1, the second covering dielectric layer 600-2, the third covering dielectric layer 600-3 and the second separation layer 112″ have no obvious boundary therebetween.
Particular processes of various operations of the above-mentioned fabrication method 2000 in Example 2 will be illustrated in detail in conjunction with
Since the contents involved in the fabrication method 2000 of the semiconductor device as described in Example 1 above may be completely or partially applicable to the fabrication method of the semiconductor device described here (Example 2), the contents relevant or similar thereto are no longer repeated. However, those skilled in the art may understand that, the semiconductor device 1000 (as shown in
With reference to
In an example, after exposing the initial word line structure 200′, a dry etching process or a combination of a dry etching process and a wet etching process may be continued to be used for formation. Furthermore, other manufacturing processes, e.g., a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., may be also performed to subsequently expand the first opening 13 along the z direction to form a second opening 14. The second opening 14 comprises a first second opening 14-1 and a second second opening 14-2, wherein part of the remained initial word line structure 200′ is spaced between the first second opening 14-1 and the second second opening 14-2 in the x direction. Part of the remained initial word line structure 200′ forms an initial third word line structure 203′ that may be used to form a third word line structure 203.
The second opening 14 comprising the first second opening 14-1 and the second second opening 14-2 splits the initial word line structure 200′ into two portions, i.e., the initial first word line structure 201′ and the initial second word line structure 202′.
In an example, as shown in
As shown in
According to the fabrication method of the semiconductor device provided by at least one implementation of the present application, the semiconductor device may comprise the word line structure and the semiconductor pillars arranged in an array, wherein the plurality of semiconductor pillars are arranged in rows to form rows of semiconductor pillars, the word line structure is disposed between the adjacent rows of semiconductor pillars and comprises the first word line structure and the second word line structure spaced apart from each other, and the adjacent rows of semiconductor pillars are connected with one of the first word line structure and the second word line structure respectively. Since sub-word line structures (which may be understood as the first word line structure and the second word line structure) connecting the adjacent rows of semiconductor pillars are spaced from each other, occurrences of short circuit between the sub-word line structures may be reduced, and the electrical performance of the semiconductor device can be improved.
Additionally,
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As an alternative, the three-dimensional semiconductor device may comprise at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
The memory system 30000 may comprise a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device as described in any implementation above, which is no longer repeated in the present application. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH, and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the region selected by the address.
In some implementations, the three-dimensional memory system may be implemented as, for example, a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multi-media card in the forms of MMC, eMMC, RS-MMC and micro-MMC, a secure digital card in the forms of SD, mini-SD and micro-SD, a memory device of a Personal Computer Memory Card International Association (PCMCIA) card type, a memory device of a Peripheral Component Interconnection (PCI) type, a memory device of a PCI-Express (PCI-E) type, a Compact Flash (CF) card, a smart media card, or a memory stick, etc. The memory system provided by the present application, as it is disposed with the semiconductor device provided by the present application, has the same advantageous effect as the semiconductor device, which is not repeated herein.
The present application provides a fabrication method of a semiconductor device, a semiconductor device and a memory system which can at least partially solve the above-mentioned problems existing in the related technologies or other problems in the field.
An aspect of the present application provides a semiconductor device which comprises a plurality of semiconductor pillars extending along a first direction and each comprising at least one side face, wherein the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction; and a word line structure located between a first row of semiconductor pillars and a second row of semiconductor pillars that are adjacent to each other, and comprising a first word line structure and a second word line structure spaced apart from the first word line structure, wherein the first word line structure is connected with a side face of the first row of semiconductor pillars; and the second word line structure is connected with a side face of the second row of semiconductor pillars.
In one implementation of the present application, the word line structure further comprises a third word line structure disposed between the first word line structure and the second word line structure in the second direction, wherein the third word line structure comprises a first sub-portion and a second sub-portion connected with each other; the first sub-portion extends on the side face of the semiconductor pillar along the first direction; and the second sub-portion extends along a third direction perpendicular to the first direction and the second direction.
In one implementation of the present application, a cross-sectional shape of the third word line structure in a plane perpendicular to the second direction comprises an L shape.
In one implementation of the present application, the semiconductor device further comprises an isolation structure.
The isolation structure is located between the first word line structure and the third word line structure in the second direction, and/or the isolation structure is located between the second word line structure and the third word line structure in the second direction.
In one implementation of the present application, the isolation structure extends along the first direction, and is connected with the second sub-portion in the second direction.
In one implementation of the present application, the semiconductor device further comprises a back gate structure extending along the second direction, wherein the word line structure and the back gate structure are distributed alternately in the third direction.
In one implementation of the present application, the back gate structure comprises two ends that are opposite in the second direction, wherein the ends and the isolation structure are oppositely disposed on two sides of the semiconductor pillars in the third direction; and the semiconductor device further comprises a ground structure connected with the ends.
In one implementation of the present application, the ends are disposed above the ground structure along the first direction.
In one implementation of the present application, the first word line structure and the second word line structure extend on the side face of the semiconductor pillar along the first direction respectively, and each comprises an upper end face and a lower end face that are opposite in the first direction, wherein a plurality of the upper end faces are flush in the first direction; and/or a plurality of the lower end faces are flush in the first direction.
In one implementation of the present application, the first word line structure and the second word line structure extend on the side face of the semiconductor pillar along the first direction respectively, and each comprises an upper end face and a lower end face that are opposite in the first direction; and the semiconductor device further comprises a back gate structure extending along the second direction, and the back gate structure comprises a top end face and a bottom end face that are opposite in the first direction, wherein in the first direction, the upper end face is higher than the top end face; and/or the lower end face is lower than the bottom end face.
Another aspect of the present application provides a method of fabricating a semiconductor device, comprising: forming a plurality of semiconductor pillars on a first side of a substrate, wherein the plurality of semiconductor pillars extend along a first direction and each comprise at least one side face, and the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction; forming an initial word line structure, wherein the initial word line structure is located between adjacent rows of the semiconductor pillars; removing part of the initial word line structure along the second direction to form an initial first word line structure and an initial second word line structure; and removing part of the initial first word line structure and part of the initial second word line structure from a second side opposite to the first side to form a first word line structure and a second word line structure.
In one implementation of the present application, the method further comprises: in a fabrication process of forming the initial word line structure, forming an initial back gate structure extending along the second direction, wherein the initial word line structure and the initial back gate structure are disposed on two sides of a row of the semiconductor pillars along a third direction, wherein the third direction is perpendicular to the first direction and the second direction.
In one implementation of the present application, the initial back gate structure comprises two ends that are opposite in the second direction; and the part of the initial word line structure removed along the second direction is opposite to the ends in the third direction.
In one implementation of the present application, the method further comprises: in a fabrication process of removing the part of the initial first word line structure and the part of the initial second word line structure to form the first word line structure and the second word line structure, removing part of the initial back gate structure from the second side to form a back gate structure.
In one implementation of the present application, removing the part of the initial word line structure along the second direction comprises: removing a first portion and a second portion of the initial word line structure sequentially along the second direction, wherein the part of the initial word line structure is spaced between the first portion and the second portion in the second direction.
In one implementation of the present application, the method further comprises: in a fabrication process of removing the part of the initial first word line structure and the part of the initial second word line structure to form the first word line structure and the second word line structure, retaining the part of the initial word line structure spaced therebetween, to form a third word line structure.
In one implementation of the present application, the initial word line structure comprises a first conductive layer and a first isolation layer from inside to outside, and removing the part of the initial first word line structure and the part of the initial second word line structure from the second side opposite to the first side to form the first word line structure and the second word line structure comprises: removing a part of the substrate, a part of the first isolation layer of the initial first word line structure and a part of the first isolation layer of the initial second word line structure from the second side, to expose the first conductive layer of the initial first word line structure and the first conductive layer of the initial second word line structure; continuing to remove a part of the first isolation layer of the initial first word line structure and a part of the first isolation layer of the initial second word line structure along the first direction, and removing a part of the first conductive layer of the initial first word line structure and a part of the first conductive layer of the initial second word line structure, to form the first word line structure and the second word line structure, wherein in the first direction, a lower end face of the remaining first conductive layer of the first word line structure is higher than a lower end face of the remaining first isolation layer of the first word line structure; and in the first direction, a lower end face of the remaining first conductive layer of the second word line structure is higher than a lower end face of the remaining first isolation layer of the second word line structure.
In one implementation of the present application, the method further comprises: after removing the part of the initial word line structure along the second direction, forming an isolation structure in a gap formed after removing the part of the initial word line structure; and in a fabrication process of continuing to remove a part of the first isolation layer of the initial first word line structure and a part of the first isolation layer of the initial second word line structure, the continuing to remove a part of the first isolation layer of the initial first word line structure and a part of the first isolation layer of the initial second word line structure stops at the isolation structure.
In one implementation of the present application, a cross-sectional shape of the initial word line structure in a plane perpendicular to the first direction comprises at least one of a rectangular shape, a trapezoidal shape, a circular shape or an oval shape.
Yet another aspect of the present application provides a memory system, comprising the semiconductor device provided by an aspect of the present application, and a controller coupled with the semiconductor device, wherein the controller is configured to store data to the semiconductor device.
According to the semiconductor device and the fabrication method, and the memory system provided by at least one implementation of the present application, the semiconductor device may comprise the word line structure and a plurality of semiconductor pillars arranged in an array, wherein the plurality of semiconductor pillars are arranged in rows to form rows of semiconductor pillars, the word line structure is disposed between the adjacent rows of semiconductor pillars and comprise the first word line structure and the second word line structure spaced apart from each other, and the adjacent rows of semiconductor pillars are connected with one of the first word line structure and the second word line structure respectively. Since sub-word line structures (which may be understood as the first word line structure and the second word line structure) connecting the adjacent rows of semiconductor pillars are spaced from each other, occurrences of short circuit between the sub-word line structures may be reduced, and the electrical performance of the semiconductor device can be improved.
Although an example fabrication method and an example structure of the semiconductor device have been described here, it may be understood that one or more features may be omitted, substituted or added from a structure of the semiconductor device. Furthermore, the listed materials of various layers are merely examples.
The above descriptions are merely descriptions of some implementations of the present application and applied technical principles. Those skilled in the art should understand that, the protection scope of the present application is not limited to the technical solutions formed by a selected combination of the above technical features, but should also encompass other technical solutions formed by any combination of the above technical features or equivalent features thereof without departing from the technical concept, for example, technical solutions formed by interchanging of the above features and the technical features with similar functions as disclosed (but not limited to those) in the present application.
The above descriptions are merely descriptions of implementations of the present application and applied technical principles. Those skilled in the art should understand that, the protection scope of the present application is not limited to the technical solutions formed by specific combinations of the above technical features, but should also encompass other technical solutions formed by any combination of the above technical features or equivalent features thereof, without departing from the technical concept, for example, technical solutions formed by interchanging the above features with the technical features with similar functions as disclosed (but not limited to those) in the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311461867.2 | Nov 2023 | CN | national |
