Semiconductor Devices and Method for Fabricating the Same

Abstract

Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole. The example method forms a copper interconnect by filling the trench and via hole with copper and performing a planarization process, deposits a Ta/TaN layer over the substrate including the copper interconnect, removes some portion of the Ta/TaN layer so that the Ta/TaN layer remains only on the copper interconnect, deposits a second insulating layer over the substrate including the Ta/TaN layer, forms a via hole through the second insulating layer by removing some portion of the second insulating layer, and fills the via hole with a conductive material to complete a via.

Description

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and, more particularly, to methods for fabricating a copper interconnect of a semiconductor device.

BACKGROUND

With the high-integration of semiconductor devices, known metals such as tungsten, copper, or alloys thereof have been turned out to be unsuitable for an interconnect material of a semiconductor device because they have a high specific resistance and cause electro migration (EM) or stress migration (SM), thereby deteriorating reliability of the semiconductor device. EM is a defect due to the increase in current density within a metal interconnect. In other words, EM is created because the current density increases by high-speed operation of the semiconductor device according to a fine interconnect pattern. SM is a creep rupture (failure) mode caused by imposing tensile mechanical stress on the metal interconnect. The mechanical stress is created by the difference in thermal expansion coefficient between the metal interconnect and an insulating layer to protect the metal interconnect. The mechanical stress increases as the width of the metal interconnect becomes narrower.

To obviate the above-mentioned problems, copper has been suggested as an alternative for known interconnect materials. Copper has a low specific resistance and ensures reliability of a semiconductor device. In addition, copper alloy has high corrosion-resistance and ensures reliability of the interconnect although it has a relatively high specific resistance in comparison with copper.

A copper dual damascene process, which inlays metal in an interconnect line, has been developed as an alternative because efforts to improve a copper etching method proved to be unsuccessful. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction although it had been confronted with barriers in terms of apparatus due to completely different structures and across-the-board changes.

FIGS. 1 a through 1d are cross-sectional views illustrating a known process of fabricating a copper interconnect of a semiconductor device. Referring to FIG. 1a, an insulating layer 10 is deposited on a substrate with at least one predetermined structure. A trench and via hole is formed through the insulating layer 10 by using a dual damascene process. A barrier layer 11 is then deposited along the bottom and the sidewalls of the trench and via hole. The trench and via hole is filled with copper by using an electrochemical plating (ECP) process and then planarized by using a chemical mechanical polishing (CMP) process to complete a lower copper interconnect 12.

Referring to FIG. 1b, a SiN layer is deposited over the structure of FIG. 1a to form a capping layer 13. The SiN layer has a thickness of about 700. Referring to FIG. 1c, an interlayer dielectric (ILD) layer 14 is deposited on the capping layer 13. Referring to FIG. 1d, some portion of the ILD layer 14 and capping layer 13 is removed by an etching process using a predetermined pattern to form a via hole. The via hole is then filled with a conductive material to complete a via 15.

However, the above-described known method of forming a copper interconnect has several problems. First, if there is an oxidized area on the surface of the copper interconnect, the adhesion between the copper interconnect and the capping layer weakens and, as a result, the SiN layer as the capping layer 13 loosens. Constantly, the copper of the interconnect is diffused into the portion in which the SiN layer gets loose. Such copper diffusion may cause a short circuit between interconnects. Second, when the via is formed to connect the upper and lower interconnects, the upper interconnect may not be connected with the lower interconnect if the SiN layer as the capping layer within the via hole is completely removed. Third, the SiN layer may raise the total dielectric constant of the upper and lower interconnects because the SiN layer itself has a high dielectric constant.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a through 1d are cross-sectional views illustrating a known process of fabricating a copper interconnect of a semiconductor device.

FIGS. 2 a through 2e are cross-sectional views illustrating an example process of fabricating a copper interconnect of a semiconductor device.

DETAILED DESCRIPTION

FIGS. 2 a through 2e are cross-sectional views illustrating an example process of fabricating a copper interconnect of a semiconductor device. Referring to FIG. 2a, a substrate (not shown) having at least one predetermined structure is prepared. A first insulating layer 20 is deposited over the substrate. A trench and via hole are formed through the first insulating layer 20 by using a dual damascene process. A barrier layer 21 is then formed along the bottom and the sidewalls of the trench and via hole. The barrier layer 21 is preferably made of Ta/TaN. The trench and via hole is filled with copper by using an ECP process and then planarized by using a CMP process to form a lower copper interconnect 22. In the illustrated example, the barrier layer 21 made of Ta/TaN prevents not only the copper of the lower interconnect from being diffused into the first insulating layer 20, but also impurities such as oxygen in the first insulating layer 20 from being diffused into the lower copper interconnect 22.

Referring to FIG. 2b, a Ta/TaN layer 23 for a capping layer is deposited over the structure of FIG. 2a.

Referring to FIG. 2c, a photoresist pattern is formed on the structure of FIG. 2b by a photolithography process using the same mask that was used in the above-mentioned dual damascene process. The Ta/TaN layer 23 on the first insulating layer 20 is removed by using the photoresist pattern so that the Ta/TaN layer 23 remains only on the lower copper interconnect 22. Thus, a capping layer 24 of Ta/TaN is formed on the lower copper interconnect.

Referring to FIG. 2d, a second insulating layer 25 is deposited over the structure of FIG. 2c.

Referring to FIG. 2e, some portion of the second insulating layer 25 is removed by an etching process using a predetermined photoresist pattern. Thus, a via hole is formed through the second insulating layer 25. The via hole is then filled with a conductive material to complete a via 26. The via 26 connects the lower copper interconnect 22 with an upper metal interconnect (not shown) to be formed by a later unit process. As above-mentioned, the conventional technology using the SiN layer as the capping layer has to completely remove the SiN layer within the via hole in order to complete the electrical connection between the upper copper interconnect and the lower metal interconnect. In the illustrated example process, however, the via achieves a good electric connection between the lower copper interconnect and the upper metal interconnect although the capping layer within the via hole is not completely removed, because the Ta/TaN layer with good electric characteristics is used as the capping layer.

From the foregoing, persons of ordinary skill in the art will appreciate that by using the Ta/TaN layer as the capping layer instead of the SiN layer, the above-described methods of fabricating a copper interconnect enhance the adhesion between the capping layer and the lower copper interconnect, prevent a short circuit between interconnects, which is caused because the capping layer is not completely removed during the via formation process, and obviate increase in dielectric constant of total interconnects due to the capping layer with the high dielectric constant.

While the examples herein have been described in detail with reference to example embodiments, it is to be understood that the coverage of this patent is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the sprit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a first insulating layer formed on a substrate having at least one predetermined structure; a trench and a first via hole formed through the first insulating layer; a barrier layer formed along the sidewalls and the bottom of the trench and first via hole; a copper interconnect formed by filling the trench and first via hole with copper; a Ta/TaN layer formed only on the copper interconnect and the barrier layer; a second insulating layer formed over the substrate including the Ta/TaN layer; a second via hole formed through the second insulating layer; and a via formed by filling the second via hole with a conductive material.

2. A semiconductor device as defined by claim 1, wherein the barrier layer is made of Ta/TaN.

3. A semiconductor device as defined by claim 1, wherein the copper interconnect is formed by using an electrochemical plating process.

4. A semiconductor device as defined by claim 1, wherein the Ta/TaN layer is used as a capping layer.

5. A semiconductor device as defined by claim 1, wherein a side wall of the Ta/TaN layer is contacted with the second insulating layer.