The present disclosure relates to a semiconductor device and, more particularly, to methods for fabricating a copper interconnect of a semiconductor device.
With the high-integration of semiconductor devices, known metals such as tungsten, copper, or alloys thereof have been turned out to be unsuitable for an interconnect material of a semiconductor device because they have a high specific resistance and cause electro migration (EM) or stress migration (SM), thereby deteriorating reliability of the semiconductor device. EM is a defect due to the increase in current density within a metal interconnect. In other words, EM is created because the current density increases by high-speed operation of the semiconductor device according to a fine interconnect pattern. SM is a creep rupture (failure) mode caused by imposing tensile mechanical stress on the metal interconnect. The mechanical stress is created by the difference in thermal expansion coefficient between the metal interconnect and an insulating layer to protect the metal interconnect. The mechanical stress increases as the width of the metal interconnect becomes narrower.
To obviate the above-mentioned problems, copper has been suggested as an alternative for known interconnect materials. Copper has a low specific resistance and ensures reliability of a semiconductor device. In addition, copper alloy has high corrosion-resistance and ensures reliability of the interconnect although it has a relatively high specific resistance in comparison with copper.
A copper dual damascene process, which inlays metal in an interconnect line, has been developed as an alternative because efforts to improve a copper etching method proved to be unsuccessful. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction although it had been confronted with barriers in terms of apparatus due to completely different structures and across-the-board changes.
a through 1d are cross-sectional views illustrating a known process of fabricating a copper interconnect of a semiconductor device. Referring to
Referring to
However, the above-described known method of forming a copper interconnect has several problems. First, if there is an oxidized area on the surface of the copper interconnect, the adhesion between the copper interconnect and the capping layer weakens and, as a result, the SiN layer as the capping layer 13 loosens. Constantly, the copper of the interconnect is diffused into the portion in which the SiN layer gets loose. Such copper diffusion may cause a short circuit between interconnects. Second, when the via is formed to connect the upper and lower interconnects, the upper interconnect may not be connected with the lower interconnect if the SiN layer as the capping layer within the via hole is completely removed. Third, the SiN layer may raise the total dielectric constant of the upper and lower interconnects because the SiN layer itself has a high dielectric constant.
a through 1d are cross-sectional views illustrating a known process of fabricating a copper interconnect of a semiconductor device.
a through 2e are cross-sectional views illustrating an example process of fabricating a copper interconnect of a semiconductor device.
a through 2e are cross-sectional views illustrating an example process of fabricating a copper interconnect of a semiconductor device. Referring to
Referring to
Referring to
Referring to
Referring to
From the foregoing, persons of ordinary skill in the art will appreciate that by using the Ta/TaN layer as the capping layer instead of the SiN layer, the above-described methods of fabricating a copper interconnect enhance the adhesion between the capping layer and the lower copper interconnect, prevent a short circuit between interconnects, which is caused because the capping layer is not completely removed during the via formation process, and obviate increase in dielectric constant of total interconnects due to the capping layer with the high dielectric constant.
While the examples herein have been described in detail with reference to example embodiments, it is to be understood that the coverage of this patent is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the sprit and scope of the appended claims.
Number | Date | Country | Kind |
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10-2003-0100705 | Dec 2003 | KR | national |
This application is a divisional of U.S. application Ser. No. 11/026,941, filed Dec. 30, 2004, which claims the benefit of Korean Application No. 10-2003-0100705, filed on Dec. 30, 2003, which are hereby incorporated herein by reference in their entirety.
Number | Date | Country | |
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Parent | 11026941 | Dec 2004 | US |
Child | 11745562 | May 2007 | US |