The present invention relates generally to integrated circuit (IC) design rule generation, and more particularly, to a method for defining distances between device channel regions to well edges to alleviate well proximity effects.
N-well proximity effect is a newly discovered phenomenon since 130 nm technologies. In case of a PMOS device inside an N-well silicon, after a Shallow Trench Isolation (STI) was fabricated, a photoresist is put on the silicon to block ion implantation so that N-well region is defined. Since the N-well implant requires high energy and large dose ions, so that the photoresist has to be very thick which inevitably has tall slanted sidewalls. During ion implantation, ions scattered laterally just inside the photo-resist edge will be able to emerge from the photo-resist. These may be implanted into the silicon within the area that will become a transistor active-region later in the process. The depth and concentration of the implant ions will depend on the angle and energy of the scattered ions. The details of the lateral scattering depend on the mass of the incoming ions and the mass of the species in the photo-resist from which they are scattered. Whether or not there is a significant effect on the threshold voltage depends on the overall width of the device, the location of the device relative to the mask edge, the lateral range of the effect, and the density and depth of the scattered ions relative to those intentionally implanted in that region.
In order to prevent device variations due to N-well proximity effects, sufficient spacing between the device active region and the N-well edges is needed.
Eq. 1 is based on averaging areas between active regions and well edges, and can model implant behaviors accurately.
While conventional methods, such as the one represented by Eq. 1, are available for calculating the distance necessary for the spacing between a device and the N-well edges, however, these solutions require long complicated equations calculating many parameters in order to get an accurate spacing distance between the device and the N-well edges. Such methods are very difficult to be put into practical use due to their complexities.
Therefore, it is desirable to device a simple yet effective method for calculating the necessary spacing between a device active region and the N-well edges in order to alleviate the N-well proximity effects.
In view of the foregoing, a semiconductor device is disclosed for alleviating well proximity effects. The semiconductor device comprises a well in a substrate, and a transistor with an active region and a gate of 0.13 um or less in gate length, wherein the gate is entirely within or extended to outside of the well, and a minimum spacing between an edge of the active region and an edge of the well is at least about 3 times the gate length.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The drawings accompanying and forming part of this specification are included to depict certain aspects of the invention. A clearer conception of the invention, and of the components and operation of systems provided with the invention, will become more readily apparent by referring to the exemplary, and therefore non-limiting, embodiments illustrated in the drawings, wherein like reference numbers (if they occur in more than one view) designate the same elements. The invention may be better understood by reference to one or more of these drawings in combination with the description presented herein. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale.
The invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well known components and processing techniques are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this detailed description.
As aforementioned that the well proximity effects exist in more advanced, such as 0.13 um, processes. This invention provides a simple method to analyze the well proximity effects based on a trajectory of each implant particle.
Where, kF, k′ and k are wave number of fixed, scattered and incoming ions, respectively; M and m are the masses of fixed and incoming ions; and h is Plack constant over 2π. Eqs. 1 and 2 indicate the conservation of momentum and Eq. 3 indicates the conservation of energy.
The scattered angle θ′ can be readily obtained by solving Eqs. 1, 2 and 3 as:
(m/M) sin2(θ′)+cos2(θ)=cos2(θ′−θ) Eq. 4
In general, Eq. 4 cannot be solved analytically. However, the physical meaning can be readily extracted in some particular cases:
(1) m=M. In this case, θ′=θ.
(2)m <<M. The first term on the left hand side of Eq. 4 is zero, such that θ′=θ or 180°. When the implant ion 210 is very light comparing with the fixed ion 220, it will be bounced back when encounter the fixed ion 220. In this case θ′=180 is a correct solution.
(3) m>>M. The ratio m/M becomes very large such that sin(θ′)≈0 to make both sides between 0 and 1. Therefore, θ′=0. When the implant ion 210 is very heavy, it just travels through the photoresist.
For m<M, the implant ions may be recoiled such that negative scattered ranges are possible. But negative scattered ranges cause no harm because the ions will not reach the substrate surface. If the scattered angle is close to 90 degrees, the scattered range may be very wide. Otherwise, the scattered ranges are usually smaller than H.
For ion implantation in integrated circuit technologies, the incoming ions are usually Boron (B, atomic weight=13), Arsenic (As, atomic weight=33), or Phosphorous (P, atomic weight=15), while the photo-resist material is usually composed of Carbon (C, atomic weight=12), Oxygen (O, atomic weight=16), or Hydrogen (H, atomic weight=1). Except Boron ions are very close to Carbon or Oxygen ions in atomic weight, either Arsenic or Phosphorous ions are much heavier than the fixed ions in the photo-resist 250. For a worst case scenario, assume that m=M, which causes θ′=0 according to Eq. 4, then Eq. 5 can be simplified as:
R=(H/2)·sin(2θ) Eq. 6
The maximum value of sin(2θ) is 1. Therefore, the maximum scattered range for m=M is:
R=(H/2) Eq. 7
where θ′=θ=45°.
It is understood that N-well proximity effect should be avoided. One way to avoid the well proximity effect is to build devices away from the edge area 160. On the other hand, the distance to the well edge should be kept at a minimum to minimize the layout area. Therefore, a properly defined layout design rule is essential. For a transistor with an active region and a gate of 0.13 um or less in gate length and is entirely within the well, a minimum spacing between an edge of the active region and an edge of the well is at least about 3 times the gate length. Besides, the depth of the well, either N-well or P-well should be kept at less than about 2 um.
x=h/tan(2*Φ−90°)=−h/cot(2*Φ), (Eq. 8)
An average scatter distance x is when the ion hits the surface half way:
X=−H/(2*cot(2*Φ), (Eq. 9)
If H=1 um, Φ=60°, then x=sqrt(3)/2*H=0.86 um.
However, in practical application, IC layouts are carried out with design rules that contain numerical limits instead of equations for various dimensions. Therefore, a simpler, design rule type of well proximity effect rule is more desirable.
d1(d3)>=3*d0 (Eq. 10)
d2(d4)>=9*d0 (Eq. 1)
When a device layout follows the design rule defined by Eq. 10 and 11, the well proximity effect can largely be ignored.
Referring to
d5>=18*d0 (Eq. 12)
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.