Patent Application
20250113557
Not applicable.
The present disclosure relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of forming semiconductor devices.
Silicon Carbide (SiC) semiconductor devices, such as SiC MOSFETs, have several advantageous features in comparison to traditional silicon-based devices. For example, SiC MOSFETs are better suited for certain high-power applications because SiC MOSFETs are capable of handling high voltages and high operating temperatures. Further, SiC MOSFETs have a low drain-to-source on-resistance (RDSON), (when designed with a short channel region) and fast switching with low power losses, resulting in highly efficient operation. The short channel region design requirement is necessary because SiC MOSFETs have relatively low channel mobility compared to silicon-based devices.
Some progress has been made in improving the performance of SiC MOSFETs by, for example, shrinking the cell pitch to improve on-resistance, by using trench gate structures to improve channel mobility, and by using charge-balance or super-junction (SJ) structures to reduce drift region resistance. However, implementing these techniques has been a challenge because of trade-offs with other performance characteristics that are adversely affected, such as breakdown voltage (BVDSS).
Accordingly, structures and methods are needed that, among other things, facilitate the use of the techniques described above without impacting other performance characteristics, such a breakdown voltage. It would be beneficial for such structures and methods to be cost effective and readily manufacturable.
The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the particular examples disclosed. In the following discussion, the terms “example” and “e.g.” are non-limiting.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description.
For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, trenches, or contacts may be illustrated as having generally straight-line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles.
Although the semiconductor devices are explained herein as certain N-type conductivity regions and certain P-type conductivity regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description, considering any necessary polarity reversal of voltages, inversion of transistor type and/or current direction, etc.
In addition, the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used herein, “current-carrying electrode” means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a “control electrode” means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor.
The term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.
The terms “comprises”, “comprising”, “includes”, “including”, “has”, “have” and/or “having” when used in this description, are open ended terms that specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.
The term “or” means any one or more of the items in the list joined by “or”. As an example, “x or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.
Although the terms “first”, “second”, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure.
It will be appreciated by one skilled in the art that words, “during”, “while”, and “when” as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term “while” means a certain action occurs at least within some portion of a duration of the initiating action.
The use of word “about”, “approximately”, or “substantially” means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated.
Unless specified otherwise, as used herein, the word “over” or “on” includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact.
Unless specified otherwise, as used herein, the word “overlapping” includes orientations, placements, or relations where the specified elements can at least partly or wholly coincide or align in the same or different planes.
It is further understood that the examples illustrated and described hereinafter suitably may have examples and/or may be practiced in the absence of any element that is not specifically disclosed herein.
In general, the present examples relate to semiconductor device structures and methods of making semiconductor devices, such as SiC MOSFET devices, having improved manufacturability and performance. More particularly, structures and methods are described that use a first charge-balance region and a second charge-balance region, which is over the first charge-balance region. In some examples, the first charge-balance region comprises a first doped region in a first semiconductor region and the second charged-balanced region comprises a second doped region in a second semiconductor region. In some examples, the first semiconductor region and the second semiconductor region comprise a first conductivity type (for example, N-type conductivity), and the first doped region and the second doped region comprise a second conductivity type (for example, P-type conductivity) opposite to the first conductivity type.
The structures can include a trench gate structure within the second semiconductor region with the second doped region interposed between the trench gate structure and the first doped region. In some examples, the second doped region is self-aligned to the trench gate structure. For example, the second doped region can be formed in the second semiconductor region using a spacer structure within or in a trench at an early stage of fabricating the trench gate structure. The spacer structure can provide lateral confinement of the second doped region in the second semiconductor region with respect to the trench gate structure, which applicant found can be used to improve short circuit withstand time (SCWT) by, for example, adding a JFET resistance in series with a channel region of the semiconductor device.
In some examples, the first doped region comprises first elongate stripe doped regions and the second doped region comprises second elongate stripe doped regions that is orthogonally oriented to the first elongate stripe doped regions in a top view. Applicant found that this non-parallel orientation improves breakdown voltage performance by reducing sensitivity to misalignment between the second doped region and the first doped region during manufacturing.
In some examples, a third doped region of the first conductivity type (for example, N-type conductivity) can be provided proximate to where the second elongate stripe doped regions intersect or overlaps the first elongate stripe doped regions in the top view to provide further breakdown voltage performance improvement or reduce specific on-resistance. In some examples, the first doped region and the second doped region are coupled to a source potential. The structures and methods provide, among other things, semiconductor devices that support smaller feature sizes, such as reduced cell pitches, and that are more manufacturable and reliable compared to previous device structures and methods.
In an example, a semiconductor device includes a body of semiconductor material including a substrate, a first semiconductor region of a first conductivity type over the substrate and a second semiconductor region of the first conductivity type over the first semiconductor region. In some examples, the second semiconductor region provides a first side of the body of semiconductor and the substrate provides a second side of the body of semiconductor material opposite to the first side. A trench gate structure includes a trench extending into the second semiconductor region from the first side, a gate conductor in the trench, and a gate dielectric separating the gate conductor from the second semiconductor region. A first elongate stripe doped region of a second conductivity type opposite to the first conductivity type is in the first semiconductor region, wherein the first elongate stripe doped region and the first semiconductor region provide a first charge-balance region. A second elongate stripe doped region of the second conductivity type is in the second semiconductor region and interposed between the trench gate structure and the first elongate stripe doped region, wherein the second elongate stripe doped region and the second semiconductor region provide a second a second charge-balance region. The second elongate stripe doped region is orthogonal to the first elongate stripe doped region in a top view.
In an example, a semiconductor device includes a substrate, a first semiconductor region comprising a first conductivity type over the substrate, and a second semiconductor region of the first conductivity type over the first semiconductor region. In some examples, the second semiconductor region provides a first side of the body of semiconductor and the substrate provides a second side of the body of semiconductor material opposite to the first side. A trench gate structure includes a trench extending into the semiconductor region from the first side, a gate conductor within the trench, and a gate dielectric separating the gate conductor from the second semiconductor region. A first doped region of a second conductivity type opposite to the first conductivity type is within the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region. A second doped region of the second conductivity type is within the second semiconductor region and interposed between the trench gate structure and the first doped region, wherein the second doped region and the second semiconductor region provide a second charge-balance region. The second doped region is self-aligned with the trench gate structure.
In an example, a method for manufacturing a semiconductor device includes providing a substrate, providing a first semiconductor region over the substrate and comprising a first conductivity type, and providing a first doped region of a second conductivity type opposite to the first conductivity type in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region. The method includes providing a second semiconductor region over the first semiconductor region and comprising the first conductivity type. The method includes providing a trench extending into the second semiconductor region, the trench comprising side walls and a lower side and providing a spacer structure along the side walls of the trench. The method includes using the spacer structure to provide a second doped region of the second conductivity type in the second semiconductor region and interposed between the lower side of the trench and the first doped region, wherein the second doped region and the second semiconductor region provide a second charge-balance region. The method includes providing a gate dielectric along the side walls and the lower side of the trench and providing a gate conductor within the trench, wherein the gate dielectric isolates the gate conductor from the second semiconductor region and the second doped region.
Other examples are included in the present disclosure. Such examples may be found in the figures, in the claims, or in the description of the present disclosure.
In an example where semiconductor device 10 comprises a 650 volt rated SiC MOSFET, substrate 12 can be a SiC substrate, can have a first conductivity type (for example, N-type conductivity), and can have a dopant concentration of about 5.0×1018 atoms/cm3. In the 650 volt example, first semiconductor region 14A can comprise SiC, can have the first conductivity type (for example, N-type conductivity), a dopant concentration in a range from about 5.01016 atoms/cm3 and 5.0×1017 atoms/cm3, and can have thickness in a range from about 0.5 microns to about 3.0 microns. In the 650 volt example, second semiconductor region 14B can comprise SiC, can have the first conductivity type (for example, N-type conductivity), can have a dopant concentration in a range from about 5.0×1016 atoms/cm3 and 5.0×1017 atoms/cm3, and can have a thickness in a range from about 1.0 microns to about 3.0 microns. The thicknesses, dopant concentrations, or dopant profiles of first semiconductor region 14A and second semiconductor region 14B can be adjusted in accordance with desired breakdown voltage characteristics for semiconductor device 10.
In the present example, second semiconductor region 14B provides a top side 18 of body of semiconductor material 11 and substrate 12 provides a bottom side 19 of body of semiconductor material 11. In the present example, bottom side 19 is opposite to top side 18. Top side 18 can also be referred to as a first side of body of semiconductor material 11 and bottom side 19 can also be referred to as a second side of body of semiconductor material 11.
A first doped region 22 is within or in first semiconductor region 14A. In the present example, first doped region 22 comprises a second conductivity type (for example, P-type conductivity) opposite to the first conductivity type. In accordance with the present example, first doped region 22 and first semiconductor region 14A form, provide, or are configured as a first charge-balance region 142 for semiconductor device 10. First charge-balance region 142 can also be referred to as a lower charge-balance region, a lower charge-balance structure, a first charge-balancing region, a first super-junction structure, or a lower super-junction structure. In some examples, first doped region 22 comprises a dopant concentration in a range from about 5.0×1016 atoms/cm3 to about 5.0×1017 atoms/cm3. In some examples, first doped region 22 extends to depth within first semiconductor region 14A in a range from about 0.5 microns to about 3.0 microns. In some examples, first doped region 22 terminates within first semiconductor region 14A without reaching substrate 12.
In some examples and with temporary reference to
A second doped region 23 is within or in second semiconductor region 14B. In some examples, second doped region 23 is coupled electrically and physically to first doped region 22. In some examples, second doped region 23 can partially extend into an upper part of first doped region 22. In the present example, second doped region 23 comprises the second conductivity type (for example, P-type conductivity). In accordance with the present example, second doped region 23 and second semiconductor region 14B form, provide, or are configured as a second charge-balance region 143. Second charge-balance region 143 also can be referred to as an upper charge-balance region, an upper charge-balance structure, a second charge-balancing region, a second super-junction, or an upper super-junction structure. In some examples, second doped region 23 comprises a dopant concentration in a range from about 5.0×1016 atoms/cm3 to about 5.0×1017 atoms/cm3.
In some examples and with temporary reference to
In some examples, semiconductor device 10 comprises a trench gate structure 280 within or in second semiconductor region 14B. In the present example, second doped region 23 is interposed between trench gate structure 280 and first doped region 22. Trench gate structure 280 includes a trench 21 extending inward from top side 18 into second semiconductor region 14B. A gate dielectric 26 is over side walls and a lower side of trench 21, and a conductor 28 is over gate dielectric 26 within or in trench 21. Gate dielectric 26 insulates or electrically separates conductor 28 from second semiconductor region 14B. Conductor 28 can also be referred to as a gate conductor, a gate electrode, or a control electrode. In some examples, conductor 28 can comprise doped polysilicon or other conductive materials.
In some examples, gate dielectric 26 comprises a first portion 26A along the side walls of trench 21 and a second portion 26B at the lower side of trench 21. In some examples, gate dielectric 26 can comprise an oxide or a nitride and can have a thickness in a range from about 200 Angstroms to about 1000 Angstroms. In some examples, the gate dielectric can contain any of the following materials: Hf, Al, La, O, N, Si, P, Bi, B, Li. In some examples, first portion 26A comprises a first thickness and second portion 26B comprises a second thickness that is greater than the first thickness. In some examples, this configuration of gate dielectric 26 reduces switching losses. In some examples, the second thickness can be about 1.2× to about 10× greater than the first thickness.
In accordance with the present description, second doped region 23 is self-aligned to trench gate structure 280. In some examples (as will be explained in more detailed later), a spacer structure can be used to form second doped region 23 through the lower side of trench 21 to self-align doped region 23 to trench gate structure 280. In addition, the spacer structure can be used to laterally confine second doped region 23 with respect to trench gate structure 280.
Semiconductor device 10 comprises a doped region or regions 31 of the second conductivity type (for example, P-type conductivity) within second semiconductor region 14B adjacent to trench gate structure 280. In some examples, doped region 31 is a single interconnected doped region, such as a plurality of interconnected stripe portions. In other examples, doped region 31 can be a plurality of separate doped regions, such as separate cell or stripe cell regions. In some examples, doped region 31 extends into second semiconductor region 14B to a depth in a range from about 0.2 microns and about 1.0 microns. Doped region 31 provides a body region or base region for semiconductor device 10.
Semiconductor device 10 further comprises a doped region 33 comprising the first conductivity type (for example, N-type conductivity) and a doped region 36 comprising the second conductivity type (for example, P-type conductivity) type within or in doped region 31. In some examples, doped region 33 provides a source region for semiconductor device 10. Doped region 33 can also be referred to as a current carrying region. Doped region 36 provides enhanced contact to doped region 31 and can reduce certain parasitic effects.
Semiconductor device further comprises a dielectric 41 overlying top side 18 and trench gate structure 280. In some examples, dielectric 41 comprises one or more dielectric or insulative layers and can be configured as an inter-layer dielectric (ILD) structure. In some examples, dielectric 41 can comprise a silicon oxide, such as a doped or undoped deposited silicon oxide. In some examples, dielectric 41 can comprise a layer of deposited silicon oxide doped with phosphorous or boron and phosphorous and at least one layer of undoped oxide. In some examples, dielectric 41 can have a thickness from about 0.4 microns to about 1.0 microns. Dielectric 41 can be planarized to provide a more uniform surface topography, which improves manufacturability.
Semiconductor device 10 comprises a conductor 44 over portions of top side 18 coupled to doped region 33 and doped region 36. In some examples, conductor 44 is coupled to first doped region 22 and second doped region 23 in another location on semiconductor device 10. In some examples, conductor 44 can comprise nickel, nickel silicide, titanium, or other conductive materials. In some examples, a conductor 46 is provided over bottom side 19 of body of semiconductor material 11 and is coupled to substrate 12. In some examples, conductor 46 can comprise a plurality of metal layers, such as nickel-titanium-nickel-silver, chrome-nickel-gold, or other conductive materials. Conductors 44 and 46 can be formed using deposition processes, such as evaporation, sputtering, or other techniques as known to one of ordinary skill in the art. In some examples, conductor 44 can be referred to a current carrying electrode or a source electrode and conductor 46 can be referred to as a current carrying electrode or a drain electrode. With an appropriate gate voltage applied to conductor 28 a channel region 45 is formed in doped region 31 proximate to top side 18 that allows for current to flow in semiconductor device 10.
In one example, the operation of semiconductor device 10 proceeds as follows. With conductor 44 and doped regions 33 receiving a source potential VS of zero volts, conductor 28 receiving a control voltage VG of 10 volts, which is greater than the threshold voltage of semiconductor device 10, and conductor 46 receiving a drain potential VD of 0.5 volts, channel regions 45 form in doped region 31. Channel regions 45 electrically connect source regions to second semiconductor region 14B and a device current IS flows from conductor 44, through channels 45, second semiconductor region 14B, first semiconductor region 14A to conductor 46. The high dopant concentration of first semiconductor region 14A and second semiconductor region 14B provide a low on-resistance for semiconductor device 10. In some examples, device current IS can be 500 amperes.
To switch semiconductor device 10 to an off state, the control voltage VG that is less than the threshold voltage of semiconductor device 10 is applied to gate conductor 28 (for example, less than 2.0 volts). This removes channels 45 and device current no longer flows through semiconductor device 10. In the off state, first semiconductor region 14A (N-type conductivity) and first doped region 22 (P-type conductivity) and second semiconductor region 14B (N-type conductivity) and second doped region 23 (P-type conductivity) compensate each other as a depletion region from a PN junction formed between doped region 31 and second semiconductor region 14B spreads. This charge-balancing effect enhances the breakdown voltage (BVDSS) of semiconductor device 10.
Experimental results for semiconductor device 10 rated as a 650 volt device in the on-state show a threshold voltage of about 3.1 volts, an on-resistance at a VGS of 18 volts, room temperature of 0.45 milli-ohm·cm2, and an on-resistance at a VGS of 18 volts at, 175 degrees Celsius of 0.77 mill-ohm·cm2. The experimental results for this semiconductor device 10 showed a breakdown voltage of 785 volts. Example figures of merit (FOM) included an RON*Qg of 715 milli-ohm·nC, an RON*QOSS of 985 milli-ohm·nC, and an Ron*EOSS of 90 milli-ohm·C. In addition, semiconductor device 10 in accordance with the present description was found to have an electric field across gate dielectric 26 (EOX) of less than 3.0 MV/cm at a VDS of approximately 600 volts and a VGS of 0 volts.
In some examples, a doped region 221 is provided to couple first elongate stripe doped regions 220 together. Doped region 221 comprises the same conductivity type as doped region 22 (for example, P-type conductivity) and comprises a dopant concentration sufficient to provide electrical contact to first elongate stripe doped regions 220. In some examples, doped region 221 can comprise an elongate stripe doped region that orthogonal to first elongate stripe doped regions 220. Doped region 221 can also be referred to as a contact region, a coupling region, a pillar, or a sinker region.
In some examples, semiconductor device 10 comprises doped region 222 within or in doped region 221. Doped region 222 comprises the same conductivity type (for example, P-type conductivity) as doped region 221 and can have a higher dopant concentration than doped region 221. Doped region 222 can be referred to as an enhancement region or a contact region and is configured to provide low contact resistance to, for example, conductor 44. In some examples, doped region 222 can comprise an elongate stripe dope region.
Doped region 221 can be placed in various locations on semiconductor device 10 between adjacent trench gate structures 280. In some examples, doped regions 221 can be interposed between adjacent trench gate structures 280.
In some examples, first semiconductor region 14A is provided over substrate 12. In some examples, first semiconductor region 14A comprises a SiC epitaxial region comprising N-type conductivity formed using epitaxial growth process techniques with phosphorous or nitrogen doping. In some examples, first semiconductor region 14A comprises a dopant concentration a range from about 5.0×1016 atoms/cm3 and 5.0×1017 atoms/cm3 and can have thickness in a range from about 0.5 microns to about 3.0 microns.
In some examples, masking and doping process techniques can be used to provide first doped region 22 within or in selected portions of first semiconductor region 14A. In some examples, ion implantation and dopant redistribution processes can be used to form doped region 22. In some examples, ion implantation is used with an aluminum dopant source, an ion implantation dose in a range from about 2.0×1012 atoms/cm2 to 5.0×1013 atoms/cm2, and ion implantation energy in a range from about 50 keV to about 3.0 MeV. In some examples, multiple ion implants can be used with different doses or different energies. Thermal processing can then be used to redistribute and activate the implanted dopant to provide first doped region 22. In some examples, first doped region 22 can have a peak dopant concentration of about 1.0×1014 atoms/cm3. First semiconductor region 14A and first doped region 22 are configured as first charge-balance region 142.
Doped region 31 can then be provided within or in second semiconductor region 14B. In some examples, doped region 31 can be formed using ion implantation. In some examples, an aluminum dopant source can be used with one or more ion implant doses in a range from about 2.0×1013 atoms/cm2 to about 6.0×1014 atoms/cm2 and an ion implant energy in a range from about 150 keV to about 400 keV. Doped region 33 can then be provided within or in doped region 31. In some examples, doped region 33 can be formed using ion implantation with a phosphorous or nitrogen dopant source. In some examples, doped region 33 can have a peak dopant concentration greater than about 3.0×1019 atoms/cm3.
In accordance with the present description, a spacer 63 is provided along the side walls of trench 21. In some examples, spacer 63 comprises a dielectric, such as an oxide or a nitride, which can be provided using chemical vapor deposition (CVD) techniques. In a first step, the dielectric can be deposited over top side 18, the side walls of trench 21, and the lower side of trench 21. An anisotropic etch can then be used to remove the dielectric from the lower side of trench 21 to provide an opening 64. Spacer 63 comprises a thickness 63A that is pre-selected to place doped region 23 inset a lateral distance 231 (shown in
In subsequent steps and with reference back to
In further steps, conductor 44 can be provided over top side 18 and coupled to doped region 33, doped region 36, and doped region 31. In some examples, first doped region 22 and second doped region 23 are coupled to conductor 44 through doped regions 221 and 222 at another location within semiconductor device 10 as illustrated in
In some examples, conductor 44 can comprise nickel, nickel silicide, titanium, or other conductive materials as known to one of ordinary skill in the art. In some examples, a conductor 46 is provided over bottom side 19 of body of semiconductor material 11 and is coupled to substrate 12. In some examples, conductor 46 can comprise a plurality of metal layers, such as nickel-titanium-nickel-silver, chrome-nickel-gold, or other conductive materials as known to one of ordinary skill in the art. Conductors 44 and 46 can be formed using deposition processes, such as evaporation, sputtering, or other techniques as known to one of ordinary skill in the art.
In summary, structures and methods have been described for a semiconductor device having improved manufacturability and performance. More particularly, a structure has been described that uses a first charge-balance structure including a first doped region and a second charge-balance structure including a second doped region. In some examples, the second doped region is provided self-aligned to a trench gate structure. In some examples, the second doped region is laterally inset from side walls of or laterally confided with respect to the trench gate structure. The configuration was found to improve short circuit withstand time (SCWT) by, for example, adding a JFET resistance in series with a channel region of the semiconductor device.
In some examples, the first doped region is provided as first elongate stripe doped regions and the second doped region is provided as second elongate stripe doped regions that are non-parallel to the first elongate stripe doped regions. In some examples, the second elongate stripe doped regions are orthogonal to the first elongate stripe doped regions. Applicant found that this non-parallel orientation improves the breakdown voltage performance of the semiconductor device by reducing sensitivity to misalignment between the second doped region and the first doped region during manufacturing.
In some examples, a third doped region can be provided proximate to where the second elongate stripe doped regions intersect or overlaps the first elongate stripe doped regions in the top view to provide further breakdown voltage performance improvement or to reduce specific on-resistance.
It is understood that the different examples described herein can be combined with any of the other examples described herein to obtain different embodiments.
While the subject matter of the invention is described with specific preferred examples, the foregoing drawings and descriptions thereof depict only typical examples of the subject matter and are not therefore to be considered limiting of its scope. It is evident that many alternatives and variations will be apparent to those skilled in the art. For example, the conductivity types of the various regions can be reversed.
As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed example. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Description, with each claim standing on its own as a separate example of the invention. Furthermore, while some examples described herein include some, but not other features included in other examples, combinations of features of different examples are meant to be within the scope of the invention and meant to form different examples as would be understood by those skilled in the art.
