Patent Application
20180286621
This disclosure relates to vacuum field effect transistors, more particularly to semiconductor-free vacuum field effect transistors.
Moore's law refers to a statement credited to Intel co-founder Gordon Moore in which he observed that the number of transistors per square inch on integrated circuits has doubled every year since their invention. The use of full three-dimensional integration may allow extension of this relationship. Three-dimensional (3D) integration typically involves stacking of semiconductor devices or dies and connecting them vertically through vias.
Current approaches typically involve many layers of heteroepitaxial growth of semiconductors. However, this generally results in rapidly deteriorating quality. Growing multiple heteroepitaxial semiconductor layers often results in semiconductor defects due to poor growth. Other approaches include laser recrystallization and amorphous silicon layers and have suffered from the same issues. In addition, the devices also suffer from poor heat extraction, causing further failures. Each of these issues has limited the number of layers to just a few.
To develop better 3D integration, one can use vacuum field effect transistors (vFET). Field emission devices normally require a hard vacuum for operation. However, if the distance between emitter and collector are smaller than the electron mean free path in air or other gases, a device can operate in such an ambient as if it were a vacuum. Typically, vFETs that operate in air or controlled gases use a fabrication process relying on semiconductors and use a planar electronics configuration. This would affect their manufacturability when applied to 3D monolithic integration. It is possible to replace the semiconductor channels of transistors with semiconductor-free vacuum field-effect transistors (vFETs) and use refractory metal or semimetal layers and insulators to remove these problems.
A first embodiment consists of a vacuum field-emission-transistor device having a drain comprised of either a metal or a semimetal material, a gate arranged adjacent to, but separated from, the drain, a source comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate, and a void through the metal drain and the metal gate to expose the drain, wherein the distance between the drain and the source is shorter than a mean free path distance of electrons in air.
A second embodiment consists of a device having a first planar array of vacuum field-effect transistors, where in each transistor has a drain formed from regions of metal or semimetal on a first dielectric film, a gate formed on a second dielectric film arranged on the first dielectric film, a source from regions of metal or semimetal on a third dielectric film arranged on the second dielectric film, and a void formed through the second and third dielectric films to expose the drain and form a channel between the source and the drain; a second planar array of vacuum field effect transistors arranged in a vertical stack with the first planar array of vacuum field effect transistors, and an interposer film between the first and second arrays of planar transistors.
Another embodiment consists of a method of manufacturing a vacuum field-effect transistor. The method forms a first metal layer on an insulating substrate, patterning the first metal layer to form drains, depositing a first dielectric layer on the drains, depositing a second metal layer on the first dielectric layer, patterning the second metal layer to form gates, depositing a second dielectric on the gates, depositing a third metal layer on the second dielectric, patterning the third metal layer to form sources such that the sources are arranged to form a stack with the drains and gates, and etching holes through the sources and the gates to expose the drains to form a first planar array of vacuum field-effect transistors.
This discussion relates to vacuum field-effect transistors, or vFETs. A field-effect transistor, as used here, consists of a device having a semiconductor-free channel to carry current. A gate electric field controls the electron emission from the source electrode and thus the current in the channel that flows from the source electrode to the drain electrode. In vacuum tube terminology, the term source is analogous to a cathode, and the term drain is analogous to an anode. Since the below discussion involves FETs, the terms source and drain will be used.
A ‘vacuum’ FET employs some of the principles of vacuum tube technology, in which a vacuum replaces the semiconductor channel. The term ‘vacuum’ is somewhat of a misnomer, as the channel can be formed in ambient air because the operating voltage is less than the ionization voltage of air. Almost no ions are created and attracted to electrodes, and for short source-drain gaps, less than 100 nanometers, the mean free paths of electrons in air is longer than the gap. The result is that few collisions, elastic or inelastic, occur.
One possible architecture for vFETs has a lateral layout, with the source and drain arranged laterally to each other and the channel between them. However, difficulties arise in controllably fabricating the short gaps and small radius features, making the lateral vFET undesirable. It is possible to have a vertical architecture, and some of these have been created, but they generally consist of semiconductor materials. As mentioned previously, semiconductor materials can have defects due to poor growth and suffer from poor heat extraction.
The embodiments here consist of vertical vFETs using only metals or semimetals and dielectrics with no semiconductor compounds. The term ‘semimetal’ is used here interchangeably with ‘metalloids’ rather than compounds of a metal and a non-metal, which may also be referred to as semimetals. The compounds defined here as semimetals include the more commonly recognized semimetals including boron, silicon, germanium, arsenic, antimony, and tellurium; as well as carbon, aluminum, selenium, polonium, and astatine.
Some of the embodiments include vertically stacked layers of vertical vFETs. The below figures show devices using metals or semimetals layers such as graphene, copper, and/or aluminum, as examples. Aluminum has a lower melting temperature, but its native oxide may assist in forming the thin dielectric layers, discussed below. The insulator layers could be silicon dioxide or graphene oxide or any other thin, preferably high temperature, high breakdown field, low defect dielectrics. For purposes of this discussion, a high temperature dielectric includes any dielectric with melting temperature greater than 600 C. The gate enhances or diminishes field emission from the source by lowering or raising the tunnel barrier and by accumulating or depleting the 2d electron or hole gas in the source (cathode) near the source/vacuum edge of the pit, also referred to as a void. Opposite charges may accumulate away from the pit or void. Space charge, which tends to screen the source-drain field, limits the source/drain (or cathode/anode) current.
The channel forms between the source 22 to the drain 14 through a void 24. By controlling the distance between the source and the drain, the device can use the ‘vacuum’ to transport the electron flow. The source-gate separation should generally be less than half the gate-drain separation. The gate controls the field that in turn controls the emission.
The manufacturing process etches holes through the sheet at the centers of the gate regions and the gate metal is oxidized or otherwise reacted to form a thin insulating barrier. An added feature of the hole formation through just the source and gate, stopping at the drain is that the drain has a much larger area than the peripheral areas of the source. One can raise the space charge limitation on the source-drain current substantially.
One can modify the work function of the electrodes to enhance emission. A chemical or physical coating can accomplish this. The low voltages of the nano-scale devices should lead to greatly reduced damage and enhanced lifetimes of the coatings relative to ordinary field emission devices. One should note that the vertical dimensions are the only dimensions that must have nano-scale and uniformity. The lateral features may have macroscopic lateral feature sizes.
In another instantiation a roll to roll process is used to fabricate the layers and build up the 3d structure.
Many variations on these processes are possible, the below discussion is merely one example of such a process. In this embodiment, three rolls of dielectric merge into a final composite film. A roller 122 directs a first roll 120 of dielectric under a print head 124 that solution prints the metal or semimetal regions 126 on the dielectric to form the source regions. Once printed, the source film may be then covered by a dielectric film 128 from a directional roller 130. These two films then merge at the nip between rollers 132 and 134. The dielectric under the drain contact regions may become part of the gate dielectric.
A second dielectric film 140 from roller 142 also receives printed metal or semimetal regions 146 from print head 144 that will eventually form the gate regions. As will be discussed in more detail regarding the composite film 184, the second print head 148 may deposit a material that can be etched to form the pits on the gate film 140. The patterned film then eventually merges with the film from 132/134 at the roller 180 and 182.
A third film 160, off roller 162, receives patterned metal or semimetal regions such as 166 from the print head 164 to form the drain regions. A covering film such as 168 may cover the patterned region and merge from roller 170. These films are merged at the nip between rollers 174 and 172. As mentioned above, all three of these films then merge at the nip between rollers 180 and 182. The resulting composite film 184 may then be treated to etch the extra material laid down as part of the gate region printing to form the voids.
In another embodiment, the drain film 160 and the gate film 140 may be merged prior to the addition of the source film 120, with the etching or material removal over the gate region occurring prior to the addition of the source film. Alternatively, the holes could be formed in the gate film prior to the merging of the films.
In this manner, a three-dimensional array of metal or semimetal vFETS can be provided having much better manufacturability and no defects from poor semiconductor heteroepitaxial growth, as there are no semiconductors involved that undergo heteroepitaxial growth.
It will be appreciated that variants of the above-disclosed and other features and functions, or alternatives thereof, may be combined into many other different systems or applications. Various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.
