The invention relates to a semiconductor fuse structure comprising a substrate having a surface, the substrate having a field oxide region at the surface, the fuse structure further comprising a fuse body, the fuse body comprising polysilicon, the fuse body lying over the field oxide region and extending into a current-flow direction, wherein the fuse structure is programmable by means of leading a current through the fuse body.
The invention also relates to an integrated circuit comprising such a semiconductor fuse structure.
The invention further relates to methods of manufacturing a semiconductor fuse structure.
Fuses for semiconductors have a wide range of applications such as die-ID, redundancy in memories, encryption, etc. Polysilicon fuses are rapidly replacing laser fuses, because they can be programmed electrically, which reduces programming costs and increases flexibility. Polysilicon fuses are currently being replaced by silicided polysilicon fuses for reducing their non-programmed resistance. These silicided polysilicon fuses are fabricated using standard CMOS processes. A large resistance after programming is desirable for easy state-detection, while fast programming is essential for short test and repair times. Furthermore, it is desirable that the programming voltage polysilicon fuses is as low as possible, so that no special measures are necessary to integrate these fuses into an integrated circuit. In general, the programming time increases when the programming voltage is reduced.
A drawback of the known polysilicon fuses is that their programming voltage is still relatively high.
It is an object of the invention to provide a semiconductor fuse structure which has a lower programming voltage while still maintaining the same programming time, or which has a shorter programming time while maintaining the same programming voltage.
The invention is defined by the independent claims. The dependent claims define advantageous embodiments.
The object of the invention is realized in that the fuse body has a tensile strain in the current-flow direction and a compressive strain in a direction perpendicular to said surface of the substrate. Because of the tensile strain in the current-flow direction and the compressive strain in the direction perpendicular to the surface of the substrate the electron mobility increases. The increased electron mobility leads to an increased electromigration, which in its turn leads to faster breakdown of the fuse. The faster breakdown of the fuse can then be exploited to reduce the programming voltage. Alternatively, when the programming voltage is kept the same, the programming time is reduced.
The semiconductor device according to the invention provides an additional advantage. Process-induced strain techniques are nowadays being explored to enhance carrier mobility in MOSFET devices and thus boost device performance. Thus the implementation of process-induced strain techniques in polysilicon fuses is very likely to be compatible with the future CMOS processes.
In an advantageous embodiment of the fuse structure according to the invention the fuse body comprises a first sublayer and a second sublayer, the first sublayer comprising polysilicon, the first sublayer lying over the field oxide region, the second sublayer comprising a silicide, the second sublayer lying over the first sublayer. This fuse structure has a dual-layer structure and is advantageous because of its lower resistance (because of the low-resistive silicide) before programming, which reduces the required programming voltage.
In another embodiment of the fuse structure according to the invention a tensile-strain layer at least covers both the fuse body and part of the substrate, so as to form the compressive strain in the fuse body in the direction perpendicular to said surface. The presence of this strain layer ensures that the strain in the fuse body is maintained better. Furthermore, during manufacturing of the fuse structure the strain layer can be used as a contact etch stop layer (CESL).
The invention also relates to an integrated circuit comprising such a semiconductor fuse structure. Scaling of CMOS processes also means reducing supply voltage and reducing I/O-voltages. The lower programming voltage of the fuse structure according to the invention thus provides better integration possibilities into future CMOS processes. Thus, an integrated circuit manufactured in these processes can greatly benefit from the reduced programming voltage of the fuse structure. A lower programming voltage reduces the need for special measures which make it possible to program the fuse structure (like the introduction of special high-voltage transistors) and thus the complexity of the integrated circuit is reduced.
The invention further relates to a method of manufacturing a semiconductor fuse structure. A first method according to the invention comprises the following steps of:
providing a substrate having a surface, the substrate comprising a field oxide region at the surface;
providing a first layer comprising polysilicon at least on the field oxide region;
patterning the first layer for at least forming a fuse body on the field oxide region, the fuse body extending into a current-flow direction;
performing an amorphization implant on the first layer for converting the polysilicon of at least the fuse body into amorphous silicon;
covering the substrate and the fuse body with a strain layer, wherein the strain layer is a low strain or tensile strain layer which results in a compressive strain in the fuse body in a direction perpendicular to the surface and which further results in a tensile strain in the fuse body in the current-flow direction;
performing a spike-anneal such that the amorphous silicon in the fuse body is recrystallised into polysilicon with preservation of at least part of its strain; and
providing spacers on both sidewalls of the fuse body.
The method of manufacturing according to the invention provides a convenient way of forming a semiconductor fuse structure according to the invention. A layer with a low strain is typically in the −200 to 200 MPa range. It may then be a low tensile strain or a low compressive strain. A low strain layer is also suitable as any nitride layer becomes tensile strained upon annealing. Thus, a low strain layer will turn into a tensile strain layer during the thermal budget of subsequent CMOS process steps. The technique of amorphization, followed by straining and recrystallisation with preservation of strain, is also called a “Stress Memorization Technique”.
One embodiment of the method according to the invention is characterized in that the strain layer is removed prior to the step of providing spacers. This step makes it possible to form the spacers in a more conventional way.
In an advantageous variant of the method according to the invention the method comprises a step of forming a silicide on the fuse body before the step of covering the substrate and the fuse body with a strain layer or after removal of the strain layer. This variant is advantageous, because the resulting fuse structure is a dual-layer structure and is advantageous because of its lower resistance (because of the low-resistive silicide) before programming, which reduces the required programming voltage.
A second method according to the invention comprises the following steps of:
providing a substrate having a surface, the substrate comprising a field oxide region at the surface;
providing a first layer comprising polysilicon at least in the field oxide region;
patterning the first layer for at least forming a fuse body in the field oxide region, the fuse body extending into a current-flow direction;
providing spacers on both sidewalls of the fuse body; and
covering the substrate, the fuse body and the spacers with a strain layer, wherein the strain layer is a tensile strain layer which results in a compressive strain in the fuse body in a direction perpendicular to the surface and which further results in a tensile strain in the fuse body in the current-flow direction.
This method of manufacturing according to the invention provides an alternative way of forming a semiconductor fuse structure according to the invention. The advantage of the second method is that it is less complex (it requires fewer process steps).
Preferably, the method comprises a step of forming a silicide on the fuse body, prior to the step of covering the substrate, the fuse body and the spacers with the strain layer. This variant of the method is advantageous, because the resulting fuse structure is a dual-layer structure and is advantageous because of its lower resistance (because of the low-resistive silicide) before programming, which reduces the required programming voltage.
Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art. Numerous variations and modifications can be made without departing from the scope of the claims of the present invention. Therefore, it should be clearly understood that the present description is illustrative only and is not intended to limit the scope of the present invention.
How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which:
a-1i illustrate different stages of a first method of manufacturing a fuse structure according to the invention;
a-2f illustrate different stages of a second method of manufacturing the fuse structure according to the invention;
Referring to
In another stage of the first method (
In a further stage of the first method (
In a further stage of the first method (
In another stage of the first method (
In a further stage of the first method (
In a later stage of the first method (
In a further stage of the first method (
Alternative to the steps in
Yet in another stage of the first method (
The technique illustrated in
Referring to
d refers to a further stage of the second method. In that stage spacers 9 are formed on sidewalls of the fuse body similar to the first method. In yet a further stage of the second method (
Referring to
Referring to
Fusing is well known by the person skilled in the art. Various publications on this matter exist. During the programming of a semiconductor polysilicon fuse the resistance increases from a first low level to a second higher level. This difference in resistance can be detected such that for example a programmable memory can be made. The physical phenomena, which occur during heavy programming, depend on various conditions. A recent publication, which explains the fusing mechanisms the best, is T. S. Doom, M. Altheimer, “Ultra-fast programming of silicided polysilicon fuses based on new insights in the programming physics”, IEDM Techn. Digest, pp. 667-670, 2005.
This invention improves upon the known fuse structures because it enhances the electron mobility in the fuse body by means of strain. Because of this measure the fuse will either be programmed faster at the same programming voltage, or be programmed at a lower programming voltage in the same programming time.
The invention thus provides an attractive semiconductor fuse structure having a better performance than the known fuse structures.
The invention also provides methods of manufacturing such fuse structures.
Throughout the specification the use of polysilicon material in the fuse body has been mentioned. However, the skilled person may be able to find alternative materials later on, which are also suitable for semiconductor fuse structures. Therefore, these kind of variations have to be regarded as equivalents to polysilicon and do not depart from the scope of the invention which is defined by the claims.
The present invention has been described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. Any reference signs in the claims shall not be construed as limiting the scope. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. “a” or “an”, “the”, this includes a plural of that noun unless something else is specifically stated.
Furthermore, the terms first, second, third and the like in the description and in the claims, are used to distinguish between similar elements and not necessarily to describe a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Number | Date | Country | Kind |
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06115191.6 | Jun 2006 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB2007/052125 | 6/6/2007 | WO | 00 | 12/5/2008 |