Semiconductor having optimized insulation structure and process for producing the semiconductor

Abstract

A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 illustrates a LOCOS insulation structure of a known type.

FIG. 2 illustrates diagrammatic cross-sectional views during various process stages involved in the production of a semiconductor having an insulation structure according to one embodiment of the invention.

FIG. 3 illustrates various process stages involved in the production of a semiconductor insulation structure in accordance with a further embodiment of the invention.

FIG. 4 illustrates diagrammatic cross-sectional views of semiconductor substrates with current conduction channels in accordance with a further embodiment of the invention.

FIG. 5 illustrates a diagrammatic cross-sectional view of a semiconductor substrate with an insulation structure forming a waveguide region in accordance with a further embodiment of the invention.

FIG. 6 illustrates a diagrammatic view of a semiconductor substrate with strip-like insulation regions in accordance with a further embodiment of the invention.

FIG. 7 illustrates a diagrammatic cross-sectional view of a semiconductor substrate with an insulation structure for guiding the heat flow in accordance with a further embodiment of the invention.

FIG. 8 illustrates a diagrammatic cross-sectional view of a semiconductor substrate with an insulation structure in accordance with a further embodiment of the invention.

Claims

1. A process for producing a semiconductor having an insulation structure comprising: providing a semiconductor substrate;

2. The process according to claim 1, comprising: forming the implantation mask as resist, andremoving the implantation mask following the implantation.

3. The process according to claim 1, comprising wherein the patterned implantation mask has topology stages which form openings and the structural composition of which is maintained in further processes.

4. The process according to claim 1, comprising: selecting oxygen or nitrogen or oxygen and nitrogen as implanted element, and selecting silicon as the semiconductor substrate, in order for the insulation structure to be formed from silicon oxide or silicon nitride or oxynitride; andwherein the distance between adjacent subregions is selected to be less than 500 nm.

5. The process according to claim 1, comprising implanting the elements according to an implantation profile extending as far as the surface of the semiconductor substrate.

6. A process for producing an insulation structure in a semiconductor substrate, comprising: providing the semiconductor substrate;producing and patterning an implantation mask on a surface of the semiconductor substrate;implanting elements into at least one subregion of the semiconductor substrate, the implanted elements being selected in such a manner that on thermal activation they form an insulation region together with further elements of the semiconductor substrate; andforming the insulation structure by irradiating the semiconductor substrate with laser radiation, so that the at least one subregion is melted and then recrystallizes as insulation region.

7. The process according to claim 6, comprising: forming the implantation mask as resist; andremoving the implantation mask following the implantation.

8. The process according to claim 6, comprising wherein the patterned implantation mask has topology stages which form openings and the structural composition of which is maintained in further processes.

9. The process according to claim 6, comprising: selecting oxygen or nitrogen or oxygen and nitrogen as implanted element, and selecting silicon as the semiconductor substrate, in order for the insulation structure to be formed from silicon oxide or silicon nitride or oxynitride.

10. The process according to claim 6, comprising wherein the distance between adjacent subregions is selected to be less than 500 nm.

11. The process according to claim 6, comprising wherein the elements are implanted according to an implantation profile extending as far as the surface of the semiconductor substrate.

12. The process according to claim 11, comprising selecting an implantation energy of less than 100 keV and an implantation dose of greater than 1015 cm−2.

13. The process according to claim 6, comprising implanting the elements according to an implantation profile buried in the semiconductor substrate.

14. The process according to claim 13, selecting an implantation energy of greater than 100 keV and an implantation dose of greater than 1015 cm−2.

15. The process according to claim 6, comprising wherein one type or various types of elements are implanted down to different depths of the semiconductor substrate over a plurality of implantation processes in order to form the implantation structure, the plurality of implantation process being based on a common implantation mask or in each case different implantation masks or partially common implantation masks.

16. A semiconductor having an insulation structure, produced by a process according to claim 11 comprising: at least one insulation region formed at the surface of the semiconductor substrate, the at least one insulation region, relative to the surface of a directly adjacent region of the semiconductor substrate, both extending into and projecting out of the semiconductor substrate; anda flank of the at least one insulation region having a lateral extent of less than 50 nm from the surface of the directly adjacent region to a top side or an underside of the insulation region.

17. A semiconductor having an insulation layer produced by the process of claim 13, comprising: a plurality of buried insulation regions which are spaced apart from one another and are embedded within the semiconductor substrate.

18. The semiconductor according to claim 17, comprising wherein the insulation regions are formed in the semiconductor substrate at a depth of from 100 to 300 nm below the surface.

19. The semiconductor according to claim 17, comprising wherein the surface of the semiconductor substrate is arched and is higher in those surface regions beneath which an insulation region is formed than in the other surface regions.

20. The semiconductor according to claim 17, comprising wherein the insulation regions at least in some cases are at a lateral distance of less than 500 nm from one another.

21. The semiconductor according to claim 17, comprising wherein that insulation regions at least in some cases have lateral dimensions of less than 500 nm parallel to the surface.

22. A semiconductor having an insulation structure produced by a process according to claim 11, comprising: a single insulation region buried at the same depth within the semiconductor substrate.

23. The semiconductor according to claim 22, comprising wherein the insulation region or insulation regions have a thickness of less than 100 nm.

24. The semiconductor according to claim 18, comprising wherein the thickness is less than 50 nm.

25. The semiconductor according to claim 18, comprising wherein the insulation regions are formed as parallel strips, the distance between the strips being in the range from 300 nm to 2 μm and/or the width of the strips being in the range from 300 nm to 2 μm.

26. A semiconductor having an insulated structure produced by a process according to claim 15, comprising wherein that the insulation structure has a plurality of insulation regions, which are formed at different depths of the semiconductor substrate.

27. A process for producing an insulation structure in a semiconductor substrate, comprising: providing the semiconductor substrate;