Claims
- 1. In combination:
- a solid state junction device comprising a plurality of layers of different materials forming a substantially unidirectionally conductive junction at their interface;
- a first of said layers comprising semiconductor material;
- a second of said layers comprising a compound having a bulk resistivity which is substantially greater than the bulk resistivity of said first layer;
- the resistance per unit area through said second layer in a direction normal to said junction being substantially less than the resistance per unit area through said semiconductor layer;
- means for producing a voltage bias across said junction; and
- means for injecting charge carriers into the region of said junction.
- 2. A combination in accordance with claim 1 in which said semiconductor layer comprises silicon and said second layer comprises a metal compound forming a unidirectional junction with said silicon.
- 3. A combination in accordance with claim 1 wherein said means for producing a voltage bias across said junction comprises an evacuated envelope containing an electron source and means for directing electrons from said source toward said plurality of layers.
- 4. A combination in accordance with claim 1 wherein an apertured third layer is positioned between said first and second layers with said second layer contacting said first layer and forming said junctions with said first layer in said apertures.
- 5. A combination in accordance with claim 4 wherein the surface of said first layer on the opposite side of said first layer from said second layer has a bulk resistance substantially lower than the average bulk resistance of said first layer.
- 6. In combination:
- a multilayer body comprising a first layer of semiconductor material and a second layer of material which is different from the material of said first layer supported on said first layer and forming a unidirectionally conductive junction at the interface of said second layer with said first layer;
- means for producing a voltage bias across said junction; and
- means for producing charge carriers in said first layer.
- 7. A combination in accordance with claim 6 wherein said first layer comprises silicon.
- 8. A combination in accordance with claim 1 wherein said semiconductor layer has a surface region on the opposite side thereof from said second layer which has a resistance at least one order of magnitude less than the resistance of said semiconductor layer.
- 9. A combination in accordance with claim 8 wherein said semiconductor layer has a surface region on the opposite side of said layer from said second layer which has a carrier concentration at least one order of magnitude greater than the average carrier density of said semiconductor layer.
- 10. A combination in accordance with claim 6 wherein the average bulk resistance of said first layer of semiconductor material is at least one order of magnitude less than the average bulk resistance of said second layer of said metal compound.
- 11. In combination:
- a first layer of semiconductor material;
- a second layer of substantially insulating material formed on said semiconductor layer and having apertures therein;
- a third layer contacting said first semiconductor layer through said apertures, said third layer being formed of a material having a higher bulk resistance than the average bulk resistance of said first layer;
- means for producing a reverse bias across the junction regions produced between said first semiconductor layer and said third layer in said apertures in said second layer; and
- means for producing charge carriers in said first layer.
- 12. A combination in accordance with claim 11 wherein said first layer comprises silicon, said second layer comprises a compound of silicon including oxygen, and said third layer comprises a metallic compound.
- 13. A semiconductor target for an image pickup tube comprising an insulating layer formed of silicon oxide mounted on a portion of one side of the substrate with another portion of said one side of said substrate exposed, and a semi-insulating layer having a resistivity of between about 10.sup.8 and 10.sup.10 ohm cm. on the exposed portion of the substrate and defining a junction for storing charges therewith, said semi-insulating layer also being on the insulating layer and forming a resistive sea.
- 14. In combination:
- a solid state junction device comprising a plurality of layers of different materials forming a substantially unidirectionally conductive junction at their interface;
- a first of said layers comprising semiconductor material;
- a second of said layers comprising a compound having a bulk resistivity which is substantially greater than the bulk resistivity of said first layer;
- said bulk resistivity of said second layer being between 10.sup.8 and 10.sup.10 ohm-centimeters;
- means for producing a voltage bias across said junction; and
- means for injecting charge carriers into the region of said junction.
- 15. A combination in accordance with claim 14 wherein said means for producing a voltage bias across said junction comprises an evacuated envelope containing an electron source and means for directing electrons from said source toward said plurality of layers.
- 16. A target for a cathode ray tube comprising:
- a semiconductor body;
- a first layer comprising insulating material having a plurality of apertures therein supported on a surface of said semiconductor body; and
- a plurality of barrier junctions formed in said apertures with said surface of said semiconductor body;
- said junctions comprising portions of a second layer of material having a resistivity between 10.sup.8 and 10.sup.10 ohm-centimeters extending over at least a plurality of said apertures and the intervening portions of said first layer between said apertures.
- 17. A target in accordance with claim 16 wherein said semiconductor substrate comprises silicon.
- 18. A target in accordance with claim 17 wherein said insulating layer comprises a compound of silicon.
- 19. A target in accordance with claim 17 wherein said apertured layer is silicon dioxide.
- 20. A target in accordance with claim 16 wherein said third layer comprises antimony trisulfide.
- 21. A semiconductor target for a cathode ray tube comprising:
- a semiconductor substrate having an insulating layer of silicon dioxide mounted on a portion of one side of said substrate with a plurality of other portions of said substrate exposed and a layer comprising material having a resistivity of between about 10.sup.8 and 10.sup.10 ohm-centimeters forming junctions with said exposed portions of said substrate for storing charges therewith, said layer extending continuously across said insulating layer between said junctions.
- 22. A semiconductor target for a cathode ray tube comprising:
- a single crystal semiconductor substrate supporting a semiinsulating layer having a resistivity of between about 10.sup.8 and 10.sup.10 ohm-centimeters on one side of said substrate and defining a junction for storing charges therewith.
- 23. An image pickup tube comprising:
- a target having a single crystal semiconductor substrate for producing charge carriers in response to radiation incident on said target through one surface thereof; and
- a junction on the opposite surface of said semiconductor substrate for storing charges produced by a scanning electron beam of said tube and discharged in accordance with the intensity of said radiation produced in said semiconductor substrate;
- said junction comprising a layer of material having a bulk resistivity of between about 10.sup.8 and 10.sup.10 ohm-centimeters supported on, and extending substantially across, the surface of said semiconductor substrate scanned by said electron beam, the thickness of said layer being substantially less than the thickness of said semiconductor substrate.
Parent Case Info
This is a continuation of application Ser. No. 76,920 filed Sept. 30, 1970.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
3670213 |
Nakagaw a |
Jun 1972 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
76920 |
Sep 1970 |
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