This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-198743, filed on Sep. 10, 2012, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor integrated circuit and an image sensor.
A voltage value read from an image sensor is converted into a digital signal by an A-D converter (Analog to Digital Converter, hereinafter also referred to as “ADC”). It is desired that the ADC is mounted as a circuit that is small as much as possible and the ADC operates consuming less power.
In general, according to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. The first analog voltage is inputted into the first electrode. The second analog voltage is inputted into the third electrode. One of a ground voltage and substantially ½ of a voltage of an input voltage range of the semiconductor integrated circuit is inputted into each second electrode and each fourth electrode.
Embodiments will now be explained with reference to the accompanying drawings.
Hereinafter, embodiments will be specifically described with reference to the drawings.
First, in the first stage, the sub-ADC 11 determines whether or not a condition 1: “Vin>1” is satisfied. When the condition 1 is satisfied, the SAR logic circuit 14 sets the most significant bit of the output digital signal Vout to “1” and generates a voltage V2 represented by the following formula (1a).
V2=Vin−Vref1/2 (1a)
On the other hand, when the condition 1 is not satisfied, the SAR logic circuit 14 sets the most significant bit of the output digital signal Vout to “0” and generates a voltage V2 represented by the following formula (1b).
V2=Vin+Vref1/2 (1b)
Here, the voltage Vref1 is a maximum value of the analog voltage Vin.
Next, in the second stage, the sub-ADC 11 determines whether or not a condition 2: “V2>0” is satisfied. When the condition 2 is satisfied, the SAR logic circuit 14 sets the second bit of the output digital signal Vout to “1” and generates a new voltage V3. The voltage V3 is represented by the formula (2a) below when the condition 1 is satisfied in the first stage and represented by the formula (2b) below when the condition 1 is not satisfied in the first stage.
V3=Vin−3Vref1/4 (2a)
V3=Vin+Vref1/4 (2b)
On the other hand, when the condition 2 is not satisfied, the SAR logic circuit 14 sets the second bit of the output digital signal Vout to “0” and generates a new voltage V3. The voltage V3 is represented by the formula (2c) below when the condition 1 is satisfied in the first stage and represented by the formula (2d) below when the condition 1 is not satisfied in the first stage.
V3=Vin−Vref1/4 (2c)
V3=Vin+3Vref1/4 (2d)
Subsequently, in the third stage, the sub-ADC 11 determines whether or not a condition 3: “V3>0” Is satisfied, and the SAR logic circuit 14 sets the third bit of the output digital signal Vout according to the determination result.
When the above three determinations are completed, the amplifier 12 multiplies the voltage V3, which is determined by the sub-ADC 11 at the third time, by gain “A” to generate a voltage A4 represented by the following formula (3), and then, the voltage A4 is inputted to the sub-ADC 13.
V4=A*V3 (3)
In an example shown in
In the fourth stage, the sub-ADC 13 determines whether or not a condition 4: “V4>0” is satisfied. The SAR logic circuit 14 generates a voltage V5 represented by the formula (4a) below when the condition 4 is satisfied and generates a voltage V5 represented by the formula (4b) below when the condition 4 is not satisfied.
V5=V4−Vref2/2 (4a)
V5=V4+Vref2/2 (4b)
However, regardless of whether or not the condition 4 is satisfied, the fourth bit of the output digital signal Vout is not set. The voltage V4 is obtained by only multiplying the voltage V3 by a constant gain. Therefore, the condition 4 is substantially equivalent to the condition 3, and thus, “whether or not the condition 4 is satisfied” accords with “whether or not the condition 3 is satisfied”. As described above, the process of the fourth stage in
Subsequently, in the fifth stage, the fourth bit of the output digital signal Vout is set according to whether or not the condition 5: “V5>0” is satisfied, and a voltage V6 is generated. Further, in the sixth stage, the fifth bit of the output digital signal Vout is set according to whether or not the condition 6: “V6>0” is satisfied.
In the manner as described above, the analog input voltage Vin is converted into a 5-bit output digital signal Vout.
According to the method described in
Therefore, in the present embodiment, it is intended to obtain an output digital signal Vout, the number of bits of which is greater than that obtained by
The process of the fourth stage is significantly different from that of
V4′=V4−Vref2/2 (5a)
V4′=V4+Vref2/2 (5b)
The sub-ADC 13 determines whether or not a condition 4′: “V4′>0” is satisfied.
The voltages V4′ represented by the above formulas (5a) and (5b) are the same as the voltages V5 shown in
Thereafter, in the fifth stage and the sixth stage, the fifth bit and the sixth bit of the output digital signal Vout are set respectively, and a 6-bit output digital signal Vout is obtained. When comparing
The number of bits can be increased by one bit compared with
V4p=V4/2+Vcm (6a)
V4n=−V4/2+Vcm (6b)
In other words, the difference between the differential signals V4p and V4n is the voltage V4. Here, the Vcm is a common voltage of the sub-ADC 13. For example, the Vcm is ½ of the power supply voltage of the sub-ADC 13. The sub-ADC 13 converts the difference between the differential signal V4p (first analog voltage) and the differential signal V4n (second analog voltage) into a digital signal.
The sub-ADC 13 includes capacitors 11p to 13p and 11n to 13n, switches 1pl to 3pl, 1ph to 3ph, 1nl to 3nl, 1nh to 3nh, 21p, and 21n, and a comparator 31.
Top plates (first electrodes) of the capacitors 11p to 13p are connected to each other and also connected to the positive input terminal of the comparator 31. The differential signal V4p is inputted into the top plates through the switch 21p. A voltage Vref2/2 can be supplied to a bottom plate (second electrode) of the capacitor 11p through the switch 1ph. Also a ground voltage can be supplied to the bottom plate of the capacitor 11p through the switch 1pl. The same applies on the capacitors 12p and 13p. Hereinafter, the capacitors 11p to 13p are also collectively referred to as “positive side capacitor” (first capacitor) 10p.
Top plates (third electrodes) of the capacitors 11n to 13n are connected to each other and also connected to the negative input terminal of the comparator 31. The differential signal V4n is inputted into these top plates through the switch 21n. The voltage Vref2/2 can be supplied to a bottom plate (fourth electrode) of the capacitor 11n through the switch 1nh. Also the ground voltage can be supplied to the bottom plate of the capacitor 11n through the switch 1nl. The same applies on the capacitors 12n and 13n. Hereinafter, the capacitors 11n to 13n are also collectively referred to as “negative side capacitor” (second capacitor) 10n.
The capacitances of the capacitors 11p, 12p, 11n, and 12p are the same, which is C. The capacitances of the capacitors 13p and 13n are double the above capacitance, that is, 2C.
The comparator 31 compares the voltage of the top plate of the positive side capacitor 10p and the voltage of the top plate of the negative side capacitor 10n. When the voltage of the top plate of the positive side capacitor 10p is greater than the voltage of the top plate of the negative side capacitor 10n, “1” is outputted to the SAR logic circuit 14 as a comparison result. When the voltage of the top plate of the negative side capacitor 10n is greater than the voltage of the top plate of the positive side capacitor 10p, “0” is outputted to the SAR logic circuit 14 as a comparison result.
Here, the voltage Vref2 is, for example, an input voltage range of the sub-ADC 13. By supplying a voltage Vref2/2, which is ½ of the input voltage range of the sub-ADC 13 instead of the input voltage range of the sub-ADC 13 itself, it is possible to reduce power consumption during switching. It is preferable that only two switches are connected to the bottom plate of each capacitor, and that one of two types of voltages (ground voltage or voltage Vref2/2) is supplied to the bottom plate and other voltages are not supplied. Thereby, the circuit configuration can be simplified.
The sub-ADC 13 in
The SAR logic circuit 14 of
When the SAR logic circuit 14 turns on the switches 21p and 21n, the differential voltages V4p and V4n are sampled by the top plates of the positive side capacitor 10p and the negative side capacitor 10n respectively, and electric charge according to each voltage is accumulated in the capacitor 10p and 10n. Subsequently, when the SAR logic circuit 14 turns off the switches 21p and 21n, the differential voltages V4p and V4n are held by the top plates of the positive side capacitor 10p and the negative side capacitor 10n, respectively. Hereinafter, such a processing operation is simply called “sample and hold of the differential voltages V4p and V4n”.
Note that, although the sub-ADC 11 in
When V3>0, the SAR logic circuit 14 controls the switches 1pl to 3pl, 1ph to 3ph, 1nl to 3nl, and 1nh to 3nh, to supply the voltage Vref2/2 to the bottom plate of the positive side capacitor 10p, and supply the ground voltage to the bottom plate of the negative side capacitor 10n. In this state, the differential signals V4p and V4n are sampled and held.
In this way, when the differential voltages V4p and V4n are sampled and held, the voltage supplied to the bottom plate of the positive side capacitor 10p is different from the voltage supplied to the bottom plate of the negative side capacitor 10n.
Subsequently, in the fourth stage, the SAR logic circuit 14 supplies the ground voltage to the bottom plates of the positive side capacitor 10p and the negative side capacitor 10n. Although the voltage of the bottom plate of the positive side capacitor 10p drops by the voltage Vref2/2, the amount of electric charge accumulated in the positive side capacitor 10p does not change. Therefore, the voltage of the top plate of the positive side capacitor 10p drops by the voltage Vref2/2 by capacitive coupling. As a result, the voltage V4p′ represented by the formula (7a) below is obtained.
V4p′=V4/2+Vcm−Vref2/2 (7a)
On the other hand, since the voltage of the bottom plate of the negative side capacitor 10n does not change, the voltage of the top plate of the negative side capacitor 10n does not change. As a result, the voltage V4n′ represented by the formula (7b) below is obtained.
V4n′=V4n=−V4/2+Vcm (7b)
The voltage V4′ (=V4−Vref2/2) shown in
When the condition 4′ is satisfied, in the fifth stage in FIG. 5, the SAR logic circuit 14 changes only the voltage supplied to the bottom plate of the capacitor 13n from the ground voltage to the voltage Vref2/2. As a result, the voltages V5p and V5n represented by the formulas (8a) and (8b) below are obtained by capacitive coupling.
V5p=V4/2+Vcm−Vref2/2 (8a)
V5n=−V4/2+Vcm+Vref2/4 (8b)
The voltage V5 (=V4−3Vref2/4) shown in
On the other hand, when the condition 4′ is not satisfied, in the fifth stage, the SAR logic circuit 14 changes only the voltage supplied to the bottom plate of the capacitor 13p from the ground voltage to the voltage Vref2/2. Thereafter, in the same manner as described above, the fifth significant bit of the output digital signal Vout is set.
In this way, in the fifth stage, the SAR logic circuit 14 switches the voltage supplied to the bottom plate of the capacitor 13p or the bottom plate of the capacitor 13n depending on whether or not the condition 4′ is satisfied.
Further, in the sixth stage shown in
In the manner as described above, it is possible to convert the input analog voltage Vin into the 6-bit output digital signal Vout.
In
Although the detailed description is omitted, even when the condition 3 is not satisfied, the output digital signal Vout can be generated by performing the same processes as those shown in
As described above, in the first embodiment, when the sub-ADC 13 samples and holds the differential voltages V4p and V4n inputted from the amplifier 12, the voltage supplied to the bottom plate of each capacitor is set according to the determination result of the third stage which is the last process by the sub-ADC 11. Therefore, the sub-ADC 13 can immediately perform an effective process in the fourth stage. As a result, it is possible to improve the bit accuracy of the output digital signal Vout without increasing the circuit area. Furthermore, the voltage Vref2/2, instead of the voltage Vref2, is supplied to the bottom plate of each capacitor. Therefore, the ADC operates with low power consumption.
In a second embodiment described below, the ADC is used for an image sensor.
The pixels 1 are arranged in a matrix form. The number of pixels in the horizontal (column) direction is n (for example, 1720 columns) and the number of pixels in the vertical (row) direction is m (for example, 832 rows). Each pixel 1 generates an analog voltage Vpix according to the intensity of emitted light, The pixel 1 belonging to k-th column outputs the generated voltage Vpix to a signal line Vpix(k). In the description below, the code “Vpix(k)” and the like are used as a name of a signal line (or a terminal) as well as a voltage value of the signal line (or the terminal).
The pixel 1 generates a voltage Vpix when no light is emitted (hereinafter referred to as a “reset voltage Vres”) and a voltage Vpix when light is emitted (hereinafter referred to as a “signal voltage Vsig”) to perform a so-called correlated double sampling.
The low decoder 2 sequentially selects one of m rows arranged in the vertical direction. Thereby, the voltages Vpix generated by the n pixels 1 belonging to the selected row are read to the signal lines Vpix(k) respectively.
One CDS circuit 3 is arranged for pixels in one column, so that a total of n CDS circuits 3 are arranged. In other words, the CDS circuit 3(0) to the CDS circuit 3(n−1) are provided corresponding to the signal lines Vpix(0) to Vpix(n−1), respectively. The CDS circuits 3 samples and temporarily holds the reset voltage Vres and the signal voltage Vsig which are read from the pixel 1. By holding both the reset voltage Vres and the signal voltage Vsig and amplifying a difference between both voltages later, it is possible to suppress the effect of variation of the reset voltages Vres among the pixels 1.
The column decoder 4 sequentially selects one of n CDS circuits 3(0) to 3(n−1) and supplies the reset voltage Vres and the signal voltage Vsig held by the selected CDS circuit 3 to the PGA 5.
The PGA 5 is an amplifier that amplifies the difference between the reset voltage Vres and the signal voltage Vsig. The PGA 5 outputs a voltage corresponding to the signal voltage Vsig as differential voltages Voutp and Voutn.
The pixel 1 includes nMOS transistors Qn1 to Qn4 and a photodiode PD that performs photoelectric conversion. Regarding the transistor Qn1, the drain is connected to a power supply terminal Vdd25, a reset signal RESET is inputted into the gate, and the source is connected to a floating diffusion FD. Regarding the transistor Qn2, the drain is connected to the floating diffusion FD, a read signal READ is inputted into the gate, and the source is connected to the cathode of the photodiode PD. The anode of the photodiode PD is connected to the ground terminal.
Regarding the transistor Qn3, the drain is connected to the power supply terminal Vdd25, an address signal ADR is inputted into the gate, and the source is connected to the drain of the transistor Qn4. Regarding the transistor Qn4, the gate is connected to the floating diffusion FD and a voltage Vpix is generated from the source. The source of the transistor Qn4 is connected to the signal line Vpix(k) and the voltage Vpix is outputted to the signal line Vpix(k).
The power supply voltage supplied by the power supply terminal Vdd25 is, for example, 2.5 V. The address signal ADR, the reset signal RESET, and the read signal READ are generated by, for example, the low decoder 2.
The pixel 1 operates as described below to generate the reset voltage Vres and the signal voltage Vsig.
First, the reset signal RESET is set to high. Thereby, the transistor Qn1 is turned on and the floating diffusion FD is initialized to a predetermined voltage. Thereafter, the reset signal RESET is set to low. Then, the read signal READ is set to high while no light is emitted on the pixel 1 in order to generate the reset voltage Vres. Thereby, the transistor Qn2 is turned on. At this time, only a negligible current flows in the photodiode PD, and thus, the voltage of the floating diffusion FD hardly drops. Here, when the address signal ADR is set to high, the transistor Qn3 is turned on. Thereby, the reset voltage Vres corresponding to the voltage of the floating diffusion FD is outputted to the signal line Vpix(k).
To generate the signal voltage Vsig, an operation similar to the above operation is performed while light is emitted on the pixel 1. A current corresponding to the intensity (brightness) of the emitted light flows in the photodiode PD. The higher the intensity of the light is, the larger the current is. Therefore, as the intensity of the light is higher, the voltage of the floating diffusion FD becomes lower. The signal voltage Vsig corresponding to the voltage of the floating diffusion FD is outputted to the signal line Vpix(k).
As described above, when the light is emitted, a current flows in the photodiode PD, and thus, the reset voltage Vres is higher than the signal voltage Vsig, that is, Vres>Vsig. By taking this into account, an ADC 6 which is suitable for an image sensor will be described.
In
Therefore, the descriptions of
The sub-ADC 11 samples and holds the reset voltage Vres at the top plate of the positive side capacitor 10p′ and the signal voltage Vsig at the top plate of the negative side capacitor 10n′.
Since Vres>Vsig as described above, the SAR logic circuit 14 performs the operation shown in
Thereafter, the switches 21p′ and 21n′ are turned off and the ground voltage is supplied to the bottom plates of the capacitors 10p and 10n (in the same manner as in the fourth stage in
In this way, the determination of the condition 1: “Vres−Vsig>0” can be omitted. Thereafter, the sub-ADC 11 may perform the same processes as those in
As described above, in the second embodiment, by using the fact that the reset voltage Vres is higher than the signal voltage Vsig, when these voltages are sampled and held by the capacitors, the voltages supplied to the bottom plates are set asymmetrically in the image sensor. Therefore, it is possible to improve efficiency of the A-D conversion process in the first-stage sub-ADC 11, reduce the circuit area of the ADC 6, and reduce the power consumption.
In the third embodiment described above, Vres>Vsig is assumed. However, due to noise or the like, an offset voltage Is subtracted from Vres or an offset voltage is added to Vsig, so that the magnitude correlation between the reset voltage Vres and the signal voltage Vsig may be reversed and Vres may be smaller than Vsig. The magnitude correlation between Vres and Vsig may be reversed by an offset voltage between differential signals in an analog circuit while the signals are transmitted though the CDS circuit 3 and PGA 5 to the ADC 6. In the present embodiment, the offset between differential signals is cancelled in the ADC 6.
For example, when the reset voltage Vres is actually 1.3 V by the noise and the like even though the reset voltage Vres is assumed to be 1.5 V, the A-D conversion as described above may be performed after adding an offset voltage Vofs=1.5V−1.3V=0.2V to the reset voltage Vres=1.3 V. In other words, in the first stage, whether or not “(Vres+Vofs)−Vsig−Vref1/2>0” is satisfied may be determined instead of determining whether or not the condition 2: “Vres−Vsig−Vref1/2>0” is satisfied.
In order to do this, when the reset voltage Vres and the signal voltage Vsig are sampled and held, the SAR logic circuit 14 may control the voltages supplied to the bottom plates according to the magnitude of the offset voltage Vofs.
Although the description is omitted, as indicated by the settings 0 to 8, the offset voltage Vofs can be adjusted to 8 steps from 0 to Vref1 by controlling the voltage supplied to the bottom plates. In the above description, an example is shown in which three capacitors are provided on each of the positive and the negative sides, so that the offset voltage Vofs can be adjusted to 8 steps. However, the offset voltage Vofs can be adjusted more finely by increasing the number of capacitors.
The voltage supply manner shown in
It has been described that the sub-ADC 11 performs an offset cancel function. However, more generally, the post-stage sub-ADC 13 can also perform the same offset cancel function. Thereby, for example, even when there is an offset between the positive output and the negative output of the amplifier 12, the offset can be cancelled.
In this way, in the third embodiment, when the reset voltage Vres and the signal voltage Vsig are sampled and held, the voltages supplied to the bottom plates of the capacitors are controlled according to the reset voltage Vres. Thereby, the offset of the reset voltage Vres can be cancelled.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fail within the scope and spirit of the inventions.
Number | Name | Date | Kind |
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8441386 | Strode | May 2013 | B2 |
Entry |
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Chun-Cheng Liu, et al., “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure”, IEEE Journal of Solid-State Circuits, vol. 45, No. 4, Apr. 2010, pp. 731-740. |
Yan Zhu, et al., “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS” IEEE Journal of Solid-State Circuits, vol. 45, No. 6, Jun. 2010, pp. 1111-1121. |
Number | Date | Country | |
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20140070975 A1 | Mar 2014 | US |