Patent Application
20060097324
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly relates to a semiconductor integrated circuit in which measures are taken to prevent antenna effect caused in plasma processing in metal interconnect formation of a semiconductor process.
2. Prior Art
In recent years, various kinds of plasma techniques have been used in a wiring process of a semiconductor process. Typical plasma techniques are, for example, dry etching used in patterning an interconnect layer, plasma TEOS deposition for forming an interlevel insulation film in a multi-layer wiring process, and the like. Hereinafter, such typical plasma techniques are collectively called “plasma processing”.
For example, in performing plasma etching, plasma charges are stored in a metal interconnect which is not connected to a doped layer of a semiconductor element. When charges exceeding a breakdown voltage of a gate oxide film of a transistor connected to the metal interconnect are stored, stored charges are discharged via the gate oxide film. As a result, the gate oxide film is broken down, transistor characteristics are changed due to change in the film quality of the gate oxide film, a hot carrier life-time is reduced, and some other inconvenience occurs. This phenomenon is called “antenna effect” and, hereinafter, an inconvenience caused by the antenna effect is referred to as “antenna damage”.
Antenna damage becomes worse when a finer design rule for semiconductor process is achieved. Factors of antenna damage are as follows. First, a gate oxide film of a transistor itself becomes a thin film and a breakdown voltage of the gate oxide film is reduced to a considerable extent, compared to the known process. Second, a minimum gate width is reduced as a design rule of semiconductor process becomes finer, whereas an interconnect length is not reduced so much even if a finer design rule for a semiconductor process is achieved. Another factor is that there is the tendency that even when over-etching occurs in dry etching of an interconnect, in order to ensure electromigration resistance of the interconnect and control a resistance value thereof, the thickness of an interconnect film can not be reduced so significantly while an interconnect width can be reduced. Furthermore, as a fourth factor, a plasma density in etching tends to be increased as an interconnect pattern becomes finer.
Because of the above-described factors, with an antenna ratio of 100,000, even though there has been no problem in the known 0.8 μm design rule CMOS generation and the like, antenna damage might occur in a finer process device. For example, in the case of a recent fine process (such as the 0.13 μm design process), antenna damage such as the occurrence of breakdown of a gate oxide film in the middle of a fabrication process step and deterioration of characteristics of a transistor might be caused in an LSI fabricated according to a general design even if the antenna ratio is at a level of about several thousands. Herein, in general, “antenna ratio” means to be the ratio between an area of a conductive layer in which plasma charges generated in plasma etching are stored and an area of a gate oxide film. Against this background, besides ESD protection for I/O ports in implementation and treatment thereof, which has been conventionally required, measures against electrostatic discharge have to be taken in a chip in consideration of wafer diffusion process. Note that antenna damage does not always occur when an antenna ratio is a predetermined level or more. Thus, it should be taken into consideration that if an interconnect to be processed in plasma processing is connected to a doped layer, plasma charges are released via the doped layer and antenna damage is not caused in a gate oxide film.
Next, a specific example for a known measure taken in the case where the antenna damage or an antenna rule error occurs in actual LSI designing will be described.
However, the above-described known measure to prevent antenna damage or an antenna rule error has the following problems. As a first problem, additional correction for an antenna rule error is needed. Another problem is that there is no clear and effective method which can be used when error correction is automated using a CAD tool. Specifically, at present, a CAD automatic placement and routing tool does not have the function of avoiding an antenna rule error beforehand and, therefore, an antenna rule error, which is to be found at a one-chip interconnect layout stage, i.e., a stage close to an end of designing can not be prevented. Therefore, under present circumstances, a designer manually adds an antenna protective diode or performs some other remedy to correct an error found at a stage where a mask order is about to be placed. As has been described, according to a known design method, reversion to a previous process step occurs and unexpected manual operation has to be performed. This has been a biggest problem of design automation.
Furthermore, there is another inconvenience. That is, some constraints are imposed on design style. In recent years, if a process step which can be performed in parallel with layout designing is used, the process step and layout designing are performed in parallel. By doing so, a time required for designing to fabrication of an LSI is reduced. For example, when in a stage where block level designing for a chip is completed, chip blocks are arranged, a mask order based on a base is placed, and then diffusion is started, layout designing proceeds in parallel to those processes. Therefore, in later designing, when an antenna rule error is found in layout designing of an upper layer using an aluminum interconnect, it is not possible to modify a lower layer design to correct the antenna rule error. In such a case, an error is avoided by wiring. That is, restrictions are imposed so that a metal interconnect in which an antenna rule error is caused is used for an even upper layer or like method is performed. By doing so, the metal interconnect is connected to a doped layer at the time of etching an interconnect and the antenna rule error is corrected. However, if the number of design modification is increased, a number of corrections are given to a chip on which an interconnect layout has been successfully done. Accordingly, an interconnect pattern and how dense the chip is with the upper aluminum interconnect are largely changed. As a result, when re-wiring is performed, the metal interconnect can not be made to settle on the chip having the same area as before correction of the antenna rule error, a timing error in logic circuit designing, which has not occurred before the correction of the antenna error, occurs due to the change in interconnect pattern and how dense the chip is with the upper aluminum interconnect, and some other inconvenience arises.
The present invention has been devised in view of the above-described problems. It is therefore an object of the present invention to provide a semiconductor integrated circuit in which antenna damage caused in plasma processing of semiconductor process can be avoided without causing reversion of designing.
To solve the above-described problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit designed using a standard cell. In the standard cell, at least one diode and one or more MOS transistors each comprising a gate electrode are provided, the diode being electrically connected to the gate electrode.
Thus, for example, in ASIC designing of a standard cell methodology or the like, a protective diode for preventing the occurrence of antenna damage or an antenna rule error is added beforehand to an input terminal of each cell in which an interconnect of which an antenna ratio has not been determined is to be provided. Thus, unlike the known design method, layout correction after an execution of layout, such as adding a protective diode to part of a chip in which an antenna rule error has occurred after an execution of chip layout, becomes no longer needed. Therefore, design efficiency in designing a semiconductor integrated circuit can be improved and a design period can be reduced.
In one embodiment of the present invention, the diode includes a first-conductive-type doped layer electrically connected to the gate electrode and a second-conductive-type well. Thus, the diode can be preferably added while increase in a chip area can be suppressed.
It is preferable that as the one or more MOS transistors, a plurality of MOS transistors are provided in the standard cell so as to share the gate electrode, and the plurality of MOS transistors includes a p-type MOS transistor and an n-type MOS transistor.
In one embodiment of the present invention, the diode is provided plural in number in the standard cell, the plurality of diodes include a first diode including a first-conductive-type doped layer electrically connected to the gate electrode, and a second-conductive-type well, and a second diode including a second-conductive-type doped layer electrically connected to the gate electrode, and a first-conductive-type well. Thus, both of positive plasma charges and negative plasma charges can be absorbed.
In one embodiment of the present invention, the gate electrode and the diode are electrically connected to each other via a shared contact. Thus, increase in a circuit area due to providing a diode can be suppressed.
In one embodiment of the present invention, the shared contact connects the gate electrode and the diode at each side of the gate electrode. Thus, a margin does not have to be provided in a connection portion of the gate electrode connected with the shared contact. Therefore, the width of the connection portion can be made to be the same as the width of the one or more MOS transistors and the shape of the gate electrode can be made to have dimensions close to expected values. Accordingly, variation in transistor characteristics of the one or more MOS transistors can be suppressed.
In one embodiment of the present invention, the gate electrode is provided plural in number in the standard cell, and diodes connected to adjacent ones of the plurality of gate electrodes, respectively, are arranged not so as to be adjacent to each other. Thus, increase in a circuit area can be suppressed.
In this case, if each of the plurality of gate electrodes is electrically connected, through a shared contact, to an associated one of the diodes located adjacent to the plurality of gate electrode, respectively, the width of a connection portion of the gate electrode connected with the shared contact can be preferably made to be the same as a gate length.
In one embodiment of the present invention, the gate electrode has branches arranged so as to be adjacent to each other and connected to diodes, respectively, and diodes connected to the branches, respectively, are arranged so as not to be adjacent to each other. Thus, increase in a circuit area can be suppressed.
A method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using a standard cell. The method includes the steps of: a) preparing a standard cell in which a MOS transistor including a gate electrode and a diode electrically connected to the gate electrode are provided; and b) disposing the standard cell by a design support apparatus.
According to the method, correction after a layout execution becomes no longer needed and a design period can be reduced.
Hereinafter, a semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in
In the semiconductor integrated circuit of the first embodiment, as described above, the diode 1 is provided between the gate electrode 13 of the MOS transistors and the second-conductive-type well 11 and the diode 2 is provided between the gate electrode 13 of the MOS transistors and the first-conductive-type well 12. Thus, charges can be released to a substrate via the diode 1 or the diode 2 when the substrate is processed in plasma processing. For example, plasma charges generated when a metal interconnect is patterned can be released. Therefore, antenna damage imposed on the gate electrode 13 of the MOS transistors can be reduced.
Even when only one of the diode 1 and the diode 2 is connected to the gate electrode 13, plasma charges can be also absorbed. However, to discharge positive plasma charges and negative plasma charges in the forward direction before a large amount of charges are stored, it is particularly effective to provide both of the diode 1 and the diode 2.
As described above, the semiconductor integrated circuit of this embodiment is characterized in that for the gate electrode 13 to be connected by automatic placement and routing, at least one diode is provided beforehand in a standard cell in which the gate electrode 13 is provided. Thus, the number of designing steps of the semiconductor integrated circuit can be reduced in the manner as described below.
As shown in
Thereafter, a MOS transistor including a gate electrode and a standard cell including a diode connected to the gate electrode are prepared using a design support apparatus 102, and the standard cell is registered in a cell library 105 using register means 111 (Step (a)).
Subsequently, a cell arrangement means 112 places the standard cell prepared in Step (a) according to the circuit specification 101 (Step (b)).
Thereafter, an inter-cell routing means 113 generates an interconnect. Note that a judgment means 114 does not have to perform detection for part of a chip having a large antenna ratio. In the above-described manner, a layout result 103 for a semiconductor integrated circuit can be obtained.
According to the designing method of this embodiment for designing a semiconductor integrated circuit, automatic placement and routing is performed using a standard cell in which a diode is provided beforehand to design a layout for a chip. Thus, unlike a known method, a situation where an antenna rule error is found after the layout of a chip is executed can be avoided and, therefore, correction of the antenna rule error after the execution of the layout, for example, by adding a diode to part of the chip in which the antenna error has occurred is not required. Moreover, manual design modification does not have to be performed. Therefore, design efficiency in designing a semiconductor device can be improved and thus a design turnaround time (design period) can be reduced. Specifically, compared to the known designing method of
Hereinafter, a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in
In the second embodiment, the diode 1 is provided between the gate electrode 13 of the MOS transistors and the second-conductive-type well 11 and the second diode 2 is provided between the gate electrode 13 of the MOS transistors and the first-conductive-type well 12 in the above-described manner. Thus, plasma charges generated in patterning of a metal interconnect and the like can be absorbed and antenna damage imposed on the gate electrode 13 of the MOS transistors can be reduced.
In this case, even when only one of the diode 1 and the diode 2 is provided, plasma charges can be also absorbed. However, to discharge positive plasma charges and negative plasma charges in the forward direction before a large amount of charges are stored, it is particularly effective to provide both of the diode 1 and the diode 2.
Moreover, the semiconductor integrated circuit of this embodiment is characterized in that a shared contact structure of
Thus, increase in a chip area resulting from providing a diode in a semiconductor integrated circuit can be suppressed.
Hereinafter, a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in
In the semiconductor integrated circuit of this embodiment, as in the semiconductor integrated circuits of the first and second embodiments, the first diode is provided between the gate electrode 13 of the MOS transistors and the second-conductive-type well 11 and the second diode 2 is provided between the gate electrode 13 of the MOS transistors and the first-conductive-type well 12 in the above-described manner. Thus, plasma charges generated in patterning a metal interconnect and the like can be absorbed and antenna damage imposed on the gate electrode 13 of the MOS transistors can be reduced.
In this case, even when only one of the diode 1 and the diode 2 is provided, plasma charges can be also absorbed. However, to discharge positive plasma charges and negative plasma charges in the forward direction before a large amount of charges are stored, it is particularly effective to provide both of the diode 1 and the diode 2.
This embodiment is characterized in that, as shown in
Hereinafter, a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with the accompanying drawings.
As shown in
In the semiconductor integrated circuit of
Moreover, as shown in
In the example of
The semiconductor device of this embodiment is characterized in that when a plurality of gate electrodes are arranged in parallel to one another, diodes connected to adjacent ones of the plurality of gate electrodes are arranged so as not to be adjacent to each other. In other words, diodes connected to adjacent ones of the plurality of gate electrodes are arranged on a diagonal line (in a staggered configuration). Moreover, when a single gate electrode has parts extending in parallel to each other, diodes provided in end portions are arranged in a staggered configuration so as not to be adjacent to each other.
Thus, increase in the area of a chip in the lateral direction (in the direction of extension of the cross-section of
Note that in the example of
As has been described, a method for designing a semiconductor device according to the present invention is useful for a method for preventing antenna damage due to the antenna effect generated in plasma processing when forming a metal film interconnect in a semiconductor process.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP 2004-326838 | Nov 2004 | JP | national |
This application claims priority under 35 U.S.C. §119(a) on Japanese Patent Application No. 2004-326838 filed on Nov. 10, 2004, the entire contents of which are hereby incorporated by reference.
