Semiconductor integrated circuit and method of designing semiconductor integrated circuit

Abstract

In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects as well as advantages of the invention will become clear by the following description of preferred embodiments of the invention. A number of benefits not recited in this specification will come to the attention of those skilled in the art upon the implementation of the present invention.

FIG. 1 is a circuit diagram showing a TDDB control cell provided with a decoupling capacitance as a semiconductor integrated circuit according to a preferred embodiment 1 of the present invention.

FIG. 2 is a layout plan view of the TDDB control cell according to the preferred embodiment 1.

FIG. 3 is a layout plan view illustrating a part of a logical block including the TDDB control cell provided with the decoupling capacitance according to the preferred embodiment 1.

FIG. 4 is a flow chart illustrating steps of a method of designing the semiconductor integrated circuit according to the preferred embodiment 1.

FIG. 5 is a circuit diagram illustrating a TDDB control cell provided with a correction circuit as a semiconductor integrated circuit according to a preferred embodiment 2 of the present invention.

FIG. 6 is a layout plan view of the TDDB control cell according to the preferred embodiment 2.

FIG. 7 is a circuit diagram illustrating a decoupling capacitance cell as a semiconductor integrated circuit according to a preferred embodiment 3 of the present invention.

FIG. 8 is a layout plan view of the decoupling capacitance cell according to the preferred embodiment 3.

FIG. 9 is a layout plan view illustrating a part of a logical block including the decoupling capacitance cells according to the preferred embodiment 3 and the TDDB control cell provided with the decoupling capacitance.

FIG. 10 is a flow chart illustrating steps of a method of designing the semiconductor integrated circuit according to the preferred embodiment 3.

FIG. 11 is a circuit diagram illustrating a TDDB control cell provided with a decoupling capacitance as a semiconductor integrated circuit according to a conventional technology.

FIG. 12 is a layout plan view of the TDDB control cell according to the conventional technology.

FIG. 13 is a flow chart illustrating procedures of a method for designing the semiconductor integrated circuit according to the conventional technology.

Claims

1. A semiconductor integrated circuit comprising: a decoupling capacitance circuit; a first output terminal; a second output terminal; a first power supply wiring; and a second power supply wiring, whereinthe decoupling capacitance circuit comprises:a TDDB control circuit comprising a first transistor and a second transistor; and a third transistor, whereinthe first transistor and the second transistor are different in conductivity type thereof from each other, a source of the first transistor is connected to the first power supply wiring, and a drain of the first transistor is connected to a gate of the second transistor,a source of the second transistor is connected to the second power supply wiring, and a drain of the second transistor is connected to a gate of the first transistor,a conductivity type of the third transistor is the same as that of the first transistor,a source and a drain of the third transistor are connected to the first power supply wiring, and a gate of the third transistor is connected to the drain of the second transistor,the first output terminal is connected to the drain of the first transistor, andthe second output terminal is connected to the drain of the second transistor.

2. The semiconductor integrated circuit as claimed in claim 1, wherein the first and third transistors are the one of the P-channel type, the second transistor is the one of the N-channel type, the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring.

3. A semiconductor integrated circuit comprising: a TDDB control circuit; a decoupling capacitance circuit;a first power supply wiring; a second power supply wiring; a first output terminal; and a second output terminal, whereinthe TDDB control circuit comprises a first transistor and a second transistor having conductivity types different from each other,a source of the first transistor is connected to the first power supply wiring, and a drain of the first transistor is connected to a gate of the second transistor,a source of the second transistor is connected to the second power supply wiring, and a drain of the second transistor is connected to a gate of the first transistor,the decoupling capacitance circuit comprises a third transistor having the same conductivity type as that of the second transistor,a source and a drain of the third transistor are connected to the second power supply wiring, and a gate of the third transistor is connected to the drain of the first transistor,the first output terminal is connected to the drain of the first transistor, andthe second output terminal is connected to the drain of the second transistor.

4. The semiconductor integrated circuit as claimed in claim 3, wherein the first transistor is the one of the P-channel type, the second and third transistors are the one of the N-channel type, the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring.

5. A semiconductor integrated circuit comprising: a TDDB control circuit; a decoupling capacitance circuit; a first power supply wiring; a second power supply wiring; a first output terminal; and a second output terminal, whereinthe TDDB control circuit comprises a first transistor and a second transistor respectively having conductivity types different from each other,a source of the first transistor is connected to the first power supply wiring, the source of the second transistor is connected to the second power supply wiring, and a drain of the first transistor is connected to a gate of the second transistor,a drain of the second transistor is connected to a gate of the first transistor,the decoupling capacitance circuit comprises a third transistor having the same conductivity type as that of the first transistor and a fourth transistor having the same conductivity type as that of the second transistor,a source and a drain of the third transistor are connected to the first power supply wiring, and a gate of the third transistor is connected to the drain of the second transistor,a source and a drain of the fourth transistor are connected to the second power supply wiring, and a gate of the fourth transistor is connected to the drain of the first transistor,the first output terminal is connected to the drain of the first transistor, andthe second output terminal is connected to the drain of the second transistor.

6. The semiconductor integrated circuit as claimed in claim 5, wherein the first and third transistors are the ones of the P-channel type, the second and fourth transistors are the ones of the N-channel type, the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring.

7. A semiconductor integrated circuit comprising: a TDDB control circuit; a correction circuit for correcting an operation defect or adding a function; a first power supply wiring; a second power supply wiring; a first output terminal; and a second output terminal, whereinthe TDDB control circuit comprises a first transistor and a second transistor having conductivity types different from each other,a source of the first transistor is connected to the first power supply wiring, and a drain of the first transistor is connected to a gate of the second transistor,a source of the second transistor is connected to the second power supply wiring, and a drain of the second transistor is connected to a gate of the first transistor,the correction circuit comprises at least one third transistor, and a power supply voltage or a ground voltage is applied fixedly to a gate of the third transistor when the third transistor is not being used,the drain of the first transistor or the drain of the second transistor is connected to the gate of the third transistor,the first output terminal is connected to the drain of the first transistor, andthe second output terminal is connected to the drain of the second transistor.

8. The semiconductor integrated circuit as claimed in claim 1, wherein the first power supply wiring is a high-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the input terminal, andthe input terminal is connected to the second output terminal through an inter-cell wiring.

9. The semiconductor integrated circuit as claimed in claim 3, wherein the first power supply wiring is a high-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type,a source and a drain of the transistor of the P-channel type are connected-to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the input terminal, andthe input terminal is connected to the second output terminal through an inter-cell wiring.

10. The semiconductor integrated circuit as claimed in claim 5, wherein the first power supply wiring is a high-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the input terminal, andthe input terminal is connected to the second output terminal through an inter-cell wiring.

11. The semiconductor integrated circuit as claimed in claim 7, wherein the first power supply wiring is a high-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the input terminal, andthe input terminal is connected to the second output terminal through an inter-cell wiring.

12. The semiconductor integrated circuit as claimed in claim 1, wherein the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the N-channel type,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the input terminal, andthe input terminal is connected to the first output terminal through an inter-cell wiring.

13. The semiconductor integrated circuit as claimed in claim 3, wherein the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the N-channel type,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the input terminal, andthe input terminal is connected to the first output terminal through an inter-cell wiring.

14. The semiconductor integrated circuit as claimed in claim 5, wherein the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the N-channel type,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the input terminal, andthe input terminal is connected to the first output terminal through an inter-cell wiring.

15. The semiconductor integrated circuit as claimed in claim 7, wherein the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell and an input terminal are further provided,the decoupling capacitance cell comprises a transistor of the N-channel type,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the input terminal, andthe input terminal is connected to the first output terminal through an inter-cell wiring.

16. The semiconductor integrated circuit as claimed in claim 1, wherein the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell, a first input terminal and a second input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type and a transistor of the N-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the first input terminal,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the second input terminalthe first input terminal is connected to the second output terminal through an inter-cell wiring, andthe second input terminal is connected to the first output terminal through an inter-cell wiring.

17. The semiconductor integrated circuit as claimed in claim 3, wherein the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell, a first input terminal and a second input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type and a transistor of the N-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the first input terminal,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the second input terminalthe first input terminal is connected to the second output terminal through an inter-cell wiring, andthe second input terminal is connected to the first output terminal through an inter-cell wiring.

18. The semiconductor integrated circuit as claimed in claim 5, wherein the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell, a first input terminal and a second input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type and a transistor of the N-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the first input terminal,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the second input terminalthe first input terminal is connected to the second output terminal through an inter-cell wiring, andthe second input terminal is connected to the first output terminal through an inter-cell wiring.

19. The semiconductor integrated circuit as claimed in claim 7, wherein the first power supply wiring is a high-voltage power supply wiring, and the second power supply wiring is a low-voltage power supply wiring, and a decoupling capacitance cell, a first input terminal and a second input terminal are further provided,the decoupling capacitance cell comprises a transistor of the P-channel type and a transistor of the N-channel type,a source and a drain of the transistor of the P-channel type are connected to the first power supply wiring, and a gate of the transistor of the P-channel type is connected to the first input terminal,a source and a drain of the transistor of the N-channel type are connected to the second power supply wiring, and a gate of the transistor of the N-channel type is connected to the second input terminalthe first input terminal is connected to the second output terminal through an inter-cell wiring, andthe second input terminal is connected to the first output terminal through an inter-cell wiring.

20. A method of designing a semiconductor integrated circuit comprising: a step of arranging logical cells for realizing a function in a logical block;a step of arranging a correction cell for correcting an operation defect or adding a function;a step of arranging a TDDB control cell comprising a decoupling capacitance circuit or a correction circuit and having a plurality of output terminals in a blank region of the logical block;a step of wiring between the arranged logical cells to each other; anda step of wiring between the TDDB control cell and the correction cell to each other.

21. A method of designing a semiconductor integrated circuit comprising: a step of arranging logical cells for realizing a function in a logical block;a step of arranging a correction cell for correcting an operation defect or adding a function;a step of arranging a TDDB control cell comprising a decoupling capacitance cell or a correction circuit and having a plurality of output terminals in a blank region of the logical block;a step of temporarily routing the logical cells to each other;a step of temporarily wiring the TDDB control cell and the correction cell to each other;a step of estimating a wiring congestion degree from a result of the temporary wirings;a step of deciding allocation number of the decoupling capacitance cells or the correction cells in accordance with the estimated wiring congestion degree;a step of performing a detailed wiring between the arranged logical cells to each other;a step of performing a detailed wiring between the TDDB control cell and the correction cell to each other.