BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view showing a logic cell of a semiconductor integrated circuit apparatus according to a first embodiment of the invention,
FIG. 2 is a view showing a power wiring unit cell on a minimum unit constituting a power wiring cell in the logic cell,
FIG. 3 is a view showing a power wiring unit cell having different cell heights in the power wiring unit cell,
FIG. 4 is a view showing a structure of a power wiring unit cell according to a second embodiment of the invention,
FIG. 5 is a view showing a structure of the power wiring unit cell according to the embodiment,
FIG. 6 is a view showing a logic cell of a semiconductor integrated circuit apparatus according to a third embodiment of the invention,
FIG. 7 is a view showing a structure of a power wiring unit cell in the logic cell,
FIG. 8 is a view showing a power wiring unit cell having different cell heights in the power wiring unit cell,
FIG. 9 is a view showing a logic cell of a semiconductor integrated circuit apparatus according to a fourth embodiment of the invention,
FIG. 10 is a view showing a power wiring unit cell in the logic cell,
FIG. 11 is a view showing a power wiring unit cell having different cell heights in the power wiring unit cell, and
FIG. 12 is a view showing a semiconductor integrated circuit apparatus constituted by using the conventional art.