Claims
- 1. A parallel data processing apparatus for processing plural data in parallel by a plurality of processors, wherein:
at least one of said plurality of processors have a plurality of series-connected logic circuits, and each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block coupled thereto consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said first logic block.
- 2. A parallel data processing apparatus according to claim 1, wherein said first and second logic blocks of each logic circuit are series-connected between a first source applied to a first of two ends of said first logic block, and a second source applied to a first of two ends of said second logic block, the second ends thereof constituting output parts of said first and second logic blocks and effecting a common connection of said first and second logic blocks.
- 3. A parallel data processing apparatus according to claim 2, wherein a potential setting circuit which sets the output signals of each of said series-connected logic circuits to a potential of said second source in synchronization with a clock signal is provided at each occurrence between adjacently disposed ones of said plurality of logic circuits.
- 4. A parallel data processing apparatus according to claim 3, wherein each said potential setting circuit comprises a precharge circuit connected between said first source and the second end of said first logic block and sets the output parts of said first and second logic blocks to a potential of said first source in synchronization with a clock signal and an inverter which sets the output signal of said logic circuit to a potential of said second source when said output parts of that logic circuit are set to the first potential level by said precharge circuit thereof.
- 5. A parallel data processing apparatus according to claim 4, wherein in at least a first stage of said plurality of series-connected logic circuits there is provided a timing control circuit which is connected between the first end of said first logic block and said second source and controls operating timing of said first block in synchronization with said clock signal.
- 6. A parallel data processing apparatus according to claim 5, wherein each said precharge circuit is provided with a PMOS transistor which forms a source/drain current path between said first source and the output parts of said first block of that logic circuit.
- 7. A parallel data processing apparatus according to claim 6, wherein said clock signal is a common clock signal for the precharge circuits of said plurality of logic circuits
- 8. A parallel data processing apparatus comprising:
a plurality of data processing units each having a processor and a memory; and a plurality of hard disks, wherein each of said data processing units is connected to corresponding ones of said hard disks and said data processing units are in mutual electrical connection to each other via a network, and wherein each of said processors has a plurality of series-connected logic circuits, and each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block coupled thereto consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said N-type logic block.
- 9. A parallel data processing apparatus according to claim 8, wherein said first and second logic blocks of each logic circuit are series-connected between a first source applied to a first of two ends of said first logic block, and a second source applied to a first of two ends of said second logic block, the second ends thereof constituting output parts of said first and second logic blocks and effecting a common connection of said first and second logic blocks.
- 10. A parallel data processing apparatus according to claim 9, wherein a potential setting circuit which sets the output signals of each of said series-connected logic circuits to a potential of said second source in synchronization with a clock signal is provided at each occurrence between adjacently disposed ones of said plurality of logic circuits.
- 11. A parallel data processing apparatus according to claim 10, wherein each said potential setting circuit comprises a precharge circuit connected between said first source and the second end of said first logic block and sets the output parts of said first and second blocks to a potential of said first source in synchronization with a clock signal and an inverter which sets the output signal of said logic circuit to a potential of said second source when said output parts of that logic circuit are set to the first potential level by said precharge circuit thereof
- 12. A parallel data processing apparatus according to claim 11, wherein in at least a first stage of said plurality of series-connected logic circuits there is provided a timing control circuit which is connected between the first end of said first logic block and said second source and controls operating timing of said first block in synchronization with said clock signal.
- 13. A parallel data processing apparatus according to claim 12, wherein each said precharge circuit is provided with a PMOS transistor which forms a source/drain current path between said first potential source and the output parts of said first block of that logic circuit.
- 14. A parallel data processing apparatus according to claim 13, wherein said clock signal is a common clock signal for the precharge circuits of said plurality of logic circuits.
- 15. A data processing unit comprising a floating point register unit, a floating point adder unit, a floating point multiplier unit, arithmetic and logic units, an address adder unit, a data cache unit and an instruction cache unit, wherein:
at least one of said floating point register unit, said floating point adder unit, said floating point multiplier unit, said arithmetic and logic units, said address adder unit, said data cache unit and said instruction cache unit have a plurality of series-connected logic circuits, and each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said N-type logic block.
- 16. A data processing unit according to claim 15, wherein said first and second logic blocks of each logic circuit are series-connected between a first source applied to a first of two ends of said first logic block, and a second source applied to a first of two ends of said second logic block, the second ends thereof constituting output parts of said first and second logic blocks and effecting a common connection of said first and second logic blocks.
- 17. A data processing unit according to claim 16, wherein a potential setting circuit which sets the output signals of each of said series-connected logic circuits to a potential of said second source in synchronization with a clock signal is provided at each occurrence between adjacently disposed ones of said plurality of logic circuits.
- 18. A data processing unit according to claim 17, wherein each said potential setting circuit comprises a precharge circuit connected between said first source and the second end of said first logic block and sets the output parts of said first and second logic blocks to a potential of said first source in synchronization with a clock signal and an inverter which sets the output signal of said logic circuit to a potential of said second source when said output parts of that logic circuit are set to the first potential level by said precharge circuit thereof.
- 19. A data processing unit according to claim 18, wherein in at least a first stage of said plurality of series-connected logic circuits there is provided a timing control circuit which is connected between the first end of said first logic block and said second source and controls operating timing of said first block in synchronization with said clock signal.
- 20. A data processing unit according to claim 19, wherein each said precharge circuit is provided with a PMOS transistor which forms a source/drain current path between said first source and the output parts of said first block of that logic circuit.
- 21. A data processing unit according to claim 20, wherein said clock signal is a common clock signal for the precharge circuits of said plurality of logic circuits.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-219809 |
Sep 1994 |
JP |
|
6-78363 |
Apr 1994 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No. 09/197,658, filed Nov. 23, 1998, which is a continuation of application Ser. No. 08/838,193, filed Apr. 16, 1997, now U.S. Pat. No. 5,841,300, which, in turn, was a continuation of application Ser. No. 08/423,374, filed Apr. 18, 1995, now abandoned, the entire disclosures of which are incorporated herein by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09197658 |
Nov 1998 |
US |
Child |
09887065 |
Jun 2001 |
US |