Claims
- 1. A parallel data processing apparatus comprising:a plurality of processors to process plural data in parallel, at least one of said processors including a plurality of series-connected logic circuits, wherein each of said logic circuits includes (i) a PMOS logic block having at least one P-type MOS transistor, (ii) a NMOS logic block coupled thereto and having at least one N-type MOS transistor, and (iii) a precharge circuit coupled solely between a high level source and an output part of said NMOS logic block and of said PMOS logic block, wherein the precharge circuits of said logic circuits, in synchronization with a clock signal, enable outputs of all of said logic circuits to be set to a low level in advance, and wherein each of said logic circuits, in response to an input signal applied thereto, provides an output signal which changes to a high level in accordance with said input signal changing from low level to high level and said at least one N-type MOS transistor turning ON.
- 2. A parallel data processing apparatus according to claim 1,wherein said PMOS and NMOS logic blocks of each logic circuit are series-connected between a first source having a first potential level applied to a first of two ends of said PMOS logic block, and a second source having a relatively lower second potential level applied to a first of two ends of said NMOS logic block, the second ends thereof constituting output parts of said PMOS and NMOS logic blocks and effecting a common connection of said PMOS and NMOS logic blocks.
- 3. A parallel data processing apparatus according to claim 2,wherein said precharge circuit is included in a potential setting circuit which sets the output of each of said series-connected logic circuits to the potential of said second source in synchronization with said clock signal and which is provided at each occurrence between the common connection of said PMOS and NMOS logic blocks of a preceding one of said logic circuits and an input of a succeeding logic circuit adjacent thereto.
- 4. A parallel data processing apparatus according to claim 3,wherein each said potential setting circuit comprises said precharge circuit connected between said first source and the second end of said PMOS logic block and sets the common connection of said PMOS and NMOS logic blocks to the potential of said first source in synchronization with a clock signal and an inverter which sets the output of said logic circuit to the potential of said second source when said common connection of said PMOS and NMOS logic blocks of that logic circuit is set to the first potential level by said precharge circuit thereof.
- 5. A parallel data processing apparatus according to claim 4,wherein in at least a first stage of said plurality of series-connected logic circuits there is provided a timing control circuit which is connected between the first end of said NMOS logic block and said second source and controls operating timing of said NMOS block in synchronization with said clock signal.
- 6. A parallel data processing apparatus according to claim 5,wherein each said precharge circuit is provided with a PMOS transistor which forms a source/drain circuit path between said first source and the second end of said PMOS logic block of that logic circuit.
- 7. A parallel data processing apparatus according to claim 6, wherein said clock signal is a common clock signal for the precharge circuits of said plurality of logic circuits.
- 8. A parallel data processing apparatus comprising:a plurality of data processing units each including a processor and a memory; and a plurality of hard disks, wherein each of said data processing units is connected to corresponding ones of paid hard disks and said data processing units are in mutual electrical connection to each other via a network, and wherein at least one said processor includes a plurality of series-connected logic circuits, each of said logic circuits including (i) a PMOS logic block having at least one P-type MOS transistor, (ii) a NMOS logic block coupled thereto and having at least one N-type MOS transistor and (iii) a precharge circuit coupled solely between a high level source and an output part of said NMOS logic block and of said PMOS logic block, wherein the precharge circuits of said logic circuits [precharge], in synchronization with a clock signal, enable outputs of all of said logic circuits to be set to a low level in advance, and wherein each of said logic circuits, in response to an input signal applied thereto, provides an output signal which changes to a high level in accordance with said input signal changing from low level to high level and said at least one N-type MOS transistor turning ON.
- 9. A parallel data processing apparatus according to claim 8,wherein said PMOS and NMOS logic blocks of each logic circuit are series-connected between a first source having a first potential level applied to a first of two ends of said PMOS logic block, and a second source having a relatively lower second potential level applied to a first of two ends of said NMOS logic block, the second ends thereof constituting output parts of said PMOS and NMOS logic blocks and effecting a common connection of said PMOS and NMOS logic blocks.
- 10. A parallel data processing apparatus according to claim 9,wherein said precharge circuit is included in a potential setting circuit which sets the output of each of said series-connected logic circuits to the potential of said second source in synchronization with said clock signal and which is provided at each occurrence between the common connection of said PMOS and NMOS logic blocks of a preceding one of said logic circuits and an input of a succeeding logic circuit adjacent thereto.
- 11. A parallel data processing apparatus according to claim 10,wherein each said potential setting circuit comprises a precharge circuit connected between said first source and the second end of said PMOS logic block and sets the common connection of said PMOS and NMOS blocks to the potential of said first source in synchronization with said clock signal and an inverter which sets the output of said logic circuit to the potential of said second source when said common connection of said PMOS and NMOS logic blocks of that logic circuit is set to the first potential level by said precharge circuit thereof.
- 12. A parallel data processing apparatus according to claim 11,wherein in at least a first stage of said plurality of series-connected logic circuits there is provided a timing control circuit which is connected between the first end of said NMOS logic block and said second source and controls operating timing of said NMOS logic block in synchronization with said clock signal.
- 13. A parallel data processing apparatus according to claim 12,wherein each said precharge circuit is provided with a PMOS transistor which forms a source/drain circuit path between said first source and the second end of said PMOS logic block of that logic circuit.
- 14. A parallel data processing apparatus according to claim 13, wherein said clock signal is a common clock signal for the precharge circuits of said plurality of logic circuits.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-78363 |
Apr 1994 |
JP |
|
6-219809 |
Sep 1994 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/197,658, filed Nov. 23, 1998, now abondened which is a continuation of application Ser. No. 08/838,193, filed Apr. 16, 1997, now U.S. Pat. No. 5,841,300, which, in turn, was a continuation of application Ser. No. 08/423,374, filed Apr. 18, 1995, now abandoned, the entire disclosures of which are incorporated herein by reference.
US Referenced Citations (12)
Foreign Referenced Citations (2)
Number |
Date |
Country |
2-277315 |
Nov 1990 |
JP |
402277315 |
Nov 1990 |
JP |
Continuations (3)
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Number |
Date |
Country |
Parent |
09/197658 |
Nov 1998 |
US |
Child |
09/887065 |
|
US |
Parent |
08/838193 |
Apr 1997 |
US |
Child |
09/197658 |
|
US |
Parent |
08/423374 |
Apr 1995 |
US |
Child |
08/838193 |
|
US |