Claims
- 1. A semiconductor device comprising:
a plurality of memory cells; an X-system circuit for accessing said plurality of memory cells, said X-system circuit including a plurality of MOSFETs; a Y-system circuit for accessing said plurality of memory cells; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said X-system circuit; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said Y-system circuit, wherein said first circuit and said second circuit are activated at different timings from each other.
- 2. A semiconductor integrated circuit according to claim 1,
wherein said X-system circuit includes a first decoder, and wherein said Y-system circuit includes a second decoder.
- 3. A semiconductor device comprising:
a plurality of memory cells; an X decoder for said plurality of memory cells, said X decoder including a plurality of MOSFETS; a Y decoder for said plurality of memory cells, said Y decoder including a plurality of MOSFETs; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said X decoder; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said Y decoder, wherein said first circuit and said second circuit are activated at different timings from each other.
- 4. A semiconductor device according to claim 3,
wherein said second circuit activates after said first circuit activates.
- 5. A semiconductor device comprising:
a plurality of memory cells; a plurality of sense amplifiers; a first address decoder, said first address decoder including a plurality of MOSFETs; a second address decoder, said first address decoder including a plurality of MOSFETs; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first address decoder; a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said second address decoder; and a third circuit provided in order to reduce a subthreshold leakage current of said plurality of sense amplifiers, wherein said first, second and third circuits are activated at different timings from each other.
- 6. A semiconductor device according to claim 5,
wherein said third circuit activates after said first circuit activates, and wherein said second circuit activates after said third circuit activates.
- 7. A semiconductor device comprising:
a plurality of memory cells; a plurality of sense amplifiers; an address decoder for decoding a plurality of X address signals, said address decoder including a plurality of transistors; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said address decoder; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said plurality of sense amplifiers, wherein said first circuit and said second circuit are activated at different timings from each other.
- 8. A semiconductor device according to claim 7,
wherein said second circuit activates after said first circuit activates.
- 9. A semiconductor memory device comprising:
a plurality of memory cells; a first circuit block comprising a plurality of transistors; a second circuit block comprising a plurality of transistors; a first circuit which enables to reduce a leakage current of said plurality of transistors of said first circuit block; and a second circuit which enables to reduce a leakage current of said plurality of transistors of said second circuit block, wherein said first circuit includes a first terminal coupled to said first circuit block, a second terminal supplied with a first voltage and a first switch coupled between said first terminal and said second terminal, wherein said second circuit includes a third terminal coupled to said second circuit block, a fourth terminal supplied with a second voltage and a second switch coupled between said third terminal and said fourth terminal, wherein said first switch is controlled by a first control signal, wherein said second switch is controlled by a second control signal which is different from said first control signal, and wherein a changing time of said second control signal from a disable level to an enable level is longer than a changing time of said first control signal from said disable level to said enable level.
- 10. A semiconductor device according to claim 9,
wherein said first circuit block comprises an X system circuit for said plurality of memory cells, and wherein said second circuit block comprises a Y system for said plurality of memory cells.
- 11. A semiconductor device according to claim 10,
wherein said changing time of said second control signal from said disable level to said enable level is more than two times said changing time of said first control signal from said disable level to said enable level.
- 12. A semiconductor device according to claim 9,
wherein the level of said first voltage is the same as that of said second voltage.
- 13. A semiconductor device comprising:
a plurality of memory cells; an X decoder including a plurality of transistors; a Y decoder including a plurality of transistors; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said X decoder; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said Y decoder, wherein said first circuit includes a first terminal coupled to said first circuit block, a second terminal supplied with a first voltage and a first switch coupled between said first terminal and said second terminal, wherein said second circuit includes a third terminal coupled to said second circuit block, a fourth terminal supplied with a second voltage and a second switch coupled between said third terminal and said fourth terminal, wherein said first switch is controlled by a first control signal, and wherein said second switch is controlled by a second control signal which is different from said first control signal.
- 14. A semiconductor device according to claim 13,
wherein the level of first voltage is the same as that of said second voltage.
- 15. A semiconductor device according to claim 13,
wherein said second control signal changes from a disable level to an enable level after said first control signal changes from said disable level to said enable level.
- 16. A semiconductor device comprising:
a plurality of memory cells; an X decoder for decoding a plurality of X address signals, said X decoder including a plurality of transistors; a Y decoder for decoding a plurality of Y address signals, said Y decoder including a plurality of transistors; a first circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said X decoder; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of transistors of said Y decoder, wherein said semiconductor device receives said plurality of X address signals in synchronism with a first strobe signal, wherein said semiconductor receives said plurality of Y address signals in synchronism with a second strobe signal which is different from said first strobe signal, and wherein said first circuit and said second circuit are activated at different timings from each other.
- 17. A semiconductor device according to claim 16,
wherein said second circuit activates after said first circuit activates.
- 18. A semiconductor device according to claim 16,
wherein said first strobe signal is a RAS signal, and wherein said second strobe signal is a CAS signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-349718 |
Dec 1995 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No. 08/985,425 filed Oct. 5, 1997; which is a continuation of application Ser. No. 08/762,883 filed Dec. 12, 1996, the entire disclosures of which are hereby incorporated by reference.
Continuations (4)
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Number |
Date |
Country |
Parent |
09875169 |
Jun 2001 |
US |
Child |
10040452 |
Jan 2002 |
US |
Parent |
09729273 |
Dec 2000 |
US |
Child |
09875169 |
Jun 2001 |
US |
Parent |
08985425 |
Dec 1997 |
US |
Child |
09729273 |
Dec 2000 |
US |
Parent |
08762883 |
Dec 1996 |
US |
Child |
08985425 |
Dec 1997 |
US |