Semiconductor integrated circuit device and related method

Abstract

Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described herein with reference to the accompanying drawings in which like reference symbols indicate like or similar elements throughout. In the drawings:

FIGS. 1 to 8 are cross-sectional views illustrating a method for fabricating a semiconductor integrated circuit device in accordance with an embodiment of the invention; and

FIGS. 9 to 11 are cross-sectional views illustrating a method for fabricating a semiconductor integrated circuit device in accordance with another embodiment of the invention.

Claims

1. A method for fabricating a semiconductor integrated circuit device, the method comprising: forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate, wherein each preliminary gate electrode structure comprises a gate electrode and a gate capping film formed on the gate electrode;forming first spacers on sidewalls of the preliminary gate electrode structures;forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region, wherein each selective epitaxial film is formed on a region of the semiconductor substrate exposed between gate electrodes;implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region, thereby forming transistors in the cell array region and the peripheral circuit region;forming a first interlayer insulating film on the semiconductor substrate;patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions and self-aligned between gate electrodes;forming a first ohmic film on the elevated source/drain regions exposed through the first openings;forming a first barrier film on the first ohmic film;forming a metal film on the first barrier film; andremoving a first portion of the metal film, a first portion of the first barrier film, and a first portion of the first ohmic film to form a plurality of self-aligned contact pads,wherein each self-aligned contact pad is node-isolated and the first portion of the metal film comprises at least one second portion of the metal film disposed on at least one of the gate capping films.

2. The method of claim 1, wherein forming the preliminary gate electrode structures comprises: sequentially forming a polysilicon film, a second ohmic film, a second barrier film, a tungsten film, and a capping film; andsequentially patterning the capping film, the tungsten film, the second barrier film, the second ohmic film, and the polysilicon film.

3. The method of claim 2, wherein: each gate electrode comprises a gate polysilicon film; andan upper surface of each selective epitaxial film is disposed higher than an upper surface of at least one of the gate polysilicon films.

4. The method of claim 1, wherein: the first openings expose at least some of the first spacers; andthe method further comprises, before forming the first ohmic film, forming one of a plurality of second spacers on each of the first spacers of the at least some of the first spacers exposed by the first openings.

5. The method of claim 1, wherein the first ohmic film is formed from a metal silicide.

6. The method of claim 5, wherein the metal silicide is a silicide of Ti, Co, W, or Ni.

7. The method of claim 1, wherein the first barrier film is formed from WN, TiN, TaN, BN, MoN, or CoN.

8. The method of claim 1, wherein the metal film is formed from W, TiN, or Al.

9. The method of claim 1, wherein the method further comprises, after forming the plurality of self-aligned contact pads: forming a second interlayer insulating film on the gate electrodes and the plurality of self-aligned contact pads;patterning the second interlayer insulating film to form a plurality of second openings exposing upper surfaces of at least some of the self-aligned contact pads, wherein the second openings expose at least one self-aligned contact pad disposed in the cell array region and expose at least one self-aligned contact pad disposed in the peripheral circuit region;filling the second openings with a metal material to form a plurality of contact plugs; andforming a metal wire on the second interlayer insulating film and the plurality of contact plugs.

10. The method of claim 9, wherein forming the plurality of second openings further comprises forming a plurality of third openings exposing upper surfaces of a plurality of miscellaneous gate electrode structures, wherein each miscellaneous gate electrode structure is formed in one of at least one miscellaneous region of the semiconductor substrate.

11. The method of claim 9, wherein the contact plugs are formed from W, TiN, or Al.

12. The method of claim 9, further comprising forming a second ohmic film and a second barrier film on the self-aligned contact pads exposed by the second openings before forming the plurality of contact plugs.

13. The method of claim 12, wherein the second ohmic film is formed from metal silicide.

14. The method of claim 13, wherein the metal silicide is metal silicide of Ti, Co, W, or Ni.

15. The method of claim 12, wherein the second barrier film is formed from WN, TiN, TaN, BN, MoN, or CoN.

16. A method for fabricating a semiconductor integrated circuit device, the method comprising: forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate, wherein each preliminary gate electrode structure comprises a gate electrode and a gate capping film formed on the gate electrode;forming first spacers on sidewalls of the preliminary gate electrode structures;forming a first interlayer insulating film on the semiconductor substrate;patterning the first interlayer insulating film to form a plurality of first openings exposing portions of the semiconductor substrate in the cell array region and the peripheral circuit region;forming selective epitaxial films on the portions of the semiconductor substrate exposed through the first openings;implanting impurities into the selective epitaxial films to form elevated source/drain regions, thereby forming transistors in the cell array region and the peripheral circuit region;forming a first ohmic film on the elevated source/drain regions exposed through the first openings;forming a first barrier film on the first ohmic film;forming a metal film on the first barrier film; andremoving a first portion of the metal film, a first portion of the first barrier film, and a first portion of the first ohmic film to form a plurality of self-aligned contact pads,wherein each self-aligned contact pad is node-isolated, and the first portion of the metal film comprises at least one second portion of the metal film disposed on at least one of the gate capping films.

17. The method of claim 16, wherein forming the preliminary gate electrode structures comprises: sequentially forming a polysilicon film, a second ohmic film, a second barrier film, a tungsten film, and a capping film; andsequentially patterning the capping film, the tungsten film, the second barrier film, the second ohmic film, and the polysilicon film.

18. The method of claim 17, wherein: each gate electrode comprises a gate polysilicon film; andan upper surface of each selective epitaxial film is disposed higher than an upper surface of at least one of the gate polysilicon films.

19. The method of claim 16, further comprising, after forming of the first openings, implanting impurities into portions of the semiconductor substrate exposed through the first openings.

20. The method of claim 16, wherein: the first openings expose at least some of the first spacers; andthe method further comprises, before forming the first ohmic film, forming one of a plurality second spacers on each of the first spacers of the at least some of the first spacers exposed by the first openings.

21. The method of claim 16, wherein the method further comprises, after forming the plurality of self-aligned contact pads: forming a second interlayer insulating film on the gate electrodes and the plurality of self-aligned contact pads;patterning the second interlayer insulating film to form a plurality of second openings exposing upper surfaces of at least some of the self-aligned contact pads, wherein the second openings expose at least one self-aligned contact pad disposed in the cell array region and expose at least one self-aligned contact pad disposed in the peripheral circuit region;filling the second openings with a metal material to form a plurality of contact plugs; andforming a metal wire on the second interlayer insulating film and the plurality of contact plugs.

22. The method of claim 21, wherein forming the plurality of second openings further comprises forming a plurality of third openings exposing upper surfaces of a plurality of miscellaneous gate electrode structures, wherein each miscellaneous gate electrode structure is formed in one of at least one miscellaneous region of the semiconductor substrate.

23. The method of claim 21, further comprising forming a second ohmic film and a second barrier film on the self-aligned contact pads exposed by the second openings before forming the plurality of contact plugs.

24. A semiconductor integrated circuit device comprising: a plurality of gate electrodes disposed on a cell array region and a peripheral circuit region of a semiconductor substrate;a plurality of gate capping films, wherein each of the gate capping films is disposed on one of the gate electrodes;first spacers formed on sidewalls of the gate electrodes;a first interlayer insulating film disposed on the semiconductor substrate, wherein groups of the gate electrodes are disposed in each of a plurality of first openings of the first interlayer insulating film;elevated source/drain regions, wherein each elevated source/drain region is disposed in one of a plurality of selective epitaxial films disposed on the semiconductor substrate in one of the first openings;a first ohmic film, wherein a plurality of portions of the first ohmic film are respectively disposed on at least some of the elevated source/drain regions;a first barrier film, wherein a plurality of portions of the first barrier film are respectively disposed on the portions of the first ohmic film; anda plurality of self-aligned contact pads respectively disposed on the portions of the first barrier film, wherein each self-aligned contact pad comprises a metal material.

25. The semiconductor integrated circuit device of claim 24, wherein each preliminary gate electrode comprises a gate polysilicon film, a gate ohmic film, a gate barrier film, and a gate tungsten film sequentially laminated.

26. The semiconductor integrated circuit device of claim 25, wherein an upper surface of each selective epitaxial film is disposed higher than an upper surface of at least one gate polysilicon film.

27. The semiconductor integrated circuit device of claim 24, further comprising: a second interlayer insulating film disposed on the first interlayer insulating film and comprising a plurality of second openings, wherein each second opening is disposed over one of the self-aligned contact pads;a second ohmic film, wherein a plurality of portions of the second ohmic film are respectively disposed in the second openings and respectively disposed on the self-aligned contact pads corresponding to the second openings;a second barrier film, wherein a plurality of portions of the second barrier film are respectively disposed in the second openings and respectively disposed on the self-aligned contact pads corresponding to the second openings;a plurality of contact plugs respectively filling the second openings; anda metal wire disposed on the second interlayer insulating film and on the plurality of contact plugs.

28. The semiconductor integrated circuit device of claim 27, wherein the second interlayer insulating film further comprises a plurality of third openings disposed on upper surfaces of a plurality of gate electrode structures, wherein each gate electrode structure is formed in at least one miscellaneous region of the semiconductor substrate.

29. The semiconductor integrated circuit device of claim 24, further comprising at least one second spacer disposed on at least one of the first spacers.