Semiconductor integrated circuit device having power reduction mechanism

Description

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit composed of scaled MOS transistors, and more particularly to a circuit suitable for high-speed and low power operation and an electronic device using the same.
BACKGROUND OF THE INVENTION
As the size of MOS transistors is scaled down, the breakdown voltage thereof is lowered as stated, for example, in the 1989 International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp. 188-192 (May 1989). Accordingly, the operating voltage thereof has to be lowered. In particular, the operating voltage is lowered even more for the purpose of achieving low power consumption for semiconductor devices used in a battery-operated portable equipment and the like.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit capable of operating at high speed and with low power consumption even when the size of MOS transistors is scaled down.
It is another object of the present invention to provide an electronic device capable of operating at high speed and with low power consumption and suitable for being battery powered drive even when the size of MOS transistors is scaled down.
To decrease power consumption for an integrated circuit having MOS transistors, it is necessary to lower the threshold voltage V.sub.T of the transistor in accord with the lowering of the operating voltage in order to maintain a high-speed operation. This is due to the fact that the operating speed is governed by the effective gate voltage of the MOS transistor, i.e., a value obtained by subtracting V.sub.T from the operating voltage, and the larger this value becomes, the higher the speed becomes. For example, a typical value of a threshold voltage of a transistor having a channel length of 0.25 .mu.m and operating at 1.5 V is anticipated to be 0.35 V according to the above-mentioned document. According to a well-known scaling law, the typical value of the threshold voltage becomes approximately 0.24 V when it is assumed that the operating voltage is 1 V. If VT is brought down to approximately 0.4 V or lower, however, it becomes no longer possible to turn the transistor completely off and a D.C. current starts to flow through it due to the sub-threshold characteristics (tailing characteristics) of the MOS transistor as described hereafter. Thus, this current becomes a serious issue in the practical operation of a device having MOS transistors at 1.5 V or lower.
A conventional CMOS inverter shown in FIG. 60 will be described. Ideally, an N-channel MOS transistor M.sub.N is turned off when an input signal IN is at a low level (=V.sub.SS), and a P-channel MOS transistor M.sub.P is turned off when IN is at a high level (=V.sub.CC), thus no current flows in either case. When V.sub.T of the MOS transistor becomes low, however, the subthreshold current can no longer be disregarded.
As shown in FIG. 61, a drain current I.sub.DS in a subthreshold region is in proportion to an exponential function of a gate-source voltage V.sub.GS and is expressed by the following expression. ##EQU1## Where, W indicates a channel width of the MOS transistor, I.sub.o and W.sub.o indicate a current value and a channel width when V.sub.T is defined, and S indicates a subthreshold swing (the gate-voltage swing needed to reduce the current by one decade). Thus, a subthreshold current; ##EQU2## flows even when V.sub.GS =0. Since V.sub.GS =0 in the transistor in an off-state of the CMOS inverter shown in FIG. 60, the current I.sub.L mentioned above will flow from the high power supply voltage V.sub.CC toward the low power supply voltage V.sub.SS which is at ground potential, even at the time of non-operation.
This subthreshold current increases exponentially from I.sub.L to I.sub.L ' when the threshold voltage is lowered from V.sub.T to V.sub.T ' as shown in FIG. 61.
As is apparent from the above expression (2), it is sufficient either to increase V.sub.T or to decrease S in order to reduce the subthreshold current. However, the former method brings about a lowering of the speed due to a lowering of the effective gate voltage. In particular, when the operating voltage is lowered with the scale-down of the breakdown voltage, the decrease in speed becomes notable and the advantages of scaled down fabrication can no longer be put to practical use, which is not preferable. Further, the latter method is difficult to apply for room temperature operation because of the following reasons.
The subthreshold swing S is expressed by the capacitance C.sub.OX of a gate insulator and the capacitance C.sub.D of a depletion layer under the gate as follows. ##EQU3## Where, k indicates the Boltzmann constant, T indicates absolute temperature, and q indicate the elementary charge. As is apparent from the above expression, S>kT in 10/q irrespective of C.sub.OX and C.sub.D, thus it is difficult to bring it to 60 mV or lower at room temperature.
The substantial D.C. current of a semiconductor integrated circuit composed of a plurality of MOS transistors increases remarkably due to the phenomenon described above. Namely, since V.sub.T has to be made lower as the operating voltage is lowered at a constant operating speed, the situation becomes more serious when the operation is performed at a lower voltage. At the time of operation at a high temperature in particular, V.sub.T becomes lower and S becomes larger. Therefore, this problem becomes even more serious. In the times of downsizing of computers or the like for the future when low power consumption is important, the increase of the subthreshold current is a substantial issue. In particular, in an electronic device which is desired to be operated by one power cell of a level of 0.9 to 1.6 V, it is also very important to cope with the increase of the current.
In order to solve the above-described problems, according to the present invention, control circuit means for controlling the supply of a large current and a small current is inserted between the source of a MOS transistor and the power supply so as to apply a current to the MOS transistor circuit by switching these currents in accordance with their use. For example, a large current is supplied when high-speed operation is required, and a small current is supplied when low power consumption is required.
Since high-speed operation is required at time of normal operation, a large current is supplied to the MOS transistor circuit from the current supply means so as to make high-speed operation possible. At this time, a D.C. current flows in the MOS transistor circuit as described previously, which, however, is sufficiently small normally as compared with the operating current, i.e., charging and discharging current of a load, thus causing no problem.
On the other hand, since low power consumption is required at the time of standby, the supplied current is changed over to a small current so as to restrain the subthreshold current. At this time, a logic voltage swing of a MOS transistor circuit generally may become smaller than that at the time of supplying a large current because the current is limited, but there is no problem in so far as ensuring the logic level.
As described above, it is possible to realize a high-speed and low power consuming MOS transistor circuit and an electronic device composed of the same according to the present invention.
Besides, the present invention has been described with a MOS semiconductor integrated circuit device as an example, but the present invention is applicable to a metal insulator semiconductor (MIS) integrated circuit device in general.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1(A) is a diagram showing an inverter in an embodiment 1 of the present invention;
FIG. 1(B) is a diagram showing the voltage levels of signals of the inverter in the embodiment 1;
FIG. 2 is a diagram showing a principle of subthreshold current reduction according to the present invention;
FIG. 3 is a diagram showing the subthreshold current reduction effect according to the present invention;
FIG. 4 is a circuit diagram showing an inverter in an embodiment 2 of the present invention;
FIGS. 5(A) to 5(C) are diagrams showing the timing of signals of the present invention;
FIG. 6 is a diagram showing a device structure of the present invention;
FIG. 7 is a circuit diagram of an inverter in an embodiment 3 of the present invention;
FIG. 8 is a circuit diagram of an inverter in an embodiment 4 of the present invention;
FIG. 9 is a diagram showing a device structure of the present invention;
FIG. 10(A) is a diagram showing an inverter chain in an embodiment 5 of the present invention;
FIG. 10(B) is a diagram showing voltage levels of signals of the inverter chain in the embodiment 5;
FIG. 11(A) is a diagram showing an inverter chain in an embodiment 6 of the present invention;
FIG. 11(B) is a diagram showing voltage levels of signals of the inverter chain in the embodiment 6;
FIG. 12(A) is a diagram showing an inverter chain in an embodiment 7 of the present invention;
FIG. 12(B) is a diagram showing voltage levels of signals of the inverter chain in the embodiment 7;
FIG. 13 is a diagram showing an example of a grouping of a combinational logic circuit applied with the present invention;
FIG. 14 is a diagram showing a combinational logic circuit in an embodiment 8 of the present invention;
FIG. 15 is a diagram showing a combinational logic circuit in an embodiment 9 of the present invention;
FIGS. 16(A) and 16(B) are diagrams showing a latch in an embodiment 10 of the present invention;
FIG. 17 is a circuit diagram showing a latch in an embodiment 11 of the present invention;
FIG. 18 is a circuit diagram of an inverter chain in an embodiment 12 of the present invention;
FIG. 19 is a circuit diagram of an inverter chain in an embodiment 13 of the present invention;
FIG. 20 is a circuit diagram of a NAND gate in an embodiment 14 of the present invention;
FIG. 21 is a circuit diagram of a NOR gate in an embodiment 15 of the present invention;
FIG. 22 is a circuit diagram of a clocked inverter in an embodiment 16 of the present invention;
FIG. 23 is a circuit diagram of a combinational logic circuit in an embodiment 17 of the present invention;
FIG. 24 is an example of a layout arrangement of a combinational logic circuit in the embodiment 17 of the present invention;
FIG. 25 is a circuit diagram of a latch in an embodiment 18 of the present invention;
FIG. 26 is a circuit diagram of an output buffer in an embodiment 19 of the present invention;
FIG. 27 is a circuit diagram of an input buffer in an embodiment 20 of the present invention;
FIG. 28 is a circuit diagram of an NMOS dynamic circuit in an embodiment 21 of the present invention;
FIG. 29 is a diagram showing an embodiment 22 of the present invention, conceptually;
FIG. 30 is a circuit diagram of a CMOS inverter in an embodiment 23;
FIG. 31 is an operation timing diagram of a CMOS inverter in an embodiment 23;
FIG. 32 is a diagram showing an inverter chain in an embodiment 24;
FIG. 33 is a diagram showing an inverter chain in an embodiment 25;
FIG. 34 is a diagram showing a CMOS inverter in an embodiment 26;
FIG. 35 is a circuit diagram of a level hold circuit in an embodiment 27;
FIG. 36 is a diagram showing a first embodiment of a power switch control of a plurality of circuit blocks according to the present invention;
FIG. 37 is a diagram showing an example of the operation of FIG. 36;
FIG. 38 is a diagram showing a modification to the first embodiment of the power switch control of a plurality of circuit blocks shown in FIG. 36;
FIG. 39 is a diagram showing a second embodiment of the power switch control in a clock synchronized operation according to the present invention;
FIG. 40 is a diagram showing an example of the operation of FIG. 39;
FIG. 41 is a diagram showing a third embodiment of the power switch control according to the present invention;
FIG. 42 is a diagram showing an example of the operation of the control example of FIG. 41;
FIG. 43 is a diagram showing a fourth embodiment of the power switch control according to the present invention;
FIG. 44 is a diagram showing an example of the operation of the control example of FIG. 43;
FIG. 45 is a diagram showing a fifth embodiment of the power switch control according to the present invention;
FIG. 46 is a circuit diagram showing a latch capable of providing a fixed output;
FIG. 47 is a timing chart for explaining the timing of the operation of the circuit of FIG. 46;
FIG. 48 is a circuit diagram of a latch capable of providing a fixed output;
FIG. 49 is a timing chart for explaining the timing of the operation of the circuit of FIG. 48;
FIG. 50 is a diagram showing a dual-phase clock logic circuit;
FIG. 51 is a circuit diagram showing an inverter operating with a dual-phase clock;
FIG. 52 is a timing chart useful for explaining the operation of the circuit shown in FIGS. 50 and 51;
FIG. 53(A) shows an embodiment of the invention applied to a gate array; and FIG. 53(B) shows a logic diagram;
FIG. 54(A) shows another embodiment of the invention applied to a gate array;
FIG. 54(B) shows a logic diagram;
FIG. 55 is a block diagram showing a single-chip microprocessor constructed according to an embodiment of the invention;
FIG. 56 is a diagram showing an internal structure of the co-processor of the microprocessor of FIG. 55;
FIG. 57 is a diagram showing the internal structure of the local memory of the microprocessor shown in FIG. 55;
FIG. 58 is a diagram showing the internal structure of the bus control unit for the microprocessor of FIG. 55;
FIG. 59 is a timing diagram useful for explaining the operation of the microprocessor of FIG. 55, according to the present invention;
FIG. 60 is a circuit diagram of a conventional CMOS inverter; and
FIG. 61 is a diagram showing subthreshold characteristics of a MOS transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
Specific embodiments of the present invention will be described in more detail hereinafter with reference to the drawings.
Embodiment 1
First, FIGS. 1(A) and 1(B) show an embodiment suitable for explaining a principle of the present invention.
FIG. 1(A) is a circuit diagram of an inverter according to an embodiment of the present invention. In FIG. 1(A), L represents a CMOS inverter, which is composed of a P-channel MOS transistor Mp and an N-channel MOS transistor MN. The present invention is applicable not only to an inverter, but also to logic gates such as NAND and NOR circuits or to a logic gate group as described later. However, a case of an inverter will be described herein for the sake of simplicity. S.sub.C and S.sub.S represent switches and R.sub.C and R.sub.S represent resistances. In the present embodiment, switches S.sub.C and S.sub.S and resistances R.sub.C and R.sub.S are inserted in parallel between power supply terminals V.sub.CL and V.sub.SL of an inverter L and power supplies V.sub.CC and V.sub.SS, respectively. With this arrangement, subthreshold current reduction is realized as described hereinafter.
In a period where high-speed operation is required, the switches S.sub.C and S.sub.S are switched on, and V.sub.CC and V.sub.SS are applied directly to the inverter L (hereinafter referred to as a high-speed operation mode). High-speed operation can be performed if threshold voltages V.sub.T of M.sub.P and M.sub.N are set low. At this time, a subthreshold current flows in the inverter L as described previously, which, however, causes no problem since the current is normally sufficiently small as compared with an operating current, i.e., charging and discharging current of a load.
On the other hand, in a period where low power consumption is required, the switches S.sub.C and S.sub.S are switched off and power is supplied to the inverter through the resistances R.sub.C and R.sub.S (hereinafter referred to as a low power consumption mode). As a result of the voltage drop due to the fact that the subthreshold current flows through resistances, V.sub.CL drops lower than V.sub.CC and V.sub.SL rises higher than V.sub.SS. As shown in FIG. 2, the subthreshold current decreases due to the voltage drop by means of the following two types of mechanisms. Incidentally, the following description is given for M.sub.N when an input signal IN is at a low level (V.sub.SS), but the same description applies to M.sub.P when IN is at a high level (V.sub.CC).
(i) Since the source potential V.sub.SL rises, backgate bias V.sub.BS =V.sub.SS -V.sub.SL =-V.sub.M is applied, and the threshold voltage rises from V.sub.T0 to V.sub.T1. The rise portion of the threshold voltage is expressed as: ##EQU4## With this, the subthreshold current decreases from I.sub.L0 to I.sub.L1. The rate of decrease is: ##EQU5## Where, K is a body effect factor. For example, when V.sub.M =0.3 V, K=0.4 .sqroot.V, S=100 mV/decade and 2.PSI.=0.64 V, the subthreshold current is reduced to 21%.
(ii) Since a source potential V.sub.SL rises, the gate-source voltage V.sub.GS =V.sub.SS -V.sub.SL =-V.sub.M becomes negative. With this, the subthreshold current decreases further from I.sub.L1 to I.sub.L2. The rate of decrease is: ##EQU6## For example, when V.sub.M =0.3 V and S=100 mV/decade, the subthreshold current is reduced to 0.1%.
When the effects of (i) and (ii) are put together, the following expression is obtained. ##EQU7## For example, when V.sub.M =0.3 V, the subthreshold current is reduced to 0.02%. Where, V.sub.M represents the solution of the following equation. ##EQU8##
Incidentally, the back gates of the MOS transistors M.sub.P and M.sub.N of the inverter L may be connected to respective sources V.sub.CL and V.sub.SL, but it is more desirable to connect the back gates to V.sub.CC and V.sub.SS as shown in FIG. 1(A) in order to obtain the effect (i) identified above.
FIG. 3 shows a subthreshold current reduction effect. Here, a future very large scale LSI operating at an ultra low voltage is assumed, and computation is made with respect to a case that a threshold voltage V.sub.TO =0.05 to 0.15 V when the back gate bias is 0 and the sum total W of the channel widths of transistors in an off state in the whole LSI is W=100 m. The more the resistance is increased, the larger V.sub.M becomes, thus increasing the effect. As an extreme case, it is also possible to make the resistance infinite, i.e., to remove the resistance.
However, as shown in FIG. 1(B), the logic voltage swing of the output signal OUT becomes smaller than the logic voltage swing of the input signal IN. Accordingly, consideration of voltage levels of the signals in the case of a multistage connection must be taken into account and such a case will be described later.
Further, the present invention has a function of compensating fluctuation of the threshold voltage automatically. Namely, when the threshold voltage is low and the subthreshold current is large, the voltage drop V.sub.M becomes larger, and, when the threshold voltage is high and the subthreshold current is small, V.sub.M becomes smaller. In either case, the fluctuation of the current is restrained. As is apparent from FIG. 3, the fluctuation of the subthreshold current is smaller as the resistance value becomes larger. For example, when the resistance value is set to 3 K.OMEGA. or more, the fluctuation of the subthreshold current I.sub.L is restrained within .+-.20% even if the threshold voltage fluctuates by .+-.0.05 V.
Embodiment 2
Next, a specific method for realizing a switch and a resistance explained in the embodiment 1 will be described. FIG. 4 shows an example in which both the switch and the resistance are realized by MOS transistors.
Switching MOS transistors M.sub.C1 and M.sub.S1 are those that have large conductance, and correspond to the switches S.sub.C and S.sub.S shown in FIG. 1(A), respectively. In a high-speed operation mode, M.sub.C1 and M.sub.S1 are turned on by bringing a signal .phi..sub.C to a low level and .phi..sub.S to a high level. The voltage levels of .phi..sub.C and .phi..sub.S may be V.sub.SS and V.sub.CC, respectively, but it may also be arranged so that .phi..sub.C is set lower than V.sub.SS and .phi..sub.S is set higher than V.sub.CC in order to make the conductances of M.sub.C1 and M.sub.S1 larger. It is sufficient to apply the voltages for the above from the outside of a chip or to generate the same by an on-chip booster circuit well known in an EEPROM and a DRAM.
In a low power consumption mode, M.sub.C1 and M.sub.S1 are turned off by bringing .phi..sub.C to a high level and .phi..sub.S to a low level conversely to the above. At this time, the current is cut off by one of two methods, for example. In a first method, .phi..sub.C is made higher than V.sub.CC and .phi..sub.S lower than V.sub.SS by means of the external voltage or the on-chip booster circuit. In a second method, transistors having threshold voltages higher (more enhanced) than those used in the inverter L are used as M.sub.C1 and M.sub.S1. The first method has such a merit that the process for producing transistors having different threshold voltages is unnecessary. On the other hand, the second method is advantageous since the implementation area does not require terminals for receiving external voltages or an on-chip booster circuit.
MOS transistors M.sub.C2 and M.sub.S2 are those that have small conductance, and correspond to the resistances R.sub.C and R.sub.S shown in FIG. 1(A), respectively. These transistors are connected to V.sub.SS and V.sub.CC at the gate thereof, respectively, and are always in an on-state. Since it is not required to turn off these transistors, there is no problem even if the threshold voltages thereof are low.
Incidentally, it is also possible to use an N-channel MOS transistor as M.sub.C2 and a P-channel MOS transistor as M.sub.S2. For example, taking an N-channel MOS transistor of M.sub.C2 as an example, a resistance can be realized effectively by what is called a diode connection in which a terminal connected with the gate and the drain thereof is connected to the terminal V.sub.CC, and the source thereof is connected to the terminal V.sub.CL. By controlling the channel width and the threshold voltage of the N-channel MOS transistor, the voltage V.sub.CL can be set to a voltage dropped from V.sub.CC by the threshold voltage of the N-channel MOS transistor at the time of standby for instance, thus making it possible to reduce the subthreshold current with a large margin.
Next, an example of an application of the timing to be used with the present invention will be described. FIGS. 5(A) to 5(C) show examples of the timing of signals .phi..sub.C and .phi..sub.S.
FIG. 5(A) and FIG. 5(B) show applications where the present invention is applied to a memory LSI. The memory LSI is brought into an operating state when a chip enable signal CE (a complementary signal), which is a clock signal from the outside, is at a low level, and a standby state when the signal CE is at a high level. In the case of FIG. 5(A), an internal signal .phi..sub.C is brought to a low level synchronously with the fall of CE and brought to a high level slightly behind the rise of CE. The internal signal .phi..sub.S is opposite thereto. Thus, the period shown at a in the figure becomes the high-speed operation mode, and the period b becomes the low power consumption mode. Generally, in a memory unit using a plurality of memory LSIs, LSIs in the operating state are small in number, and a large majority of LSIs are in the standby state. Accordingly, when those LSIs that are in the standby state are brought into a low power consumption state using the present invention, it contributes greatly to obtaining a low power consumption of a memory unit. Besides, the reason for providing delay from the rise of CE until entering into the low power consumption mode is that an internal circuit of the LSI is reset in the interim.
FIG. 5(B) shows an example in which further low power consumption is achieved. Here, only immediately after CE has changed is the LSI operation period brought into the high-speed operation mode. Namely, read-write of data are performed immediately after CE is brought to a low level, and the internal circuit is reset immediately after CE is brought to a high level. Therefore, these LSI operation periods are brought into the high-speed operation mode according to the present invention, and other LSI operation periods are brought into the low power consumption mode according to the present invention. Alternatively, the high-speed operation mode may be entered into when an address signal changes.
FIG. 5(C) shows an example in which the present invention is applied to a microprocessor. A clock signal CLK is applied in a normal operation state. At this time, the signal .phi..sub.C is at a low level and .phi..sub.S is at a high level, presenting the high-speed operation mode. When the microprocessor is brought into a standby state or a data holding state, the clock signal CLK is suspended, and a signal BU is brought to a high level. .phi..sub.C shows the high level and .phi..sub.S shows the low level synchronously with the above, presenting the low power consumption mode. With this, the power consumption of the microprocessor is reduced, thus making it possible to operate the microprocessor in a backup mode for a long period of time with a power supply of small capacity, such as a battery.
FIG. 6 shows an example of a device having a semiconductor structure for realizing the circuit shown in FIG. 4. Polysilicon 130, 131, 132 and 133 in the figure correspond to gates of MC.sub.2, M.sub.P, M.sub.N and M.sub.S2 shown in FIG. 4, respectively (M.sub.C1 and M.sub.S1 are not shown here).
It is to be noted that M.sub.C2 and M.sub.P hold a same n-well 101 which is connected to V.sub.CC through an n+ diffusion layer 120 in common. M.sub.N and M.sub.S2 also hold a p-substrate connected to V.sub.SS in common in a similar manner as above. As it is understood from the foregoing, it not only produces the effect (i) described heretofore, but also produces a more advantageous layout area to connect the back gates of the MOS transistors to V.sub.CC and V.sub.SS as compared with connection of the same to the sources.
Although an n-well is formed in a p-substrate in the example shown here, a p-well may also be formed in an n-substrate conversely to the above. Otherwise, a triple well structure such as described in the ISSCC Digest of Technical Papers, pp. 248-249, Feb. 1989 may also be adopted.
Embodiment 3
FIG. 7 shows another method for realizing a switch and a resistance. The feature of the present embodiment is to use a current mirror circuit. Namely, MOS transistors M.sub.C2 and M.sub.C3 having the same threshold voltage form what is called a current mirror circuit, and when a current in proportion to a current source I.sub.0 flows in M.sub.C2 the impedance thereof is large. The same is also applied to M.sub.S2 and M.sub.S3. Thus, M.sub.C2 and M.sub.S2 may be regarded as having high resistance. Besides, a circuit CS composed of the current source I.sub.0 and M.sub.C3 and M.sub.S3 may be held in common by a plurality of logic gates.
The current mirror circuit is not limited to the circuit illustrated there, but also another circuit may be adopted. For example, a bipolar transistor may be used in place of the MOS transistor.
As described, various modifications are possible for the method for realizing a switch and a resistance. In a word, any means for applying a large current in a period where high-speed operation is required and for applying a small current in a period where low power consumption is required will suffice. The drawings will be illustrated with switches and resistances hereinafter as shown in FIG. 1 for the sake of simplicity.
Embodiment 4
The backgates of the MOS transistors of the inverter may be connected to other power supplies not limiting to V.sub.CC and V.sub.SS, and the voltages thereof may also be made variable. An example is shown in FIG. 8. The back gates of M.sub.P and M.sub.N are connected here to power supplies V.sub.WW and V.sub.BB, respectively, and backgate voltage values thereof are changed depending on time of operation and time of standby. As to V.sub.BB, in the period where high-speed operation is required, V.sub.BB is made shallow (or slightly positive in an extreme case), and V.sub.T of M.sub.N is lowered so as to make high-speed operation possible. In the period where low power consumption is required, V.sub.BB is made deep and V.sub.T of M.sub.N is raised, thereby to restrain the subthreshold current. With this, the effect (i) described previously is increased further. V.sub.BB has been described above, but the same is applied to V.sub.WW except that the polarity of the voltage is reversed. Incidentally, a back gate voltage generating circuit of this sort is described in ISSCC Digest of Technical Papers, pp. 254-255, Feb. 1985.
FIG. 9 shows an example of a device structure for realizing the circuit shown in FIG. 8. The triple well structure described previously is used here, in which an n-well 105 (a backgate of the P-channel MOS transistors) is connected to V.sub.WW through an n+ diffusion layer 120, and a p-well 103 (a backgate of the N-channel MOS transistors) is connected to V.sub.BB through a p+ diffusion layer 127.
This triple well structure has such an advantage that the backgate voltage can be set for every circuit because both the P-channel and the N-channel transistors can be incorporated in respective wells for every circuit. For example, when a circuit in an operating state and a circuit in a standby state are included in one LSI, it is possible to make the backgate voltage of the former shallow and the backgate voltage of the latter deep.
Embodiment 5
Next, a case of an inverter chain in which inverters are connected successively will be described. The principle will be described with respect to a case of two stages first for the sake of simplicity.
FIG. 10(A) shows a circuit diagram for CMOS inverters L.sub.1 and L.sub.2. Switches S.sub.Ci and S.sub.Si and resistances R.sub.Ci and R.sub.Si (i=1,2) are provided for each inverter at every stage.
In the high speed operation mode, all four switches are switched on, and V.sub.CC and V.sub.SS are applied directly to the inverters L.sub.1 and L.sub.2. High-speed operation is made possible by setting the threshold voltages of the MOS transistors of the inverters low. On the other hand, in the low power consumption mode, all of the switches are switched off, and the power is supplied to the inverters through resistances. Voltages V.sub.CL1 and V.sub.CL2 fall lower than V.sub.CC, and voltages V.sub.SL1 and V.sub.SL2 rise higher than V.sub.SS by voltage drops due to the fact that the subthreshold current flows through the resistances.
As to the inverter L.sub.1 at the first stage, the subthreshold current decreases by the mechanisms described previously (effects (i) and (ii)) in a similar manner as to the case of FIG. 1(A). However, the logic voltage swing of the output N.sub.1 of L.sub.1 is smaller than the logic voltage swing of the input signal IN as shown in FIG. 10(B). Namely, the voltage level of N.sub.1 shows V.sub.CL1 when IN is at a low level (=V.sub.SS), and the voltage level of N.sub.1 shows V.sub.SL1 when IN is at a high level (=V.sub.CC). Since N.sub.1 is the input to the inverter L.sub.2 at the second stage, it is desirable to, set the resistance values so that V.sub.CC >V.sub.CL1 >V.sub.CL2 and V.sub.SS <V.sub.SL1 <V.sub.SL2 are effected for the subthreshold current reduction of L.sub.2. With this, the subthreshold current decreases by the mechanisms described previously (effects (i) and (ii)) with respect to L.sub.2, too. When V.sub.CL1 =V.sub.CL2 and V.sub.SL1 =V.sub.SL2, the effect (i) is obtainable, but the effect (ii) is not obtainable.
Embodiment 6
The same embodiment is also applied to a multistage connection shown in FIG. 11(A), and it is recommended to effect V.sub.CC >V.sub.CL1 >V.sub.CL2 > . . . >V.sub.CLK and V.sub.SS <V.sub.SL1 <V.sub.SL2 < . . . <V.sub.SLK. Since the logic voltage swing becomes smaller step by step as shown in FIG. 11(B), however, the voltage swing is recovered by inserting a level conversion circuit appropriately. In the present example, a level conversion circuit LC is added after the inverter at a Kth stage so that the logic voltage swing of an output signal OUT becomes the same as that of an input signal IN. A level conversion circuit of this sort is described in Symposium on VLSI Circuits, Digest of Technical Papers, pp. 82-83, June 1992 for instance.
The level conversion circuit LC is not required at the time of high-speed operation. The reason is that, since all the switches are in an on-state, V.sub.CL1 =V.sub.CL2 = . . . =V.sub.CLK =V.sub.CC and V.sub.SL1 =V.sub.SL2 = . . . =V.sub.SLK =V.sub.SS and the logic voltage swing is not reduced. Thus, it is possible to avoid the delay by switching the switch S.sub.LC on so as to bypass the level conversion circuit at the time of high-speed operation.
Embodiment 7
FIG. 12(A) shows another example of an inverter chain of multistage connection. In the present example, all of switches S.sub.C and S.sub.S and resistances R.sub.C and R.sub.S are held in common by means of the inverters L.sub.1 to L.sub.K, and the voltages V.sub.CL and V.sub.SL are common to L.sub.1 to L.sub.K. Therefore, the subthreshold current reduction effect (i) described previously is obtainable, but the effect (ii) is not obtainable as described with reference to FIG. 10(A). Thus, the subthreshold current reduction effect becomes smaller than that in the previous embodiment.
On the other hand, however, there is such an advantage that the layout area of switches and resistances can be saved. Further, there is such a feature that the voltage levels of all the signals including input-output signals are the same and there is no reduction in the logic voltage swing as in the previous embodiment as shown in FIG. 12(B). As a result, there is such a merit that the level conversion circuit is not required, and a logic circuit such as a NAND circuit, a NOR circuit or the like is fabricated easily.
Embodiment 8
Next, a case where the present invention is applied to a general combinational logic circuit will be described.
For example, a combinational logic circuit shown in FIG. 13 is considered. In order to apply the present invention thereto, logic gates are grouped first as shown in FIG. 13. In the present example, 15 pieces of logic gates L.sub.1 to L.sub.15 are divided into three groups G.sub.1, G.sub.2 and G.sub.3. In grouping, it is arranged so that the output signals of logic gates included in the (i)th group are inputted only to logic gates of the (i+1)th group and therafter.
Next, switches and resistances are inserted between each logic gate group and the power supplies as shown in FIG. 14. Since the logic voltage swing of the output signal of the logic gate becomes smaller step by step similarly to the case shown in FIG. 11(B), level conversion circuit groups GC.sub.1 and GC.sub.2 are inserted as shown in FIG. 14 so as to recover the voltage swing. Besides, although it is not illustrated, the level conversion circuit groups GC.sub.1 and GC.sub.2 may be bypassed at the time of high-speed operation similarly to the case of FIG. 11(A).
One of the features of the present embodiment is that logic gates included in the same group hold the switch and the resistance in common. Speaking of the example shown in FIG. 13, three inverters included in the group G.sub.1 hold the switches S.sub.C1 and S.sub.S1 and the resistances R.sub.C1 and R.sub.S1 in common.
Another feature of the present embodiment is that the switch and the resistance are held in common by groups before and after the level conversion circuit. Namely, groups G.sub.1 and G.sub.K+1 hold the switches S.sub.C1 and S.sub.S1 and the resistances R.sub.C1 and R.sub.S1 in common, groups G.sub.2 and G.sub.K+2 hold the switches S.sub.C2 and S.sub.S2 and the resistances R.sub.C2 and R.sub.S2 in common, and groups G.sub.K and G.sub.2K hold the switches S.sub.CK and S.sub.SK and the resistances R.sub.CK and R.sub.SK in common, respectively.
It is possible to reduce the number of switches and resistances for the whole LSI so as to reduce the layout area by holding the switches and the resistances in common by a plurality of logic gates as described above.
Embodiment 9
FIG. 15 shows another embodiment of the present invention. What differs from embodiments described up to this point in the embodiment shown in FIG. 15 is that voltage limiters (voltage down converters and voltage up converters) VC.sub.1, VC.sub.2, . . . , VC.sub.K and VS.sub.1, VS.sub.2, . . . , VS.sub.K are used.
When low power consumption is required, switches T.sub.C1 to T.sub.CK and T.sub.S1 to T.sub.SK are changed over to the illustrated sides, and the power is supplied to the logic gate groups by means of voltage limiters. The voltage limiters VC.sub.1, VC.sub.2, . . . , VC.sub.K operate as voltage down converters on the side of the power supply voltage V.sub.CC, and generate almost stabilized internal voltages V.sub.CL1, V.sub.CL2, . . . , V.sub.CLK lower than V.sub.CC, respectively. On the other hand, VS.sub.1, VS.sub.2, . . . , VS.sub.K operate as voltage up converters on the side of ground V.sub.SS, and generate almost stabilized internal voltage V.sub.SL1, V.sub.SL2, . . . , V.sub.SLK higher than V.sub.SS, respectively. It is recommended to effect V.sub.CC >V.sub.CL1 >V.sub.CL2 > . . . >V.sub.CLK and V.sub.SS <V.sub.SL1 <V.sub.SL2 < . . . <V.sub.SLK for the generated voltages similarly to the embodiment described previously. Incidentally, a voltage limiter of this sort has been disclosed in JP-A-2-246516.
In contrast with the above, when high-speed operation is required, the switches are changed over to the side opposite to that which is illustrated and V.sub.CC and V.sub.SS are applied directly to the logic gate groups, thus making high-speed operation possible. Besides, since the voltage limiters become unnecessary at this time, the operation may be suspended.
Embodiments 10, 11
The circuits without feedback such as an inverter chain and a combinational logic circuit have been used in the embodiments up to this point, but the present invention is also applicable to a circuit with feedback. A case of a latch circuit obtained by combining two NAND gates shown in FIG. 16(A) will be described as an example.
FIG. 16(B) shows a circuit diagram. Switches S.sub.C1, S.sub.S1, S.sub.C2 and S.sub.S2 and resistances R.sub.C1, R.sub.S1, R.sub.C2 and R.sub.S2 are inserted among two NAND gates L.sub.1 and L.sub.2, the power supply V.sub.CC and the ground V.sub.SS, respectively. V.sub.CL1 and V.sub.CL2 fall lower than V.sub.CC, V.sub.SL1 and V.sub.SL2 rise higher than V.sub.SS, and the subthreshold current is reduced by the effect (i) described previously.
FIG. 17 shows an example in which the threshold voltage V.sub.T of four MOS transistors M.sub.P12, M.sub.P22, M.sub.N12 and M.sub.N22 used for latching information is made higher (more enhanced) than the threshold voltage of other MOS transistors M.sub.P11, M.sub.P21, M.sub.N11 and M.sub.N21 in order to further reduce the subthreshold current. Since the threshold voltage V.sub.T of other MOS transistors M.sub.P11, M.sub.P21, M.sub.N11 and M.sub.N21 to which the input signal is applied is left as it is (low), high-speed operation is possible. In this case, switches and resistances on the V.sub.SS side are not required because it is possible to cut off the current by means of transistors M.sub.N12 and M.sub.N22 on the V.sub.SS side having high threshold voltages.
Embodiments 12, 13
In the embodiments shown up to this point, it has been possible to reduce the subthreshold current whether the input signal is at a low level or at a high level. In a practical LSI, however, the level of a specific signal in the period where the subthreshold current reduction is required, e.g., in a standby state is often known in advance. In such cases, it is possible to reduce the subthreshold current by a simpler circuit.
FIG. 18 shows a circuit example of an inverter chain in which it is found that the input signal IN in a standby state is at a low level "L". Since IN is at a low level, nodes N.sub.1, N.sub.3, N.sub.5, . . . show a high level, and nodes N.sub.2, N.sub.4, N.sub.6, . . . show a low level. Thus, M.sub.P2, M.sub.P4, . . . among P-channel MOS transistors are in an off state, and M.sub.N1, M.sub.N3, . . . among N-channel MOS transistors are in an off state. It is sufficient to insert switches and resistances in the sources of these transistors in an off state because the subthreshold current flows in the transistor in the off state.
Further, there is no problem if the switch and the resistance are held in common by means of a plurality of inverters as shown in FIG. 19.
Although these embodiments are restricted by the fact that the level of the input signal has to be known, there is such an advantage that the subthreshold current can be reduced by a simple circuit. As it becomes apparent when FIGS. 18 and 19 are compared with FIG. 11(A), the number of switches and resistances is reduced and the level conversion circuit becomes unnecessary.
Embodiments 14, 15
In not only an inverter, but also in a logic gate such as a NAND gate and a NOR gate, it is possible to reduce the subthreshold current by a simpler circuit when the level of the input signal in a standby state is known.
FIG. 20 shows an example of a two-input NAND gate, and FIG. 21 shows an example of a two-input NOR gate. In the case when both input signals IN.sub.1 and IN.sub.2 are at a low level or when both are at a high level, these gates are substantially equivalent to the inverter. Consequently, the method described with reference to FIG. 18 and FIG. 19 is applicable. The problem exists in a case that one input is at a low level "L" and the other input is at a high level "H" as shown in the figures.
In the case of the NAND gate shown in FIG. 20, a P-channel MOS transistor M.sub.P12 and an N-channel MOS transistor M.sub.N11 are in an off state. Since the output OUT is at a high level, however, it is M.sub.N11 that the subthreshold current flows in. Thus, it is sufficient to insert a switch and a resistance on the V.sub.SS side. Conversely, in the case of a NOR gate shown in FIG. 21, it is a P-channel MOS transistor M.sub.P14 that the subthreshold current flows in. Thus, it is sufficient to insert a switch and a resistance on the V.sub.CC side.
FIG. 20 and FIG. 21 show examples in which the present invention is applied to two-input logic gates, but the present invention is also applicable in a similar manner to a logic gate having three inputs or more. Further, it is a matter of course that the switch and the resistance may be held in common with other logic gates.
Embodiment 16
FIG. 22 shows a circuit example in case it is comprehended that a clock CLK.sub.1 is at a low level and a clock CLK.sub.2 is at a high level in a standby state in a clocked inverter. Since both MOS transistors M.sub.P16 and M.sub.N16 are in an off state in this case, the output OUT shows a high impedance, and the voltage level thereof is determined by another circuit (not illustrated) connected to OUT. Since it is determined by the voltage level in which of the transistors M.sub.P16 or M.sub.N16 the subthreshold current flows, it is sufficient to insert switches and resistances on both of the V.sub.CC side and the V.sub.SS side in this case.
Embodiment 17
In the case of a general combinational logic circuit, it is possible to reduce the subthreshold current by a simpler circuit when the level of the input signal has been determined in advance. Description will be made by taking the combinational logic circuit shown in FIG. 23 as an example.
FIG. 23 shows a circuit structure example for the case where all of inputs IN.sub.1 to IN.sub.6 of this circuit are at a low level. As to inverters L.sub.1 to L.sub.3, L.sub.5 and L.sub.6, switches and resistances are inserted on the V.sub.SS side of L.sub.1 to L.sub.3 and the V.sub.CC side of L.sub.5 and L.sub.6 similarly to FIG. 18 and FIG. 19. Since the input signals are all at a low level, a NOR gate L.sub.7 is substantially equivalent to an inverter. Consequently, it is sufficient to insert a switch and a resistance on the V.sub.SS side. Since one of input signals is at a low level and the other is at a high level with respect to a NOR gate L.sub.4, a switch and a resistance are inserted on the V.sub.CC side similarly to FIG. 21. Of the eight NAND gates in the circuit group G, only the NAND gate L.sub.12 has all its three input signals at the high level and is equivalent to the inverter. Hence, the switch and the resistor, as indicated at MC, are inserted to the side of the voltage V.sub.CC. For the remaining NAND gates, the switch and the resistor, as indicated at MS, may be inserted to the side of the voltage V.sub.SS, as in FIG. 20, because the input signals have the low level and the high level.
As is apparent from the above description, it is sufficient to insert a switch and a resistance on the V.sub.SS side for a logic gate having an output at a high level and on the V.sub.CC side for a logic gate having an output at a low level. The layout area can be saved by holding these switches and resistances in common by a plurality of logic gates.
FIG. 24 is a diagram showing an example of the layout construction including a decoder circuit and a word driver circuit of a memory, e.g., a dynamic random access memory (DRAM). The group G1 (i.e., the decoder circuit) and the groups G21 to G24 (i.e., the word driver circuits) are the same circuit groups as the group G of FIG. 23. A memory cell MC1 is interposed between the circuit group G1 and the voltage V.sub.CC1 or the power source at the voltage V.sub.CC side, and a memory cell MC2 is interposed between the circuit groups G21 to G24 and the voltage V.sub.CC2 or the power source at the voltage V.sub.CC side. The memory cells MC1 and MC2 are composed of p-MOS transistors, which realize the switch and the resistor, as indicated at MC in FIG. 23, by their ON resistances and OFF resistances. Specifically, the ON resistances are those when the switch is turned ON in FIG. 23, and the OFF resistances are the resistance Rc when the switch is turned OFF in FIG. 23. On the other hand, letters MA designate a memory cell array having the memory cells MC arrayed two-dimensionally. If one W1 of the outputs W1 and W2 of the word driver circuit is selected, the signals of the memory cells are read out to paired data lines DT and DB and are amplified by sense amplifiers SA1 and SA2. This arrangement is repeated in the DRAM, and the transverse length of the memory array MA in the layout of FIG. 24 is substantially equal to the length of the groups G1 and G21 to G24. At this time, the memory cells MC1 and MC2 are shared by the numerous groups G1 and G21 to G24 and are arranged in the region below the sense amplifier region, as shown in FIG. 24. Thanks to this arrangement, the layout area can be reduced.
Embodiment 18
It is also possible to reduce the subthreshold current by a simpler circuit as for a circuit with feedback in case the level of a signal is known in advance. FIG. 25 shows an example in which the present invention is applied to a latch circuit shown in FIG. 16(A).
In a latch circuit of this sort, both input signals IN.sub.1 and IN.sub.2 are normally at a low level in a standby state, and one of output signals OUT.sub.1 and OUT.sub.2 is brought to a high level and the other is brought to a high level, thus holding information in one bit. FIG. 25 shows a circuit structure example in case it is comprehended that OUT.sub.1 is at a low level and OUT.sub.2 is at a high level. A NAND gate L.sub.1 is equivalent to an inverter since two input signals thereof are both at a high level, and a switch and a resistance are inserted on the V.sub.CC side similarly to FIG. 18 and FIG. 19. It is sufficient to insert a switch and a resistance on the V.sub.SS side similarly to FIG. 20 for a NAND gate L.sub.2 since one of input signals thereof is at a low level and the other is at a high level. It is a matter of course that these switches and resistances may be held in common with other logic gates.
Embodiment 19
FIG. 26 shows an example in which the present invention is applied to a well known data output buffer in a memory LSI or the like. In a standby state, an output enable signal OE is at a low level, outputs of NAND gates L.sub.21 and L.sub.22 are at a high level and an output of an inverter L.sub.23 is at a low level. Accordingly, two MOS transistors M.sub.P20 and M.sub.N20 constituting an output stage L.sub.24 are both in an off state, and an output DOUT has a high impedance.
As to logic gates L.sub.21 to L.sub.23, it is sufficient to insert a switch and a resistance on the V.sub.SS side or the V.sub.CC side in accordance with the criteria stated in the description with reference to FIG. 23. As to an output stage L.sub.24, it is sufficient to insert switches and resistances on both the V.sub.CC side and the V.sub.SS side in a similar manner to the case of the clocked inverter shown in FIG. 22.
Embodiment 20
FIG. 27 shows an example in which the present invention is applied to a well known data input buffer in a memory LSI or the like. In FIG. 27, SB represents a signal which shows a high level in a standby state. Outputs of inverters L.sub.31 and L.sub.32 can be used as .phi..sub.S and .phi..sub.C for controlling switches respectively as shown in FIG. 4 and FIG. 7. L.sub.33 represents a NAND gate and receives .phi..sub.S and a data input signal D.sub.IN. Since .phi..sub.S is at a low level in a standby state, the output of L.sub.33 shows a high level irrespective of D.sub.IN. Thus, an output d.sub.IN of an inverter L.sub.34 shows a low level. On the other hand, since SB is at a low level in the operating state, the output d.sub.IN follows the input D.sub.IN.
Concerning the NAND gates L.sub.33 and the inverter L.sub.34, the subthreshold current can be reduced by inserting switches and resistances on the V.sub.SS side and the V.sub.CC side, respectively. Although such techniques cannot be applied to the inverters L.sub.31 and L.sub.32, the subthreshold current can be reduced by enhancing the threshold voltages of the MOS transistors. Since high-speed performance is not required in many cases for changing over the standby state to and from the operating state, there is no problem in using MOS transistors having enhanced threshold voltages.
A data input buffer has been described above, but the same is applied to an input buffer for an address signal and other signals.
The embodiments illustrated in FIGS. 18 to 26 have a merit that the subthreshold current can be reduced by a simple circuit, but on the other hand, these embodiments are restricted in that they are unapplicable unless the signal level in a period where subthreshold current reduction is required, e.g., in a standby state, is known. Accordingly, it is desirable to fix the levels of as many nodes as possible in the LSI to known levels. It is possible to have the level of the signal d.sub.IN fixed to a low level by using a circuit such as the input buffer shown in FIG. 27 as means for the above. As another method for deciding upon the level, there is also a method wherein the data input terminal D.sub.IN is specified to be a low level (or a high level) in case of a standby state.
Although the foregoing description has been directed to the data input buffers, similar description can be applied to an input signal for an address signal or the like.
The embodiments illustrated in FIG. 18 to FIG. 27 are suitable for application to a memory LSI. Because, in the memory LSI, there are comparatively many nodes in which either a high level or a low level is known at time of standby, the levels of most nodes can be fixed by using the input buffer shown in FIG. 27.
The reference examples of FIGS. 26 and 27 can be used not only as the input/output circuit for the external terminals of the LSI chip but also as the driver/receiver for the internal bus of the microprocessor, for example.
In the random logic LSI such as a microprocessor, it is effective to fix the voltage of a troublesome node forcibly by fixing the output of an internal register or by adding a logic such as a flip-flop having a resetting function. FIG. 41 shows an embodiment of the structure of the latch capable of fixing an output. This circuit is simplified by replacing the inverter in the ordinary latch by a NAND circuit. As illustrated in FIG. 42, the latch operates as an ordinary one while the signal .phi..sub.S is at the high level, and the level of the output signal Q is fixed to the high level while the signal .phi..sub.S is at the low level (or in a sleep mode). Here, the sleep mode is one for interrupting the operation of the entire LSI or the circuit block unit so as to reduce the current dissipation. Incidentally, the subthreshold current of the latch itself can be reduced in the sleep mode if the signal .phi.t is at the low level whereas the signal .phi.b is at the high level. If this latch is used, the node N.sub.41 is forcibly set to the high level because the signal .phi..sub.S takes the low level, so that the data are erased from the register in the sleep mode. However, this erasure raises no problem even in the use, in which the necessary data in the CPU are saved to the main memory to open the reset state again after the sleep mode, that is, for the resume function in which a notebook personal computer is held in the standby state if it receives no input for a predetermined period. FIG. 43 shows another embodiment of the latch capable of fixing the output forcibly. As shown in FIG. 44, this circuit also acts as an ordinary latch while the signal .phi..sub.S is at the high level and fixes the level of the output signal Q to the high level while the signal .phi..sub.S is at the low level. This latch can retain the data even in the sleep mode because the node N.sub.41 is not influenced even if the signal .phi..sub.S takes the low level. The operation can be reopened from the state before the sleep mode after this sleep mode is released and can establish the sleep mode even while the CPU is executing its task. Thus, this embodiment is suitable for the case in which the operation is resumed after a relatively short time from the sleep mode.
Embodiment 21
The embodiments in which the present invention is applied to a CMOS circuit have been described so far, but the present invention is also applicable to a circuit composed of MOS transistors having a single polarity. FIG. 28 shows an example of a circuit composed of N-channel MOS transistors only. In FIG. 28, PC represents a precharge signal, and IN.sub.1 and IN.sub.2 represent input signals.
At the time of standby, i.e., in a precharge state, PC is at a high level and IN.sub.1 and IN.sub.2 are at a low level, and the output OUT is precharged to a high level (=V.sub.CC -V.sub.T). At the time of operation, IN.sub.1 and IN.sub.2 are brought to a high level or remain at a low level after PC is brought to a low level. When at least one of IN.sub.1 and IN.sub.2 is brought to a high level, OUT is brought to a low level. When both of IN.sub.1 and IN.sub.2 remain at a low level, OUT is left (as is) at a high level. Namely, this circuit outputs the NOR of IN.sub.1 and IN.sub.2.
In this circuit, M.sub.N41 and M.sub.N42 on the V.sub.SS side are those transistors that are in an off state at time of standby, and the subthreshold current flows in these transistors. Accordingly, in order to apply the present invention to this circuit, it is sufficient to insert a switch and a resistance on the V.sub.SS side as shown in the figure. They are not required on the V.sub.CC side.
Incidentally, in the LSI for complicated operations such as a random logic LSI, the logic (or voltage) state of each node in the chip in the standby state, for example, is determined by the design automation (DA) method so that the position to insert the aforementioned switch and resistor can be automatically determined by the DA.
As described above, the present invention is very effective for achieving low power consumption of MOS transistor circuits and a semiconductor integrated circuit composed of the same. The demand for low power consumption of a semiconductor integrated circuit is great, and recently a microprocessor system having a low power backup mode was described in the Sep. 2, 1991, issue of Nikkei Electronics, pp. 106-111, for instance. In the backup mode, the clock is stopped and the supply of power to unnecessary parts thereof is suspended, thereby reducing power consumption. However, no consideration is given to the extent of reduction of the subthreshold current. These processor systems operate at 3.3 to 5 V and can use transistors having a sufficiently high threshold voltage so that the subthreshold current is too low to raise any problem. However, if the operating voltage becomes as low as 2 or 1.5 V so that the threshold voltage has to be dropped, the excessive subthreshold current cannot be reduced any more by the method of the prior art using the CMOS circuit. When the present invention is applied to, for example, a resuming circuit to which the power is supplied even in the backup mode, lower power consumption can be realized.
Embodiment 22
In the examples described above, there are such problems that the logic voltage swing is reduced with the increase of the number of stages, and a more or less complicated design is required for the case where the voltage level of an input signal is unknown. FIG. 29 shows a circuit for solving these problems, in which the switches are switched on so as to perform normal high-speed operation in a period required until the logic output is settled as described so far. In other periods than the above, a subthreshold current passage of a logic circuit is cut off by switching off the switches. However, since a supply passage of the power supply voltage is interrupted when the switches are switched off, the output of the logic circuit becomes floating, and the logic output is no longer settled. Thus, it is a feature that a sort of latch circuit (a level-hold circuit) for holding a voltage level is provided at the output thereof. If a transistor having a high threshold voltage or the like is used for the level-hold circuit, the subthreshold current of the level-hold circuit becomes negligibly small, thus making it possible to make the subthreshold current small on the whole. The delay time is affected little by the level-hold circuit, and is determined by the logic circuit. Even if a high-speed circuit having large driving capability is used in the logic circuit, the consuming current is only the current flowing through the level-hold circuit since no current flows through the logic circuit in a standby state. The level-hold circuit may have a small driving capability since it only holds the output, thus making it possible to reduce the current consumption. Since the output of the logic circuit is held by the level-hold circuit even if the switches are switched off, there is no possibility of inversion of the output and the operation is stabilized. Thus, a semiconductor device operating stably with low power consumption and at a high speed can be realized. According to the present embodiment, since the voltage level is always guaranteed at a constant value by means of the level-hold circuit, the logic voltage swing will never be decreased with the increase of the number of the logic stages. Further, the present embodiment is effective independent of the logic input.
The present embodiment will be described further with reference to FIG. 29. A logic circuit LC is connected to a power supply line VHH at a high potential and a power supply line VLL at a low potential through switches SWH and SWL. Here, it is also possible to have VHH and VLL correspond to V.sub.CC and V.sub.SS which have been heretofore described, respectively. A level-hold circuit LH is connected to an output terminal OUT of the logic circuit LC. Switches SWH and SWL are controlled by a control pulse CK so as to be switched on and off at the same time. The logic circuit LC is composed of a logic gate such as an inverter, a NAND circuit, a NOR circuit, a flip-flop circuit, or a plurality of combinations thereof. The level-hold circuit LH can be composed of a positive feedback circuit.
The operation of the logic circuit LC is performed with the switches SWH and SWL on. After an output OUT in accordance with an input IN of the logic circuit LC is settled or determined, the switches SWH and SWL are switched off, a current passage from VHH to V.sub.SS through the logic circuit LC is cut off, and the output of the logic circuit LC is held by the level-hold circuit LH.
The delay time of a circuit is affected little by the level-hold circuit LH, and is determined by the logic circuit LC. It is possible to perform a high-speed operation having a short delay time by using a circuit having large driving capability for the logic circuit LC. For example, in a standby state, since no current flows through the logic circuit LC, the consuming current is the only one that flows through the level-hold circuit LH. Since a level-hold circuit LH having small driving capability will suffice, the consuming current can be made small. Moreover, since the output OUT of the logic circuit LC is maintained by means of the level-hold circuit LH, there is no possibility of malfunction. Hence, a circuit which performs stabilized operation with low power consumption and at a high speed can be realized.
Embodiment 23
An embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. 30. An NMOS transistor MN1 and a PMOS transistor MP1 operate as the switches SWL and SWH shown in FIG. 29, respectively. In order to reduce a leakage current when the switches are switched off, the threshold voltages of the transistors MN1 and MP1 are made sufficiently high. Their channel width/length ratios are determined so that on state resistances do not become large. A control pulse CK is inputted to the gate of the NMOS transistor MN1 and a control pulse CKB is inputted to the date of the PMOS transistor MP1. CKB represents a complementary signal of CK. A CMOS inverter INV composed of an NMOS transistor MN2 and a PMOS transistor MP2 is connected to MN1 and MP1. In order to increase the driving capability in low voltage operation, the threshold voltages of the transistors MN2 and MP2 are made low. The level-hold circuit LH composed of NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4 is connected to an output terminal OUT of the inverter INV. In order to reduce a penetrating current while holding the output, the threshold voltages of the transistors MN3, MN4, MP3 and MP4 are made sufficiently high, and the channel width/length ratios thereof are made sufficiently small. An example of numeric values of the power supply voltage and the threshold voltages will be shown. VLL is set to the ground potential at 0 V, and VHH is set to the external power supply voltage at 1 V. The threshold voltages of the NMOS transistors are set to 0.2 V for MN2 and to 0.4 V for MN1, MN3 and MN4. The threshold voltages of the PMOS transistors are set to -0.2 V for MP2 and to -0.4 V for MP1, MP3 and MP4.
The operation will be described with reference to a timing chart shown in FIG. 31. First, the control pulse CK is raised to VHH, CKB is lowered to VLL, transistors MN1 and MP1 are turned on, and the inverter INV is connected to VHH and VLL. When the input signal IN is raised to VHH from VLL, MP2 is turned off and MN2 is turned on, and the output OUT is discharged from VHH to VLL. The transistor MN2 starts conduction in a saturated region, and the value of the current flowing in MN2 is determined by the voltage between the gate (input terminal IN) and the source (node NL). Since the transistor MN1 is provided between the node NL and VLL, the potential of the node NL rises temporarily by the on-state resistance of MN1 and the current flowing from MN2. Since the gate of MN1 is at VHH, however, a design is possible so that the on-state resistance becomes sufficiently small even if the threshold voltage is high, thus reducing the influence upon the delay time. Further, MN4 is in an off state and MP4 is in an on state so that the level-hold circuit LH holds the output OUT at VHH when the output OUT is inverted to VLL. As a result, a current flows from VHH to VLL through MP4 and MN2 since MN2 is turned on, but the influence exerted on the delay time and the current consumption is small by designing the driving capability of MP4 small as compared with that of MN2. When the output OUT lowers, MN3 is turned off and MP3 is turned on, a node NLH in the level-hold circuit is inverted from VLL to VHH, MN4 is turned on and MP4 is turned off, and the level-hold circuit LH operates so as to hold the output OUT at VLL, thus preventing current from flowing. MP2 is in an off state since the gate and the source are both at VHH, but the leakage current is large and current flows through the inverter INV since the threshold voltage is low. Then, the control pulse CK is lowered to VLL, CKB is raised to VHH, and the transistors MN1 and MP1 are turned off, thus isolating the inverter INV from VHH and VLL. At this time, MN1 and MP1 are turned off completely because the gate and the source thereof are at equal potential and the threshold voltage is high. The output OUT is held at VHH by positive feedback of the level-hold circuit LH. Since the NMOS transistor MN2 is in an on state, the node NL is held at VLL. On the other hand, the voltage of a node NH starts to drop due to the leakage current of the PMOS transistor MP2 from the node NH to the output terminal OUT. Then, the source potential drops lower than the gate potential, and MP2 is turned off completely. As a result, the current of the inverter INV does not flow in a standby state. Further, before the input signal IN changes, the control pulse CK is raised to VHH, CKB is lowered to VLL, and the transistors MN1 and MP1 are turned on, thus bringing the node NH to VHH. Since the input IN is inverted from VHH to VLL, the output OUT is inverted from VLL to VHH.
It is desirable that the level-hold circuit LH follows the output OUT quickly so that the period of time when the current flows through the inverter INV and the level-hold circuit LH becomes shorter. Consequently, the inverter INV and the level-hold circuit LH are arranged close to each other so as to reduce the wiring delay.
As is apparent from the present embodiment, when the threshold voltage of the MOS transistor used as the switch is brought to approximately 0.4 V or higher which has been deemed to be required to reduce the subthreshold current, it is possible to lower the threshold voltage of the MOS transistor in the logic circuit without increasing the current flow in a standby state. Even if the operating voltage is lowered to 1 V or lower, it is possible to set the threshold voltage of the MOS transistor to 0.25 V or below, thereby to secure driving capability. Thus, low power consumption by lowering of voltage can be realized. Further, it is possible to realize performance improvement by the scaling down of elements based on a conventional scaling law. Moreover, since the structure is the same as a conventional CMOS logic circuit except that the switch and the level-hold circuit are loaded, the same design techniques as before can be used.
Embodiment 24
FIG. 32 shows an embodiment in which the present invention is applied to a CMOS inverter chain. An inverter chain can be realized by a multistage connection of two switches and also a level-hold circuit provided on the inverter at one stage as shown in FIG. 30. Also, by the present embodiment, the switches and level-hold circuit are held in common by a plurality of inverters so as to reduce the number of elements and the area. A case of an inverter chain with four stages is taken as an example here, but a case including a different number of stages is also structured in a similar manner. Four inverters INV1, INV2, INV3 and INV4 are cascaded. The level-hold circuit LH is connected to the output terminal OUT of the inverter INV4 at the last stage. Each inverter is composed of one PMOS transistor and NMOS transistor similarly to the INV shown in FIG. 30. The transistor size in respective inverters may either be the same as or different from each other. With a cascaded driver, it is also possible to increase the channel width in the order of INV1, INV2, INV3 and INV4 at a constant interstage ratio while keeping the channel length the same. The sources of the PMOS transistors of respective inverters are connected to the node NH, and the sources of the NMOS transistors thereof are connected to the node NL. A switch SWL is provided between the node NL and the power supply VLL on a low level, and a switch SWH is provided between the node NH and the power supply VHH on a high level. The switches SWL and SWH are controlled by a control pulse CK and switched on and off at the same time. As shown in FIG. 30, the switch SWL is realized by an NMOS transistor, and the switch SWH is realized by a PMOS transistor applied with a complementary signal of CK at the gate thereof.
The operation of the inverter chain is performed with the switches SWL and SWH on. For example, when the output IN is inverted from the low level VLL to the high level VHH, a node N1 is inverted from VHH to VLL by means of the inverter INV1, a node N2 is inverted from VLL to VHH by means of the inverter INV2, a node N3 is inverted from VHH to VLL by means of INV3, and the output OUT is inverted from VLL to VHH by means of INV4. When OUT is at VHH, the level-hold circuit LH is operated so as to hold OUT at VHH. In a standby state, the current passage from VHH to VLL through the inverters is cut off by switching off the switches SWL and SWH.
It is sufficient to provide a level-hold circuit at the output terminal thereof only by handling the inverter chain collectively as one logic circuit as in the present embodiment. Further, the switches SWL and SWH can be held in common by a plurality of inverters. The sizes of the switches SWL and SWH are determined by the magnitude of the peak current applied. The peak of the current sum flowing in a plurality of inverters becomes smaller than the sum of peak currents in respective inverters. For example, when an inverter chain is formed assuming an interstage ratio at 3, the peak of the current sum becomes almost equal to the peak current at the last stage. Accordingly, a small area of the switch will suffice when the switch is held in common by a plurality of inverters as compared to a case where a switch is provided for every inverter.
Embodiment 25
FIG. 33 shows another embodiment in which the present invention is applied to an inverter chain. A case of an inverter chain at four stages is taken as an example similarly to FIG. 32, but the inverter chain is structured similarly in the case of another number of stages, too. Inverters INV1, INV2, INV3 and INV4 are connected in series. Level-hold circuits LH3 and LH4 are connected to a node N3 which is an output terminal of the inverter INV3 and an input terminal of the inverter INV4 and to an output terminal OUT of INV4, respectively. Each inverter is composed of one each of a PMOS transistor and an NMOS transistor similarly to the INV shown in FIG. 30. Odd-numbered inverters INV1 and INV3 are connected to nodes NL1 and NH1, and even-numbered inverters INV2 and INV4 are connected to nodes NL2 and NH2. Switches SWL1 and SWL2 are provided between the nodes NL1, NL2 and the power supply VLL on a low level side, respectively, and switches SWH1 and SWH2 are provided between the nodes NH1, NH2 and the power supply VHH on a high level side, respectively. The switches SWL1, SWL2 and SWH1, SWH2 are controlled by a control pulse CK, and switched on and off at the same time.
The operation of the inverters is performed with the switches SWL1, SWL2, SWH1 and SWH2 on. For example, when the input IN is inverted from the low level VLL to the high level VHH, a node N1 is inverted from VHH to VLL, a node N2 is inverted from VLL to VHH, a node N3 is inverted from VHH to VLL, and the output terminal OUT is inverted from VLL to VHH by means of INV4 in consecutive order. When N3 is at VLL, the level-hold circuit LH3 operates so as to hold N3 at VLL. Further, when OUT is at VHH, the level-hold circuit LH operates so as to hold OUT at VHH. For example, in a standby state, the current passages from VHH to VLL through the inverters are cut off by switching off the switches SWL1, SWL2, SWH1 and SWH2. At this time, since the node N3 is held at a low level VLL by the level-hold circuit LH3, the node NL1 is also held at VLL through the inverter INV3. Furthermore, the node N1 is held at VLL through the inverter INV1. Similarly, nodes NH2 and N2 are also held at VHH because the output terminal OUT is held at the high level VHH by means of the level-hold circuit LH4. Thus, the nodes connecting the inverters are held at either VHH or VLL.
As described above, the nodes N1, N2 and N3 among the inverters are all held at either a high level or a low level by providing two sets of switches, connecting odd-numbered inverters and even-numbered inverters to different switches and connecting the level-hold circuits to any output terminal of odd-numbered inverters and any output terminal of even-numbered inverters, respectively. Since the input to each inverter is not brought to an intermediate level even if the standby state continues for a long time, operation is stabilized, and neither data inversion nor DC current flow does not occur when the switches are turned on.
In the embodiments shown in FIGS. 30-33, the present invention is applied to a CMOS inverter and an inverter chain. However, the present invention is not limited to these embodiments described so far, but also includes other embodiments not departing from the gist that stabilized operation is performed with low power consumption and at a high speed by loading a logic circuit with a switch and a level-hold circuit.
Embodiment 26
For example, another embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. 34. In the embodiment shown in FIG. 30, transistors MN1 and MP1 operating as switches are provided between the CMOS inverter INV and power supplies VLL and VHH. In contrast to the above, these transistors are provided between an NMOS transistor and a PMOS transistor in the present embodiment.
Two NMOS transistors MN2 and MN1 and two PMOS transistors MP1 and MP2 are connected in series between the low level power supply VLL and the high level power supply VHH. The NMOS transistor MN1 and the PMOS transistor MP1 operate as switches. In order to reduce the leak current when those transistors are turned off, the threshold voltages of the transistors MN1 and MP1 are made high. A control pulse CK is inputted to the gate of the NMOS transistor MN1 and a control pulse CKB of a complementary signal of CK is inputted to the gate of the PMOS transistor MP1. The NMOS transistor MN2 and the PMOS transistor MP2 are connected to the input terminal IN at the gates thereof, and operate as CMOS inverter. In order to increase the driving capability in low voltage operation, the threshold voltages of the transistors MN1 and MP1 are made low. A level-hold circuit LH structured similarly to FIG. 30 is connected to the output terminal OUT.
The operation is performed in a similar manner as the embodiment shown in FIG. 30. The transistors MN1 and MP1 are turned on by control pulses CK and CKB, thus having MN2 and MP2 operate as a CMOS inverter. For example, when the input IN is inverted from the low level VLL to the high level VHH, the transistor MN2 which has been in an off state starts to conduct and operates in a saturated region. At this time, the current value of MN2 is determined by the gate-source voltage. Since the transistor MN1 is provided between MN2 and the output terminal OUT, the on-state resistance of MN1 is connected to the drain of MN2. As a result, the influence of the on-state resistance of MN1 exerted upon the current value of MN2 is small. After the output OUT is determined, the transistors MN1 and MP1 are turned off, thereby to prevent further current flow and maintain the output OUT by means of the level-hold circuit LH.
When switches are inserted on the output terminal side of the logic circuit as in the present embodiment, it is impossible to hold the switches in common by means of a plurality of logic gates, but the influence of the on-state resistance of the switches is small. In case the transistors used as switches are the same, the delay time is reduced as compared with a case where the switches are provided on the power supply side of the logic circuit as in the embodiment shown in FIG. 30. Otherwise, if it is designed so that the delay time becomes equal, the channel width/length ratio of the transistor used as a switch may be reduced, thus enabling a reduction in area.
Embodiment 27
FIG. 35 shows another structure example of the level-hold circuit. A case in which this level-hold circuit is replaced with a level-hold circuit composed of NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4 in the embodiment shown in FIG. 30 will be described.
This level-hold circuit is composed of NMOS transistors MN3, MN4 and MN5 and PMOS transistors MP3, MP4 and MP5. In order to reduce the leakage current in a standby state, the threshold voltages of respective transistors are made high. For example, it is set to 0.4 V for the NMOS transistor and -0.4 V for the PMOS transistor. MN3 and MP3 form as inverter, and MN4, MN5, MP4 and MP5 form a clocked inverter. A control pulse CKB is inputted to the gate of MN5, and a control pulse CK is inputted to the gate of MP5. The operation timing is the same as the case when the level-hold circuit LH shown in FIG. 30 is used as shown in FIG. 31. The control pulse CK is raised to the high level VHH and CKB is lowered to the low level VLL so as to operate the inverter INV. At this time, the transistors MN5 and MP5 are turned off in the level-hold circuit. As a result, when the output OUT is inverted, current does not flow through the inverter INV and the level-hold circuit, and delay time and current consumption may be reduced. In a standby state, the control pulse CK is lowered to the low level VLL and CKB is raised to the high level VHH, and the inverter INV is isolated from power supplies VLL and VHH. At this time, the transistors MN5 and MP5 are turned on in the level-hold circuit, and the output OUT is held by positive feedback.
By forming the level-hold circuit by the combination of an inverter and a clocked inverter as described above, the number of transistors is increased by two, but the logic circuit and the level-hold circuit do no longer conflict with each other, and the delay time and the current consumption may be reduced. Further, the driving capability of the level-hold circuit may also be increased, and there is no possibility that the output fluctuates even when the leakage current through the output terminal is large, thus making stabilized operation possible.
Recently, for microprocessors operating at 3.3 V to 5 V, the application of the clock to the circuit, which is unnecessary in the low-power backup mode (or sleep mode), is interrupted to reduce the charging/discharging current so as to reduce the power consumption, as has been described hereinbefore. In the present reference example, as shown in FIG. 51, all the transistors MP11 and MN11, and MP12 and MN12 are turned OFF by lowering both the clocks CK1t and CK2t in the sleep mode, to shut the through currents through the logic circuits LC1 and LC2. As a result, the effect of reducing the sub-threshold current is higher in the sleep mode than in the operation mode.
In the reference examples of FIGS. 29 to 35, the main switch is controlled by the single timing signal CK (or CKB). In case, however, a plurality of circuit blocks are in the LSI, the sub-threshold current can be further reduced by controlling the individual power switches at different timings. This method is shown as embodiments of the present invention in FIGS. 36 to 40. Incidentally, the method can be used not only for reducing the sub-threshold current but also for reducing the current at an ordinary non-transient operation time.
Embodiment 1 of Power Switch Control
FIG. 36 shows an example of the control of power switches of a plurality of circuit blocks according to a first embodiment. Letters IN designate a representative signal to be input to the LSI chip. For the operation period, the logic circuit blocks are sequentially operated in the order of LG1, LG2 and LG3 in response to signal IN. Each logic circuit block is constructed of the logic circuit LC and the level hold circuit LH, as has been described with reference to FIGS. 29 to 35. Letters SWH1 to SWH3 designate power switches interposed between the voltage V.sub.CC and the logic circuit blocks LG1, LG2 and LG3, and letters SWL1 to SWL3 designate power switched interposed between the voltage VSS and the logic circuit blocks LG1, LG2 and LG3. FIG. 36 is characterized in that the control of the power switches SWH1 and SWL1 of the logic circuit block LG1 is carried out in response to a sleep-mode/normal-operation-mode switching signal SLP whereas the control of the logic circuit blocks LG2, LG3 and so on for the succeeding stages is carried out by controlling the power switches SWH2 to SWH3 by means of KH1 to KH3 for sensing the operations of the preceding stages. Although not shown, moreover, there may be provided means for detecting the operations of the succeeding stages to turn OFF the power switches of the individual logic circuit blocks, or means having a timer for turning OFF the power switches automatically after a constant time period. Even if the power switches are turned OFF, the data is held by the level hold circuits in the individual logic circuit blocks. Since the power switches of the individual logic circuit blocks are not turned ON before the logic circuit blocks are operated, the sub-threshold current of the entire LSI is reduced. Moreover, the shift from the sleep mode to the normal operation mode can be effected within a short time period because only the first stage may be reset (or set). Incidentally, in the logic circuit block LG1, the means KH1 detects the change of the output of the logic circuit LC, as shown. Alternatively, it may detect the change of the internal node of the logic circuit LC. Moreover, the means KH1 may activate not only the power switch of the logic circuit block LG2 at the next stage but also the power switch of the logic circuit block LG3 at the subsequent stage.
An example of the operation of FIG. 36 is shown in FIG. 37. In this example, the sleep mode is established when the signal SLP is at the high level, and the operation mode is established when the same is at the low level. Now, at time t1, the signal SLP is switched from the high level to the low level so that the mode is switched from the sleep state to the normal operation state. As a result, the power switches SWH1 and SWL1 of the first stage logic circuit block LG1 are turned ON. At time t2, the signal IN is changed to operate the logic circuit block LG1. This time period of t2-t1 can be shortened because only the switches SWH1 and SWL1 may be turned ON, as described above. Incidentally, these switches SWH1 and SWL1 are always active while the signal SLP is at the low level. On the other hand, the remaining power switches corresponding to the circuit blocks are turned ON according to the flow of signals. Specifically, at time t3, the output .phi.G1 of the logic circuit block LG1 is switched. This is detected by the means KH1 to switch a signal .phi.1 so that the power switches SWH2 and SWL2 of the logic circuit block LG2 of the subsequent stage are turned ON. As a result, the logic circuit block LG2 is operated to have its output .phi.G2 switched at time t4. This change is detected by the means KH2 to switch a signal .phi.2 so that the power switches SWH3 and SWL3 of the logic circuit block LG3 are turned ON. As a result, the logic circuit block LG3 is operated. Here, if the signal .phi.G2 is switched at time t4 so that the logic circuit block LG3 at the subsequent stage begins its operation, the logic circuit block LG2 may have its output level held. At time t5, therefore, the signal .phi.1 can be switched to turn OFF the power switches. This detection of time t5 may be fed back from the output of the subsequent stage circuit, as described above, or supported by a timer. For the purposes of the description of the following power switch control embodiments, similar operations are presumed to be carried out.
A modification of the control of the power switches shown in FIG. 36 is set forth in FIG. 38. In FIG. 36, the flow of signals for turning ON the power switches proceeds from left to right, as shown in the figure. In FIG. 38, however, the signal flow direction is from right to left. Specifically, .phi.4 is fed back to switches SWH3 and SWL3 to turn off logic circuit block LG3. This is detected by means KH3, and the signal .phi.3 is fed back to the switches SWH2 and SWL2. It follows that once circuit block LG2 is turned on, the detector KH2 provides an output signal .phi.2 that is fed back to switches SWH1 and SWL1 to continue the propagation of the signal flow in the direction from right to left, with respect to the circuit layout shown in the figure.
Embodiment 2 of Power Switch Control
FIG. 39 is a diagram showing a control example of the power switches in the LSI which operate in synchronism with a clock in accordance with a second embodiment of the power switch control of the present invention. This embodiment is exemplified by an LSI chip that is operated in synchronism with the clock signal CLK and such that one operation of the LSI is completed by clocks of n (wherein n=4) cycles. In the chip, the circuit blocks LG1 to LG4 are sequentially operated in response to the input IN in synchronism with the clock signal CLK. Each circuit block is constructed of a logic circuit and a level hold circuit as in the foregoing reference examples. This example is characterized in that the power line switches SWH1 to SWL4 are controlled by the power line switch control circuit SV in response to the clock signal CLK thereby to suppress the sub-threshold current. Since each circuit block operates for only one of the n cycles, the power line switches may be sequentially turned ON or OFF in accordance with the flow of signals in the chip. As a result, the circuit blocks, in which the power switches are active, can be suppressed to about one n-th.
An example of the operation of FIG. 39 is shown in FIG. 40. In this example, one cycle of the LSI chip is operated for the four clocks of the clock signal CLK. In response to the breakage of the clock CLK of the first cycle, the signal IN at this time is fetched to switch the signal .phi.1 so that the switches SWH1 and SWL1 are turned ON to operate the logic circuit block LG1. Before and after (slightly before, as shown) the output .phi.G1 of the logic circuit block LG1 is switched, the output .phi.2 is switched in response to the transition to the next CLK so that the switches SWH2 and SWL2 are turned ON to operate the logic circuit block LG2. When the signal .phi.G1 is switched to start the operation of the logic circuit block LG2, the logic circuit block LG1 may hold the output level. Thus, the switches SWH1 and SWL1 are turned OFF at a suitable timing (in response to the rise of the next clock CLK), to hold the signals by the level hold circuit in the logic circuit block LG1. From then on, the power switches are controlled until the signal .phi.4. In each circuit block in the LSI chip, therefore, the power switches can be independently turned ON/OFF in response to the clock CLK, so that the operation can reduce the current consumption caused by the sub-threshold current.
The reference examples of FIGS. 18 to 27 are premised by the fact that the input signals are at specific levels. In case the input levels are different from the intended values, the sub-threshold current reducing effect is lowered. When the power is made, for example, the input signal levels are not fixed, but a large sub-threshold current may flow. In order to prevent this, the power lines may desirably be equipped with switches, as shown in FIGS. 55 to 59, according to the embodiments of the present invention.
Embodiment 3 of Power Switch Control
FIG. 41 is a diagram showing a first control example of the power switch according to a third embodiment of the present invention. Letter K1 designates the logic gate groups which are shown in FIGS. 18 to 27. A power switch SCC is controlled by a control circuit SV. This circuit SV includes a level detecting circuit LD1 for detecting the level of the externally applied power VCC and a level detecting circuit LD2 for detecting the level of the external input signal IN, which are operative to generate output signals .phi.VC and .phi.SB, respectively. Letters LL designate a logic circuit for generating a switch control signal .phi.1 in response to the signals .phi.VC and .phi.SB. Specifically, at the rise of the power VCC, the switch SCC is turned ON by detecting that the power VCC reaches a predetermined level and that the input signal IN takes a specific level (i.e., the level for reducing the sub-threshold current of the logic gate group K1). At the switching time of the power VCC, the switch is turned OFF by detecting the drop of the level of the power VCC.
An example of the operation of the LSI of FIG. 41 is shown in FIG. 42. When the power VCC is made, the potential is raised to a level VC.alpha., for example. Then, the level detecting circuit LD1 operates to switch the output signal .phi.VC from the low level to the high level in this example. Next, when the input signal IN takes such a specific signal level (e.g., the high level) as has a high effect for reducing the sub-threshold current of the logic gate group K1, that is, when the level exceeds VC.beta., the level detecting circuit LD2 has its output .phi.SB switched. As a result, the switch control signal .phi.1 is switched to turn ON the power switch so that the internal power source VCI is raised. In case, on the contrary, the input signal IN rises prior to the power VCC, the output .phi.SB of the level detecting circuit LD2 is switched when the input signal IN rises to the value VC.beta.. After this, when the power VCC reaches the value VC.alpha., the level detecting circuit LD1 operates to switch the output signal .phi.VC from the low level to the high level. As a result, the signal .phi.1 is switched to turn ON the power switch so that the internal power source VC1 is raised. In either case, the switch is turned ON after the level of the input signal IN has been fixed, so that a large sub-threshold current will not flow. The logic circuit LL is constructed to keep the signal .phi.1 unchanged even if the power VCC exceeds the level VC.alpha. so that the input signal IN changes to change the level .phi.SB. The internal power VC1 breaks in response to the breakage of the external power VCC. Incidentally, the switch is disposed at the side of the power VCC in the shown example but may be inserted to the side of the power VSS. Moreover, in case a plurality of powers are applied, then a level detecting circuit may be provided for at least one of the powers.
Embodiment 4 of Power Switch Control
FIG. 43 is a diagram showing a second control example of the power switch according to a fourth embodiment of the present invention. This embodiment is characterized by providing a circuit LK1 (e.g., a NOR gate) for fixing the input signal level of the logic gate group K1. By this circuit, the level of the input signal IN' of the gate group K1 is fixed at the power rising time to a level (e.g., the low level) for reducing the sub-threshold current of the gate group K1. An example of the operation is shown in FIG. 44. When the power VCC is made to establish a predetermined potential level VC.alpha., this level is detected by the level detecting circuit LD1 to switch the signal .phi.VC from the low level to the high level in this example. As a result, a one-shot pulse is generated in the signal .phi.K1 in a one-shot generating circuit OSH. As the signal .phi.K1 rises to the high level, the input signal IN' of the gate group K1 takes the low level no matter what level the input signal IN from the outside might take. Simultaneously with this, a signal .phi.VC' is generated from the signal .phi.VC by a delay circuit DLY so that the switch SCC is turned ON to raise the internal power VC1 to feed the current to the gate group K1. In this arrangement meanwhile, the signal IN' has already been set by the aforementioned circuit LK1 to the level for reducing the sub-threshold current of the gate group K1. Thus, it is ensured that the potential is fixed at the power making time to feed a large current. When the power VCC breaks, the internal power VC1 also breaks. FIG. 43 shows that the level detecting circuit responds only to the power VCC, but there may be provided a level detecting circuit for the input signal IN or another power, as shown in FIG. 41. Moreover, the switch is disposed at the side of the power VCC in the shown example but may be inserted to the side of the power VSS.
FIG. 48 is a diagram showing a third control example of the power switch according to a fifth embodiment of the present invention. In the embodiments of FIGS. 41 to 44, the external power VCC is inputted to the power switch control circuit SV and is used as the power source of the circuit so that its level may be detected. In the present embodiment, however, there is disposed over the LSI board a battery in addition to the external power source VCC so that the power VCT is fed to the power switch control circuit SV from the battery. Only one battery may be disposed over the board, for example, and shared by a plurality of chips. With this construction, the level detecting circuit acts, too, even when the power VCC is not fed, so that the change of the intrinsic power VCC can be easily monitored. Each LSI chip may be given a construction similar to those of FIGS. 41 or 43. Here, the power switch control circuit SV is always activated by the electric current coming from the battery, to monitor the change of the external power source VCC. By using the present construction, it is possible to easily prevent excessive sub-threshold current, as described hereinbefore, at the power making time. Incidentally, the battery used in FIG. 45 establishes a constant voltage at all times. If, however, a power source for fixing the level at first is prepared, it can be used in place of the battery.
In the random logic LSI such as a microprocessor, the voltage of a subject node is effectively fixed in a forcible manner by fixing the output of an internal register or by adding the logic of a flip-flop circuit having a resetting function. FIG. 46 shows an example of the construction of a latch circuit which can have its output fixed. This circuit has such a simple construction that the inverter in the ordinary latch circuit is replaced by a NAND circuit. As shown in FIG. 47, the circuit acts as a normal latch circuit, while the signal .phi..sub.S is at the high level, and fixes the output signal Q to the high level while the signal .phi..sub.S is at the low level (in the sleep mode). Here, in the sleep mode, the operation of the entire LSI or the circuit block unit is interrupted to reduce the current consumption. Incidentally, if the signal .phi.t is set in the sleep mode to the low level whereas the signal .phi.b is set to the high level, the subthreshold current of the latch circuit itself can also be reduced. If this latch circuit is used, the signal .phi..sub.S takes the low level so that the node N.sub.41 is forced to take the high level. As a result, the data of the register is deleted in the sleep mode. However, in use, the necessary data in the CPU is saved to a main memory so that the reset state is reopened after the sleep mode, and this raises no problem for the resume function by which a note type personal computer is brought into its stand-by state if no input is fed for a predetermined time period. FIG. 48 shows another example of the construction of the latch circuit capable of fixing the output forcibly, which includes using a battery. As shown in FIG. 49, this circuit also acts as a normal latch circuit, while the signal .phi..sub.S is at the high level, and fixes the level of the output signal Q to the high level while the same is at the low level. This latch circuit can hold the data even in the sleep mode because the node N.sub.41 is not influenced even if the signal .phi..sub.S takes the low level. After the sleep mode has been released, the operation can be reopened as it is from the state before the sleep mode, so that the sleep mode can be established even while the CPU is executing a task. As a result, this circuit is suitable in case the operation is returned for a relatively short time period from the sleep mode.
FIG. 50 shows an embodiment in which this invention is applied to a logic circuit for logic operations with a dual-phase clock. In the LSI of an ordinary microprocessor, most of the logic operations in the chip are frequently synchronized with a dual-phase clock. The logic circuit is divided into the logic circuits LC1 and LC2 which are additionally equipped at their individual outputs with latches LT1 and LT2 to be controlled by clocks CK1b and CK2b. In this embodiment, the latches LT1 and LT2 play the role of the level holder. Here, the logic circuits LC1 and LC2 are combinational logic circuits each of which is composed of one or a plurality of logic gates. These two logic circuits LC1 and LC2 are alternately operated in synchronism with the clocks so that switches SWH1 and SWL1 and switches SWH2 and SWL2 are alternately turned ON and OFF by the clocks to interrupt the subthreshold current of the logic circuit which is not operated. According to this embodiment, it is possible to realize a low-power LSI having a low operating voltage and a small subthreshold current.
The operations will be described by using a specific circuit embodiment shown in FIG. 51 and the timings of the control clocks illustrated in FIG. 52. For simplicity, the logic circuits LC1 and LC2 are individually exemplified by one inverter. Moreover, the latches LT1 and LT2 are exemplified by the level holder shown in FIG. 35 but may be exemplified by the circuit shown in FIG. 30. Clocks CK1t and CK2t alternately take the high level without any mutual superposition. The clocks CK1b and CK2b are the signals which are inverted from the clocks CK1t and CK2t, respectively. Here, the high-speed operations can be achieved if the MOS transistors composing the logic circuits LC1 and LC2 have their threshold voltages set at the low level. On the other hand, the MOS transistors having their gates supplied with the clocks must be able to interrupt the subthreshold current when turned OFF. For this necessity, it is sufficient to raise the threshold voltages or to set the high level of the clocks higher than the high voltage VHH and the low level lower than the low voltage VLL.
In the operation mode, the logic circuit LC1 is operated while the clock CK1t is at the high level. At this time, the clock CK2t is at the low level so that the latch LT2 latches the data to be supplied thereto. Moreover, since the logic circuit LC2 need not operate, the transistors MP12 and MN12 are turned OFF to interrupt the subthreshold current. While the clock CK2t is at the high level, on the contrary, the latch LT1 latches the data, and the logic circuit LC2 operates so that the subthreshold current of the logic circuit LC1 can be interrupted. In short, the current of either the logic circuit LC1 or LC2 can be interrupted to reduce the subthreshold current to one half of the prior art.
In order to reduce the power in the recent microprocessor operating at 3.3 V to 5 V, as described above, the charging and discharging currents are reduced by interrupting the supply of clocks to an unnecessary circuit in the low-power backup mode (i.e., the sleep mode). In this embodiment, when both the clocks CK1t and CK2t are held at the low level in the sleep mode, as shown in FIG. 52, both the transistors MP11 and MN11 and the transistors MP12 and MN12 are turned OFF to interrupt the current flow through both the logic circuits LC1 and LC2. As a result, the effect for reducing the subthreshold current in the sleep mode is far higher than that in the operation mode.
FIGS. 53(A) and 53(B) show another embodiment of this invention, in which the invention is applied to a gate array. This gate array is a digital logic circuit so that the foregoing embodiments can be applied to reduce the subthreshold current. In the gate array, however, some gates are left unused and inactivated when the logic circuit is to be constructed, as will be described in the following. FIG. 53(A) shows the embodiment in which the logic shown in FIG. 53(B) is constructed in a one-circuit block of the gate array using two-input NANDs as its basic cells. In this Figure, blocks A001, A002 and A003 enclosed by broken lines are the basic NAND cells. Moreover, INN1 and OUT1 designate the input and output of this logic circuit block, respectively. In case the inverter is constructed of the NAND cells, as shown, it is a current practice to fix inputs A004 and A005 at the high level (V.sub.CC) thereby to inactivate the corresponding gates. The gates thus inactivated frequently occupy several ten % of the usable gates. Thus, the subthreshold currents that flow through the inactivated gates cannot be ignored in the low-voltage gate array in which the threshold voltages of the transistors are scaled down. As shown, transistors MA01 and MA03 have their sources connected with a second power source line V.sub.CL which is separated from the power source V.sub.CC through the transistor M.sub.C and the resistor R.sub.C. In the low-power mode, the signal .phi..sub.C is set to the high level to cut off the transistor M.sub.C. Then, the transistors MA01 and MA03 are inversely biased between their gates and sources and are deeply cut off so that the subthreshold currents of the inactivated gates can be drastically reduced. As to the active gates, however, the leakage currents can also be prevented, if the p-channel transistors have their sources connected with V.sub.CC or V.sub.CL whereas the n-channel transistors have their sources connected with V.sub.SL or V.sub.SS in accordance with the logic states (at the high level "H" or the low level "L", as shown) of the individual gate outputs for a period requiring the low lower dissipation as in the standby state. Incidentally, as to the inactive gate, no current has to be supplied to the transistors even when they are in operation so that an interconnection other than the power source line V.sub.CL formed to have a minimum interconnection width and a high impedance can be used. For this interconnection, the transistor M.sub.C is not always essential, and only use of the resistor R.sub.C may be sufficient.
FIGS. 54(A) and 54(B) show another embodiment of this invention, in which the prevention of the subthreshold current according to this invention is applied to the inactive gates in a gate array composed of basic cells of two-input NORs. FIG. 54(A) shows the embodiment in which the logic shown in FIG. 54(B) is composed of the NOR cells. In FIG. 54(A), broken lines A001, A012 and A013 are the basic NOR cells. In case the inverter is composed of the NOR cells, it is a current practice to fix an input A014 or A015 at the LOW (V.sub.SS) level thereby to inactivate the corresponding gates. If the transistors MA11 and MA13 have their sources connected at this time with the lower source line V.sub.SL, they can be deeply cut off on the basis of the aforementioned operating principle, to prevent the subthreshold current.
Moreover, as the LSI chip has its scale enlarged, a test circuit for testing other circuit groups is packaged on the chip. This test circuit can have its operation interrupted during ordinary chip operation (other than the testing time). In this case, the foregoing embodiments are effective for reducing the subthreshold current of the test circuit.
An example in which the individual embodiments thus far described are applied to a single-chip microprocessor is described next. First of all, a microprocessor having the foregoing power reducing mechanisms will be described. In the microprocessor of the prior art, the power is controlled by controlling the entire chip at one time. Since the chip i386SL of Intel, for example, has a completely static internal circuit, its internal status can be retained, even if the input of a clock to the chip is interrupted, to reopen the operation when the input of the clock is applied again. Thus, the operation of the entire chip is interrupted to reduce the power of the entire system by interrupting the input of the clock. However, this is possible only when the power source voltage is as high as 3.3 V to 5 V as in the prior art. This is because the MOS transistors composing the CMOS circuit can take threshold voltages as high as about 0.4 to 0.5 V so that their subthreshold currents can be reduced to negligible values. As has already been described thereinbefore, however, the high-speed system to be operated by a power source voltage of 2 V or less or by the voltage of one battery of about 0.9 or 1.6 V cannot have its power reduced any more even if the clock is interrupted. In the LSI composed of logic gates, e.g. mainly random gates, generally speaking, the number of the logic gates having varying input voltages is about 20% of all the multiple logic gates in the chip. The remaining about 80% logic gates have their inputs unvaried. Since the CMOS circuit of the prior art advantageously has a high threshold voltage, most of the power of the 80% of the logic gates can be neglected to reduce the power of the entire chip. However, this advantage cannot be expected any more at a low power source voltage. Next will be described a microprocessor as one example of an electronic apparatus in which the entire chip can have its power reduced for operation at a low power source voltage.
FIG. 55 shows a single-chip microprocessor having a power reducing mechanism of this invention packaged therein. This microprocessor is featured in that the chip is equipped with a mechanism for controlling the active/standby modes for each unit, as will be described in the following. Reference numeral 600 designates the single-chip microprocessor. This microprocessor 600 is packaged thereover with a central processing unit (CPU) 601, a co-processor A (COPA) 602, a coprocessor B (COPB) 603, a local memory (LM) 604 and a bus control unit (BUSC) 605. These individual units are connected through an internal bus 651 over the chip. Moreover, the units are connected with the chip externally through the BUSC 605 and an external bus 652. With this external bus 652, there are connected a main memory (MS) 606, an input/output device (IO) 607 and so on. The CPG 606 is a clock generator, and the individual units in the chip operate in synchronism with a clock signal 653 generated by the CPG 606.
The COPA 602, the COPB 603 and the LM 604 individually have two operating states, one of which is the sleep state. In this state, the individual units do not operate so that the power to be dissipated is remarkably reduced. Another is the active state. In this state, the units execute the data reading/writing operations and other execute operations. Therefore, the power dissipation is not suppressed to a remarkably small value. The logic circuits constructed of these individual units are exemplified by the circuits of FIGS. 18 to 27, FIGS. 30 to 33 and FIGS. 50 to 52. As a result, the power dissipation in the sleep state can be reduced. In the active state, too, the power can also be reduced by controlling the active state finely for each phase of the dual-phase clocks with the circuits of FIGS. 50 to 52, for example. The MS 606 and the IO 607 have the active/sleep states, too. Signals 654 and 655 to be outputted from the microprocessor 600 are signals for instructing to activate the MS 606 and the IO 607, respectively.
The co-processors COPA 602 and COPB 603 are basically the units of the same kind a nd execute the specified operations only when the program executed in the CPU contains an instruction to require the execution of the COPA or COPB. It is sufficient that the active state is effected only at that time while the sleep state prevails in the remaining period. In an ordinary program, the request for this execution is not so frequent. These co-processors are characterized in that they are equipped with a number of register files and a (or a plurality of) proprietary execution unit so that they have a number of transistors in their entirety.
On the other hand, the LM 604 is stored with the programs and data required by the CPU so that the frequency of its access is high. In case, however, the CPU has a cache memory packaged therein, the execution is performed in the CPU. This structure is characterized in that the accessing frequency is dropped to elongate the period of the sleep state.
The CPU 601 is a unit for executing instructions and processing data and for executing programs at all times (at an activity ratio of 100%). The CPU contains the fundamentals of an ordinary processor, such as a general purpose register, an execution unit and so on and may contain a cache memory, as the case may be. The instructions or data are stored in the LM 604 or MS 606. The LM 604 is an on-chip memory having a small capacitance but accessible at a high speed so that it is stored with the instructions or data to be frequently used by the CPU 601. The instructions or data, which need not be accessed so frequently, are stored in the memory MS 606 which has a large capacitance but an intermediate speed. The CPU 601 can access the LM 604 directly through the internal bus 651. On the other hand, the access to the MS 606 is executed through the internal bus 651, the BUSC 605 and the external bus 652. The BUSC 605 includes external bus buffers having a bit width of about 32 to 128 bits. The BUSC may be activated only for accessing a memory or device outside of the chip. The BUSC may be held in the sleep state if the program or data it needs are present in the chip.
The COPA 602 is a co-processor for executing multiplication, division and calculations of roots and absolute values and has a proprietary execution unit packaged therein for processing these calculations at high speed. The COPB 603 is a co-processor for executing functional calculations of trigonometric functions and distances and has a proprietary execution unit for processing those calculations at a high speed. The CPU 601 starts the executions of the individual co-processors by writing commands for instructing the operations required into command registers CMDA 609 and CMDB 610 in the COPA 602 and COPB 603, by way of the internal bus 651. The individual co-processors are in the sleep state before the executions are started, so that little power is dissipated.
FIG. 56 is a diagram showing the internal constructions of the COPA 602. The inside is constructed of two blocks ITFA 700 and EXA 701. The ITFA 700 is composed of a command register CMDA 609, a command decoder DEC 706, operand registers RA 702, RB 703 and RC 704, and a control circuit CNT 705. The EXA 701 has a proprietary execution unit for processing the multiplications, the divisions and the calculations of roots and absolute values at a high speed, and a control circuit for controlling the execution unit. The command sent from the CPU 601 through the internal bus 651 is latched in the CMDA 609 and decoded by the DEC 706 to cause the EXA 701 to execute the operations instructed by that command. The command is divided into one of multiplication, division, and calculations of either roots or absolute values. The source operands are sent from the CPU 601 and stored in the RA 702 and RB 703, and the executed results of the EXA 701 are stored in the RC 704 and read out by the CPU 601. The EXA 701 is in the sleep state while it is not executing. When the command is decoded by the DEC 706, a signal for causing the EXA 701 to execute the operation instructed by the command is generated so that the EXA 701 starts its execution. During this execution, the EXA 701 is in the active state. After this execution, the EXA 701 stores the results in the RC 704 to clear the CMDA 609 to zero. When the DEC 706 detects that the content of the CMDA 609 is zero, the EXA 701 is brought into the sleep state by asserting a SLEEP signal 707. The CNT 705 controls the reading/writing and zero-clearing operations for the individual registers 609, 702, 703 and 704. The ITFA 700 is always in the active state so as to receive the commands from the CPU at all times. The clock signal 653 generated by the CPG 606 is used in the ITFA 700. On the other hand, a EXA clock signal 710 is outputted through a gate circuit 709 and used as a clock for the EXA 701. When the SLEEP 707 is asserted, the gate circuit 709 interrupts the EXA clock 710 so that the clock is not supplied to the EXA 701. As a result, the clock of the EXA 701 is also interrupted in the sleep state. By this SLEEP signal, for example, the switches of the circuits of FIG. 18 to 27 or FIGS. 29 to 33 are controlled to reduce the subthreshold current in the sleep state.
The EXA 701 contains not only a proprietary execution unit but also a register for latching the intermediate result of the execution, a register for latching the execution state, and a latch for controlling the execution. These registers and latches to be used are exemplified by the circuits of FIG. 46 and FIG. 48. For the case of the circuit of FIG. 46, the internal state of the latch is broken once the sleep state is entered. For the case of the circuit of FIG. 48, on the other hand, the internal state of the latch is not broken even if the sleep state is entered. As a result, when the active state is restored after the sleep state is once entered, the temporary executions that were suspended can be reopened.
The COPB is a co-processor for executing the functional calculations of trigonometric functions and distances and is given an internal structure and an operation similar to that of the COPA 602.
FIG. 57 shows the internal structure of the LM 604. MEM 901 is a memory unit for storing information such as instructions/data. MCNT 902 receives an access demand from the CPU 601 to read the data stored in the MEM 901 and to write the data in the MEM 901. When an access demand is made by the CPU 601, the MCNT 902 asserts a signal ACT 903 for activating the MEM 901 and activates the MEM 901. Without the access demand, the ACT 903 is negated so that the MEM 901 is in the sleep state. By this ACT signal, the switches of the circuits of FIGS. 18 to 27 or FIGS. 29 to 33, for example, are controlled to reduce the subthreshold current in the sleep state. In this state, too, the data are retained in the memory. The MCNT 902 is always in the active state so that it may receive the access demand from the CPU at all times.
The CPU 601 accesses the instructions or data to the MS 606 through the internal bus 651, the BUSC 605 and the external bus 652. Only at this time, the BUSC 605 is activated. FIG. 58 shows the internal structure of the BUSC 605. BCNT 800 is a circuit for controlling the access to the external bus 652 in response to the demand of the CPU 601. OUTB 801 is a driver circuit for driving the external bus 652, when data are supplied from the internal bus 651 to the external bus 652, and is activated only at this time. INB 802 is a driver circuit for driving the internal bus 651, when data are supplied from the external bus 652 to the internal bus 651, and is activated only at this time. When the BCNT 800 receives a write demand for the MS 606 or the IO 607 outside of the chip from the CPU 601, it asserts ACTW 803 to activate the OUTB 801. On the other hand, when the BCNT receives a read demand of the MS 606 or the IO 607 outside of the chip from the CPU 601, it asserts ACTR 804 to activate the INB 802. For the period other than those operations, the OUTB 801 and the INB 802 are in the sleep state. The BCNT 800 is always active so that it may receive the access demand to the outside of the chip. The BCNT 800 further outputs the active support signal 654 for the MS 606 and the active instruct signal 655 for the IO 607. In case the CPU 601 demands the BCNT 800 to access the MS 606, the BCNT 800 detects the demand to assert the signal 654 to activate the MS 606. The signal 655 is also used for similar operations.
The OUTB 801 is exemplified by the output buffer of FIG. 27, and the switches S.sub.S and S.sub.C are controlled in accordance with the ACTW signal. This OUTB drives a high load (e.g., the external bus 652) and needs the MOS transistors having a large channel width in the number of the bus width (e.g., 64 bits) so that its total channel width is remarkably large. As a result, the reduction of the subthreshold current of the OUTB highly contributes to the reduction of the current of the entire system.
The INB 802 used is exemplified by the input buffer of FIG. 27, and the ACTR signal is supplied to the SB terminal. As a result, the internal bus 651 has its voltage level fixed in the sleep state. Thus, the units COPA, COPB and LM connected with the internal bus 651 can be exemplified by the circuits of FIGS. 18 to 27 so that these units can have their subthreshold currents reduced easily.
The MS 606 is exemplified by a DRAM. This DRAM may be an ordinary DRAM or a synchronous DRAM, as is disclosed on pp. 43-49 of IEEE Spectrum, October 1992. In this synchronous DRAM, the supply of the clock to the chip inside can be controlled by a clock enable/disable signal so that the current dissipation can be effectively reduced by utilizing the signal. Specifically, the clock supply to the chip inside is interrupted in the sleep state. Moreover, the subthreshold current of the internal circuit can be reduced by using the circuit of FIG. 27 as the input buffer of the synchronous DRAM and by applying the clock enable/disable signal to the SB terminal.
FIG. 59 illustrates examples of the overall operations of the microprocessor 600. The abscissa indicates the time, and hatching lines indicate that the individual units or blocks are active. In this example, the CPU 601 issues a dividing command to the COPA 602 at time T1, and the COPA 602 executes the divisions from time T1 to time T2 and reports the end of calculations to the CPU 601 at time T2 until it comes again into the sleep state. After this, the CPU 601 issues a distance calculating command to the COPB 603 at time T3, and the COPB 603 executes the distance calculations from time T3 to time T4 and reports the end of calculations to the CPU 601 at time T4 until it comes again into the sleep state. The LM 604 is activated only when the access to data is demanded by the CPU 601. The BUSC 605 is also activated only when the CPU 601 accesses the outside. Thus, the individual units and blocks in the microprocessor 600 have their active/sleep states precisely controlled so that the microprocessor 600 can have its power dissipation greatly reduced.
This embodiment of the invention is applied internally of the chip, but it is self-explanatory that this invention can be expanded to an embodiment of a computer system constructed of a plurality of chips. For example, this invention can be easily applied to the case in which the individual units 601 to 605 of FIG. 55 are made of different chips.
As has been described hereinbefore, the present invention is remarkably effective for reducing the power consumption of the MOS transistor circuit and the semiconductor integrated circuit constructed of the former. The demand for reducing the power consumption of the semiconductor integrated circuit is earnest especially in recent years, as in the microprocessor system having a low-power backup mode, ad disclosed on pp. 106-111 of NIKKEI ELECTRONICS issued on Sep. 2, 1991. In the backup mode, the power consumption is reduced by interrupting the clock or the supply the power to unnecessary portions. However, no consideration is taken into the reduction of the sub-threshold current. Since these processor systems operate at 3.3 to 5 V, transistors having sufficiently high threshold voltages can be used to reduce the sub-threshold current to a trouble-free level. If, however, the operating voltage is lowered to 2 V or 1.5 V so that the threshold voltage has to be lowered, the technique of the prior art using the CMOS circuit cannot reduce the excessive sub-threshold current any more. A further reduction of the power consumption can be realized if the present invention is applied to a resume circuit (which is fed with the power even in the backup mode).
As has been described hereinbefore, according to the present invention, it is possible to realize a MOS transistor circuit operating at a high speed with a low power consumption and a semiconductor integrated circuit constructed of the MOS transistor circuit.
Respective embodiments of the present invention have been described above taking a MOS semiconductor circuit device as an example, but the present invention is also applicable to a metal insulator semiconductor (MIS) circuit device.

Claims

1. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit that changes a voltage potential at a source of the first MOS transistor between a first operating voltage potential and a second voltage operating potential;
wherein a logic voltage swing at the output node when the voltage potential at a source of the first MOS transistor is the second operating voltage potential is smaller than a logic voltage swing at the output node when the voltage potential at the source of the first MOS transistor is the first operating voltage potential;
wherein a back rate of the first MOS transistor is connected to the first operating potential;
a second control unit that changes a voltage potential at a source of the second MOS transistor between a third operating voltage potential and a fourth voltage operating potential;
wherein the second MOS transistor's characteristics is that a leak current flows through the source-drain path of the second MOS transistor even when a voltage between the gate and the source of the second MOS transistor is 0 volts; and
wherein a back gate of the second MOS transistor is connected to the third operating potential.
2. A semiconductor integrated circuit according to claim 1,
wherein the first control unit comprises a first switch and the second control unit comprises a second switch.
3. A semiconductor integrated circuit according to claim 2,
wherein the first control unit comprises a first resistor and the second control unit comprises a second resistor.
4. A semiconductor integrated circuit according to claim 1,
wherein the first control unit changes the voltage potential at the source of the first MOS transistor synchronously with a chip activating signal,
wherein the second control unit changes the voltage potential at the source of the second MOS transistor synchronously with the chip activating signal.
5. A semiconductor integrated circuit according to claim 4,
wherein the voltage potentials at the sources of the first and second MOS transistor are being changed at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
6. A semiconductor integrated circuit according to claim 5,
wherein the voltage potentials at the sources of the first and second MOS transistor are being changed at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
7. A semiconductor integrated circuit according to claim 1,
wherein the first control unit changes the voltage potential at the source of the first MOS transistor in response to a back-up mode signal,
wherein the second control unit changes the voltage potential at the source of the second MOS transistor in response to the back-up mode signal.
8. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor;
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor,
wherein a first signal potential supplied to a gate of the third MOS transistor is at least as high as a voltage potential at the source of the third MOS transistor if the third MOS transistor is a D-channel type,
wherein the first signal potential is at least as low as a voltage potential at the source of the third MOS transistor if the third MOS transistor is a n-channel type;
a second control unit having a fourth MOS transistor whose source-drain path is between a second operating voltage potential and a source of the second MOS transistor;
wherein the second MOS transistor's characteristics is that a leak current flows through the source-drain path of the second MOS transistor even when a voltage between the gate and the source of the second MOS transistor is 0 volts,
wherein a second signal potential supplied to a gate of the fourth MOS transistor is higher than a voltage potential at the source of the fourth MOS transistor if the fourth MOS transistor is a p-channel type, and
wherein the second signal potential is lower than a voltage potential at the source of the fourth MOS transistor if the fourth MOS transistor is a n-channel type.
9. A semiconductor integrated circuit according to claim 8,
wherein the second control unit comprises a sixth MOS transistor whose source-drain path is between the second operating voltage potential and the source of the second MOS transistor,
wherein a conductance of the sixth MOS transistor is smaller than that of the fourth MOS transistor.
10. A semiconductor integrated circuit according to claim 8,
wherein a back gate of the second MOS transistor is connected to the second operating potential.
11. A semiconductor integrated circuit according to claim 8,
wherein both the first and second signal potential are supplied synchronously with a chip activating signal.
12. A semiconductor integrated circuit according to claim 11,
wherein both the first and second signal potentials are supplied at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
13. A semiconductor integrated circuit according to claim 12,
wherein both the first and second signal potentials are supplied at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
14. A semiconductor integrated circuit according to claim 8,
wherein both the first and second signal potentials are supplied in response to a back-up mode signal.
15. A semiconductor integrated circuit according to claim 9,
wherein both the first and fifth MOS transistor are formed in a first semiconductor region and both the second and sixth MOS transistor are formed in a second semiconductor region.
16. A semiconductor integrated circuit comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor;
a second control unit having a fourth MOS transistor whose source-drain path is between a second operating voltage potential and a source of the second MOS transistor;
wherein the second MOS transistor's characteristics is that a leak current flows through the source-drain path of the second MOS transistor even when a voltage between the gate and the source of the second MOS transistor is 0 volts;
wherein an absolute value of a threshold voltage of the third MOS transistor is larger than an absolute value of a threshold voltage of the first MOS transistor;
wherein an absolute value of a threshold voltage of the fourth MOS transistor is larger than an absolute value of a threshold voltage of the second MOS transistor.
17. A semiconductor integrated circuit according to claim 16,
wherein the first control unit comprises a fifth MOS transistor whose source-drain path is between the first operating voltage potential and the source of the first MOS transistor,
wherein a conductance of the fifth MOS transistor is smaller than that of the third MOS transistor,
wherein the second control unit comprises a sixth LOS transistor whose source-drain path is between the second operating voltage potential and the source of the second MOS transistor,
wherein a conductance of the sixth MOS transistor is smaller than that of the fourth MOS transistor.
18. A semiconductor integrated circuit according to claim 16,
wherein a back gate of the first MOS transistor is connected to the first operating potential,
wherein a back gate of the second MOS transistor is connected to the second operating potential.
19. A semiconductor integrated circuit according to claim 16,
wherein both a first signal potential supplied to a gate of the third MOS transistor and a second signal potential supplied to a gate of the fourth MOS transistor are supplied synchronously with a chip activating signal.
20. A semiconductor integrated circuit according to claim 19,
wherein both the first and second signal potentials are supplied at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
21. A semiconductor integrated circuit according to claim 20,
wherein the first and second signal potentials are supplied at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
22. A semiconductor integrated circuit according to claim 16,
wherein both a first signal potential supplied to a gate of the third MOS transistor and a second signal potential supplied to a gate of the fourth MOS transistor are supplied in response to a back-up mode signal.
23. A semiconductor integrated circuit according to claim 17,
wherein both the first and fifth MOS transistor are formed in a first semiconductor region,
wherein both the first and fifth MOS transistor are formed in a first semiconductor region and both the second and sixth MOS transistor are formed in a second semiconductor region.
24. A semiconductor integrated circuit according to claim 16,
wherein a chip of the semiconductor integrated circuit is supplied with a power supply voltage equal to or smaller than 2 volt.
25. A semiconductor integrated circuit according to claim 24,
wherein an absolute value of a threshold voltage of the first MOS transistor is equal to or smaller than 0.35 volt.
26. A semiconductor integrated circuit according to claim 24,
wherein a channel length of the first MOS transistor is equal to or smaller than 0.25 .mu.m.
27. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor;
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor,
wherein a first signal potential supplied to a gate of the third MOS transistor is at least as high as a voltage potential at the source of the third MOS transistor if the third MOS transistor is a D-channel type,
wherein the first signal potential is at least as low as a voltage potential at the source of the third MOS transistor if the third MOS transistor is a n-channel type, and
wherein the first signal potential is supplied synchronously with a chip activating signal.
28. A semiconductor integrated circuit according to claim 27,
wherein the first signal potential is supplied at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
29. A semiconductor integrated circuit according to claim 28,
wherein the first signal potential is supplied at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at a reset level.
30. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor;
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor and a fourth MOS transistor whose source-drain path is between the first operating voltage potential and the source of the first MOS transistor,
wherein the fourth MOS transistor is an output transistor of a current mirror circuit, a current that flows through the source-drain path of the fourth MOS transistor is smaller than the leak current of the first MOS transistor when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second control unit having a fifth MOS transistor whose source-drain path is between a second operating voltage potential and a source of the second MOS transistor and sixth MOS transistor whose source-drain path is between the second operating voltage potential and the source of the second MOS transistor;
wherein the second MOS transistor's characteristics is that a leak current flows through the source-drain path of the second MOS transistor even when a voltage between the gate and the source of the second MOS transistor is 0 volts; and
wherein the sixth MOS transistor is an output transistor of a current mirror circuit, a current that flows through the source-drain path of the sixth MOS transistor is smaller than the leak current of the second MOS transistor.
31. A semiconductor integrated circuit according to claim 30,
wherein a back gate of the second MOS transistor is connected to the second operating potential.
32. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor;
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor and a fourth MOS transistor whose source-drain path is between the first operating voltage potential and the source of the first MOS transistor;
wherein the fourth MOS transistor is an output transistor of a current mirror circuit, a current that flows through the source-drain path of the fourth MOS transistor is smaller than the leak current of the first MOS transistor when a voltage between a rate and the source of the first MOS transistor is 0 volts; and
wherein a back gate of the first MOS transistor is connected to the first operating potential.
33. A semiconductor integrated circuit comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor, said second MOS transistor whose characteristics is that a leak current flows through a source-drain path of the second MOS transistor even when a voltage between a gate and the source of the second MOS transistor is 0 volts;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit coupled between a first operating voltage potential and the source of the first MOS transistor;
a second control unit coupled between a second operating voltage potential and the source of the second MOS transistor;
wherein said first control unit has a mode that limits its output current to one smaller than the leak current flows through a source-drain path of the first MOS transistor when a voltage between a gate and the source of the first MOS transistor is 0 volts, and
wherein said second control unit has a mode that limits its output current to one smaller than the leak current flows through a source-drain path of the second MOS transistor when a voltage between a gate and the source of the second MOS transistor is 0 volts.
34. A semiconductor integrated circuit according to claim 33,
wherein a back gate of the first MOS transistor is connected to the first operating potential.
35. A semiconductor integrated circuit according to claim 33,
wherein a first control unit comprises a first switch and the second control unit comprises a second switch.
36. A semiconductor integrated circuit according to claim 35,
wherein the first control unit comprises a first resistor and the second control unit comprises a second resistor.
37. A semiconductor integrated circuit according to claim 33,
wherein a chip of the semiconductor integrated circuit is supplied with a power supply voltage equal to or smaller than 2 volt.
38. A semiconductor integrated circuit according to claim 37,
wherein an absolute value of a threshold voltage of the first MOS transistor is equal to or smaller than 0.35 volt.
39. A semiconductor integrated circuit according to claim 37,
wherein a channel length of the first MOS transistor is equal to or smaller than 0.25 .mu.m.
40. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit that chances a voltage potential at a source of the first MOS transistor between a first operating voltage potential and a second voltage operating potential;
wherein a logic voltage swing at the output node when the voltage potential at a source of the first MOS transistor is the second operating voltage potential is smaller than a logic voltage swing at the output node when the voltage potential at the source of the first MOS transistor is the first operating voltage potential;
wherein a back gate of the first MOS transistor is connected to the first operating potential; and
wherein the first control unit changes the voltage potential at the source of the first MOS transistor synchronously with a chip activating signal.
41. A semiconductor integrated circuit according to claim 40,
wherein the voltage potential at the source of the first MOS transistor is being changed at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
42. A semiconductor integrated circuit according to claim 41,
wherein the voltage potential at the source of the first MOS transistor is being changed at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
43. A semiconductor integrated circuit according to claim 40,
wherein the voltage potential at the source of the first MOS transistor is changed in response to a back-up mode signal.
44. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor;
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit having a third MOS transistor whose source-drain path is between a first operating voltage potential and a source of the first MOS transistor and a fourth MOS transistor whose source-drain path is between the first operating voltage potential and the source of the first MOS transistor;
wherein the fourth MOS transistor is an output transistor of a current mirror circuit, a current that flows through the source-drain path of the fourth MOS transistor is smaller than the leak current of the first MOS transistor when a voltage between a gate and the source of the first MOS transistor is 0 volts; and
wherein a chip of the semiconductor integrated circuit is supplied with a power supply voltage equal to or smaller than 2 volt.
45. A semiconductor integrated circuit according to claim 44,
wherein an absolute value of a threshold voltage of the first MOS transistor is equal to or smaller than 0.35 volt.
46. A semiconductor integrated circuit according to claim 44,
wherein a channel length of the first MOS transistor is equal to or smaller than 0.25 .mu.m.
47. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor,
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor;
a first control unit that changes a voltage potential at a source of the first MOS transistor between a first operating voltage potential and a second voltage operating potential;
wherein a back gate of the first MOS transistor is connected to a first back gate potential;
wherein a voltage deference between the first operating voltage potential and the first back gate potential is smaller than a voltage between the second operating voltage potential and the first back gate potential; and
a second control unit that changes a voltage potential at a source of the second MOS transistor between a third operating voltage potential and a fourth voltage operating potential;
wherein the second MOS transistor's characteristics is that a leak current flows through the source-drain path of the second MOS transistor even when a voltage between the gate and the source of the second MOS transistor is 0 volts;
wherein a back gate of the second MOS transistor is connected to a second back gate potential; and
wherein a voltage deference between the third operating voltage potential and the second back gate potential is smaller than a voltage deference between the fourth operating voltage potential and the second back gate potential.
48. A semiconductor integrated circuit according to claim 47,
wherein the first control unit comprises a first switch and the second control unit comprises a second switch.
49. A semiconductor integrated circuit according to claim 48,
wherein the first control unit comprises a first resistor and the second control unit comprises a second resistor.
50. A semiconductor integrated circuit according to claim 47,
wherein the first control unit changes the voltage potential at the source of the first MOS transistor synchronously with a chip activating signal,
wherein the second control unit changes the voltage potential at the source of the second MOS transistor synchronously with the chip activating signal.
51. A semiconductor integrated circuit according to claim 50,
wherein the voltage potentials at the sources of the first and second MOS transistor are being changed at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
52. A semiconductor integrated circuit according to claim 51,
wherein the voltage potentials at the sources of the first and second MOS transistor are being changed at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
53. A semiconductor integrated circuit according to claim 47,
wherein the first control unit changes the voltage potential at the source of the first MOS transistor in response to a back-up mode signal,
wherein the second control unit changes the voltage potential at the source of the second MOS transistor in response to the back-up mode signal.
54. A semiconductor integrated circuit, comprising:
a first MOS transistor whose characteristics is that a leak current flows through a source-drain path of the first MOS transistor even when a voltage between a gate and the source of the first MOS transistor is 0 volts;
a second MOS transistor whose drain is connected to the drain of the first MOS transistor,
an input node connected to the gate of each of the first and second MOS transistor;
an output node connected to the drain of each of the first and second MOS transistor; and
a first control unit that changes a voltage potential at a source of the first MOS transistor between a first operating voltage potential and a second voltage operating potential;
wherein a back gate of the first MOS transistor is connected to a first back gate potential;
wherein a voltage deference between the first operating voltage potential and the first back gate potential is smaller than a voltage between the second operating voltage potential and the first back gate potential; and
wherein the first control unit changes the voltage potential at the source of the first MOS transistor synchronously with a chip activating signal.
55. A semiconductor integrated circuit according to claim 54,
wherein the voltage potential at the source of the first MOS transistor is being changed at a beginning term (a) of the chip activating signal, the beginning term is shorter than a whole term (b) of the chip activating signal.
56. A semiconductor integrated circuit according to claim 55,
wherein the voltage potential at the source of the first MOS transistor is being changed at a beginning term after the chip activating signal is set to a reset level, the beginning term is shorter than a whole term (a+b) that the chip activating signal is at the reset level.
57. A semiconductor integrated circuit according to claim 54,
wherein the voltage potential at the source of the first MOS transistor is changed in response to a back-up mode signal.

Priority Claims (5)

Number	Date	Country
4-094070	Apr 1992	JPX
4-094077	Apr 1992	JPX
4-345901	Dec 1992	JPX
5-022392	Feb 1993	JPX
5-231234	Sep 1993	JPX

Parent Case Info

This application is a continuation application of U.S. Ser. No. 08/294,055, filed Aug. 24, 1994, now U.S. Pat. No. 5,614,487, which is a continuation-in-part application of application Ser. No. 08/193,765, filed Feb. 8, 1994 now U.S. Pat. No. 5,583,457, which is a continuation-in-part application of application Ser. No. 08/045,792, filed Apr. 14, 1993, abandoned.

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Continuations (1)

	Number	Date	Country
Parent	294055	Aug 1994

Continuation in Parts (2)

	Number	Date	Country
Parent	193765	Feb 1994
Parent	45792	Apr 1993

Semiconductor integrated circuit device having power reduction mechanism

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Abstract