Claims
- 1. A semiconductor integrated circuit device comprising:
- a semiconductor chip;
- a reference voltage supply pattern which transmits a reference voltage externally supplied to a circuit formed on the semiconductor chip; and
- a voltage source pattern being arranged along said reference voltage supply pattern and having a potential externally supplied, wherein the reference voltage is varied in response to a variation in the potential at said voltage source pattern.
- 2. The semiconductor integrated circuit device as claimed in claim 1, wherein said semiconductor integrated circuit device is a synchronous dynamic random access memory device.
- 3. The semiconductor integrated circuit device as claimed in claim 1, wherein said potential at said voltage source pattern is a ground level potential.
- 4. The semiconductor integrated circuit device as claimed in claim 1, wherein said voltage source pattern comprises two conductor patterns which are arranged along both sides of the reference voltage supply pattern.
- 5. The semiconductor integrated circuit device as claimed in claim 1, wherein said voltage source pattern is not connected to any circuit parts on said semiconductor chip.
- 6. The semiconductor integrated circuit device as claimed in claim 1, further comprising a second voltage source pattern connected to said circuit and a first external connection terminal,
- said voltage source pattern connected to a second external connection terminal,
- wherein the voltage source pattern is electrically isolated form said second voltage source pattern on said semiconductor chip.
- 7. A semiconductor integrated circuit device comprising:
- a semiconductor chip;
- a reference voltage supply pattern which transmits a reference voltage externally supplied; and
- a voltage source pattern being arranged along said reference voltage supply pattern and having a potential externally supplied, and a circuit for comparing an externally supplied signal with said reference voltage to determine a logic level of said externally supplied signal.
- 8. The semiconductor integrated circuit device as claimed in claim 7, wherein said voltage source pattern is not connected to any circuit parts on said semiconductor chip.
- 9. The semiconductor integrated circuit device as claimed in claim 7, further comprising a second voltage source pattern connected to said circuit and a first external connection terminal,
- said voltage source pattern connected to a second external connection terminal,
- wherein the voltage source pattern is electrically isolated from said second voltage source pattern on said semiconductor chip.
- 10. The semiconductor integrated circuit device as claimed in 7, wherein a potential of said externally supplied signal is varied in response to said potential of said voltage source pattern.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-008542 |
Jan 1994 |
JPX |
|
6-086697 |
Apr 1994 |
JPX |
|
Parent Case Info
This application is a divisional of U.S. application Ser. No. 08/722,934 filed on Sep. 30, 1996, now U.S. Pat. No. 5,757,226, which is a continuation of U.S. application Ser. No. 08/377,229, field Jan. 24, 1995, now abandoned.
US Referenced Citations (9)
Foreign Referenced Citations (2)
Number |
Date |
Country |
63-265524 |
Nov 1988 |
JPX |
4030470 |
Feb 1992 |
JPX |
Non-Patent Literature Citations (4)
Entry |
Paul Horowitz, The Art of Electronics, Cambridge University Press, NY, NY, 2nd ed., 1990, pp. 310-311. |
Concannon et al., IBM Technical Disclosure Bulletin--"Regulated On-Chip Supply Voltage Source For MOSFET Integrated Circuits", Feb. 1982; pp. 4668-4669. |
Hansen, IBM Technical Disclosure Bulletin--"Voltage Regulator", Sep. 1971; p. 1050. |
Dorler et al., IBM Technical Disclosure Bulletin--"Constant-Voltage Source", Sep. 1971, p. 1058. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
722934 |
Sep 1996 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
377229 |
Jan 1995 |
|