SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract

A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-169721, filed on Oct. 24, 2022, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor integrated circuit device.

BACKGROUND

In the related art, there is, for example, a memory system shown in FIG. 1. The conventional memory system shown in FIG. 1 includes a microcomputer 101 and EEPROMs (Electrically Erasable and Programmable Read Only Memories) 102_1 and 102_2 which are semiconductor integrated circuit devices. The microcomputer 101, which is a master device, and the EEPROMs 102_1 and 102_2, which are slave devices, are interconnected by an I2C bus. Further, a maximum of eight EEPROMs 102_1 to 102_8 (EEPROMs 102_3 to 102_8 are not shown) can be connected to the microcomputer 101 by the I2C bus. In the following description, the EEPROMs 102_1 to 102_8 may be referred to as an EEPROM 102 when there is no need to distinguish them.

The EEPROM 102 recognizes its own address based on a level (HIGH level or LOW level) of a voltage applied to its own address terminals T_A0 to T_A2. In addition to the address terminals T_A0 to T_A2, the EEPROM 102 includes terminals T_SCL and T_SDA for I2C communication, and terminals T_Vcc, T_GND, and T_WP. The microcomputer 101 includes terminals T_SCL and T_SDA for I2C communication.

The EEPROM 102_1 recognizes its own address as 000 since a LOW level voltage is applied to its own address terminal T_A2, a LOW level voltage is applied to its own address terminal T_A1, and a LOW level voltage is applied to its own address terminal T_A0.

The EEPROM 102_2 recognizes its own address as 001 since a LOW level voltage is applied to its own address terminal T_A2, a LOW level voltage is applied to its own address terminal T_A1, and a HIGH level voltage is applied to its own address terminal T_A0.

The EEPROM 102 whose address matches 3-bit digital data in a slave address included in communication data output from the microcomputer 101 communicates with the microcomputer 101. In other words, the microcomputer 101 can select the EEPROM 102 communicating with the microcomputer 101, based on the 3-bit digital data in the slave address.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.

FIG. 1 is a diagram showing a configuration example of a conventional memory system.

FIG. 2 is a diagram showing a configuration of an EEPROM according to an embodiment.

FIG. 3 is a diagram showing a configuration of the EEPROM according to an embodiment.

FIG. 4 is a diagram showing a configuration of the EEPROM according to an embodiment.

FIG. 5 is a diagram showing a configuration example of a comparator.

FIG. 6 is a diagram showing a relationship between a resistance value of a pull-down resistor and an address.

FIG. 7 is a diagram showing a relationship between a resistance value of a pull-up resistor and a voltage of an address terminal when the resistance value of the pull-down resistor is set to each of eight types shown in FIG. 6.

FIG. 8 is a diagram showing a configuration example of the pull-up resistor.

FIG. 9 is a diagram showing another configuration example of the pull-up resistor.

FIG. 10 is a diagram showing a startup sequence of the EEPROM according to the embodiment.

FIG. 11 is a diagram showing a modification of the EEPROM according to the embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.

FIGS. 2 to 4 are diagrams showing a configuration of an EEPROM according to an embodiment. FIG. 2 is a diagram showing a state in which a pull-down resistor R2 is externally connected to an address terminal T_A of the EEPROM 1. FIG. 3 is a diagram showing a state in which a predetermined voltage VDD is applied to the address terminal T_A of the EEPROM 1. FIG. 4 is a diagram showing a state in which a ground voltage is applied to the address terminal T_A of the EEPROM 1.

The EEPROM 1 is an example of a semiconductor integrated circuit device. The semiconductor integrated circuit device is an electronic component formed by enclosing a semiconductor integrated circuit in a housing (package) made of resin. A plurality of terminals are provided to be exposed in the housing of the semiconductor integrated circuit device.

The EEPROM 1 includes a pull-up resistor R1, a filter circuit F1, an AD converter A1, a data processing part 3, a nonvolatile storage part 4, an address terminal T_A, terminals T_SCL and T_SDA for I2C communication, and terminals T_Vcc, T_GND, and T_WP.

A first end of the pull-up resistor R1 is connected to the address terminal T_A. A divided voltage VDD of a power supply voltage Vcc is applied to a second end of the pull-up resistor R1. In FIG. 2, a first end of the pull-down resistor R2 is connected to the address terminal T_A, and a ground voltage is applied to a second end of the pull-down resistor R2.

The AD converter A1 converts a voltage VA of the address terminal T_A into 3-bit digital data D1.

The data processing part 3 recognizes an address of the EEPROM 1 based on the digital data D1. The data processing part 3 communicates with an external device such as a microcomputer, and writes/reads data to/from the nonvolatile storage part 4.

The nonvolatile storage part 4 includes a plurality of memory cells (transistor cells) and stores data in a nonvolatile manner.

The filter circuit F1 is provided between the address terminal T_A and the AD converter A1. The filter circuit F1 is a low-pass filter including a resistor and a capacitor. By providing the filter circuit F1, it is possible to prevent an address from being erroneously recognized due to high-frequency noise flowing into the address terminal T_A.

The EEPROM 1 may set an address in one address terminal T_A. Accordingly, for example, when the EEPROM 1 is mounted on a DRAM module, the number of terminals of the DRAM module to which functions other than those related to the EEPROM can be assigned can be increased. Further, since the EEPROM 1 has one address terminal T_A, it can be enclosed by a package with a small number of terminals, thereby reducing the mounting area of a board on which internal components are mounted.

In this embodiment, the AD converter A1 is a flash type AD converter. The flash type AD converter has advantages of easy logic control and less influence of noise and interference. Further, unlike this embodiment, the AD converter A1 may have a configuration other than a flash type.

The AD converter A1, which is a flash type AD converter, includes comparators COMP1 to COMP9, a resistor ladder circuit including resistors R_LD1 to R_LD10, and an encoder 2.

The divided voltage VDD of the power supply voltage Vcc is applied to a first end of the resistor ladder circuit, and the ground voltage is applied to a second end of the resistor ladder circuit. The above-mentioned resistor ladder circuit generates a plurality of reference voltages VREF1 to VREF9 having different values at respective connection nodes between two resistors.

The divided voltage VDD of the power supply voltage Vcc applied to the first end of the pull-up resistor R1 and the divided voltage VDD of the power supply voltage Vcc applied to the first end of the resistor ladder circuit including the resistors R_LD1 to R_LD10 have the same voltage value. Therefore, for example, even if the power supply voltage Vcc fluctuates due to the influence of temperature, etc., the voltage VA of the address terminal T_A and the plurality of reference voltages VREF1 to VREF9 are similarly affected by the voltage fluctuation. As a result, the AD converter A1 may read the resistor value of the pull-down resistor R2 with high precision. Accordingly, a highly precise constant voltage circuit or constant current circuit is not required, so that the AD converter A1 can be implemented as a simple circuit configuration.

A comparator COMPk (k is any natural number from 1 to 9) compares the voltage VA of the address terminal T_A and a reference voltage VREFk. FIG. 5 is a diagram showing a configuration example of the comparator COMPk. The comparator COMPk in the configuration example shown in FIG. 5 is a chopper type comparator including switches SW1 to SW3 and inverters INV1 to INV3. The switch SW1 is controlled by a clock signal CLK1, and the switch SW2 is controlled by a clock signal CLK2. The clock signals CLK1 and CLK2 are adjusted so that the switches SW1 and SW2 are not turned on at the same time. The switch SW3 is an N-channel type MOS field effect transistor and is connected in parallel to the inverter INV1. The EEPROM 1 includes a bootstrap circuit B1 that supplies a gate signal to the switch SW3. The bootstrap circuit B1 receives, for example, the divided voltage VDD of the power supply voltage Vcc and uses a boot voltage, which is obtained by boosting the divided voltage VDD of the power supply voltage Vcc, as a HIGH level of the gate signal. By supplying the gate signal from the bootstrap circuit B1 to the switch SW3, the on-resistance of the switch SW3 can be reduced.

The encoder 2 converts each output of the comparators COMP1 to COMP9 into the 3-bit digital data D1. FIG. 6 is a diagram showing a relationship between the resistance value of the pull-down resistor R2 and the 3-bit digital data D1 (address). As can be seen from the relationship in FIG. 6, the address of the EEPROM 1 can be set by the resistance value of the pull-down resistor R2.

FIG. 7 is a diagram showing a relationship between the resistance value of the pull-up resistor R1 and the voltage VA of the address terminal T_A when the resistance value of the pull-down resistor R2 is set to each of eight types shown in FIG. 6. As can be seen from the relationship in FIG. 7, when the resistance value of the pull-up resistor R1 is set to 60 kΩ, the amount of change in the voltage VA of the address terminal T_A when the setting of the resistance value of the pull-down resistor R2 is sequentially switched becomes equal, thereby making it difficult for an address to be erroneously recognized. Therefore, in this embodiment, the resistance value of the pull-up resistor R1 is set to 60 kΩ.

The pull-up resistor R1 includes a trimmable configuration so that component variations in the pull-down resistor R2 or manufacturing process variations in the pull-up resistor R1 can be corrected.

FIG. 8 is a diagram showing a configuration example of the pull-up resistor R1. The pull-up resistor R1 includes resistors R11 to R14 and P-channel type MOS (Metal Oxide Semiconductor) field effect transistors Q1 to Q3. A parallel circuit is constituted by connecting, in parallel, a series circuit with the resistor R11 and the MOS field effect transistor Q1, a series circuit with the resistor R12 and the MOS field effect transistor Q2, and a series circuit with the resistor R13 and the MOS field effect transistor Q3. The parallel circuit is then connected in series to the resistor R14.

The nonvolatile storage part 4 stores trimming setting for the pull-up resistor R1. Specifically, the nonvolatile storage part 4 stores the level of each of gate signals of the MOS field effect transistors Q1 to Q3. The data processing part 3 controls the MOS field effect transistors Q1 to Q3 based on the trimming setting of the pull-up resistor R1 stored in the nonvolatile storage part 4.

For example, the pull-up resistor R1 may include a configuration as shown in FIG. 9, but in the case of the configuration shown in FIG. 9, when a plurality of MOS field effect transistors are turned on, an influence of the on-resistance of the plurality of MOS field effect transistors on the resistance value of the pull-up resistor R1 increases. Therefore, it is desirable for the pull-up resistor R1 to have the configuration as shown in FIG. 8.

As shown in FIG. 3, when the predetermined voltage VDD is applied to the address terminal T_A, the encoder 2 outputs a signal S1 corresponding to the predetermined voltage VDD. This facilitates a production test of the EEPROM 1. As shown in FIG. 3, when the predetermined voltage VDD is applied to the address terminal T_A, each of outputs of the comparators COMP1 to COMP9 becomes a LOW level. The encoder 2 outputs the signal S1 when each of the outputs of the comparators COMP1 to COMP9 is at the LOW level. The signal S1 is, for example, an analog voltage signal with the same voltage value as the power supply voltage Vcc.

As shown in FIG. 4, when the ground voltage is applied to the address terminal T_A, the encoder 2 outputs a signal S2 corresponding to the ground voltage. This facilitates the production test of the EEPROM 1. As shown in FIG. 4, when the ground voltage is applied to the address terminal T_A, each of the outputs of the comparators COMP1 to COMP9 becomes a HIGH level. The encoder 2 outputs the signal S2 when each of the outputs of the comparators COMP1 to COMP9 is at the HIGH level. The signal S2 is, for example, an analog voltage signal with the same voltage value as the ground voltage.

FIG. 10 is a diagram showing a startup sequence of the EEPROM 1. When the supply of the power supply voltage Vcc to the terminal T_Vcc is started, the EEPROM 1 shifts from a power-off state to a power-on state and generates a clock signal CLK using an internal oscillator. The EEPROM 1 operates based on the clock signal CLK.

After shifting from the power-off state to the power-on state, the EEPROM 1 first sets an enable signal EN as a HIGH level. An enable/disable changeover switch is provided between the pull-up resistor R1 and an application terminal to which the divided voltage VDD of the power supply voltage Vcc is applied, between the address terminal T_A and an application terminal to which the ground potential is applied, and between the resistor R_LD10 and an application terminal to which the divided voltage VDD of the power supply voltage Vcc is applied. The enable/disable changeover switch is turned on when the enable signal EN is at a HIGH level, and turned off when the enable signal EN is at a LOW level.

When the enable signal EN becomes the HIGH level, the comparators COMP1 to COMP9 sample the voltage VA of the address terminal T_A. After that, the comparator COMPk compares the voltage VA of the address terminal T_A and the reference voltage VREFk. After the comparison operation of the comparator COMPk is completed, the enable signal EN switches from the HIGH level to a LOW level.

<Others>

The embodiments of the present disclosure may be appropriately modified in various ways within the scope of the technical ideas shown in the claims. The various embodiments described so far may be appropriately combined and implemented unless contradictory. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.

In the above-described embodiments, the EEPROM 1 includes a configuration in which the pull-up resistor R1 is an internal resistor and the pull-down resistor R2 is connected externally, but as shown in FIG. 11, the EEPROM 1 may include a configuration in which the pull-down resistor R2 is an internal resistor and the pull-up resistor R1 is connected externally. In the configuration shown in FIG. 11, it is desirable that the pull-down resistor R2 is trimmable and the trimming setting is stored in the nonvolatile storage part 4. Further, it is desirable that a voltage applied to the first end of the pull-up resistor R1 has the same voltage value as a voltage applied to the first end of the resistor ladder circuit including the resistors R_LD1 to R_LD10. In the above-described embodiments, the AD converter A1 is a 3-bit AD converter, but it is not limited to 3 bits, and may be any multiple-bit AD converter. That is, the number of bits of the digital data D1 output from the AD converter A1 is not limited to 3 bits, but may be any plural number of bits.

In the above-described embodiments, the EEPROM has been described as an example, but the semiconductor integrated circuit device may be other than the EEPROM.

<Supplementary Notes>

Supplementary Notes are provided for the present disclosure in which specific configuration examples are shown in the above-described embodiments.

A semiconductor integrated circuit device (1) according to the present disclosure has a configuration (first configuration) that includes: a terminal (T_A); an internal resistor that is either a pull-up resistor (R1) including a first end which is connected to the terminal and a second end to which a first constant voltage is applied or a pull-down resistor (R2) including a first end which is connected to the terminal and a second end to which a ground voltage is applied; and an AD converter (COMP1 to COMP9, R_LD1 to R_LD10, 2) configured so that a voltage of the terminal is converted into digital data with a number of bits of 2 or more.

The semiconductor integrated circuit device of the first configuration may have a configuration (second configuration) that the internal resistor is configured to be trimmable, and the device further includes a nonvolatile storage part (4) configured to store trimming setting.

The semiconductor integrated circuit device of the first or second configuration may have a configuration (third configuration) that the AD converter includes: a resistor ladder circuit (COMP1 to COMP9) configured to generate a plurality of reference voltages; a plurality of comparators (R_LD1 to R_LD10) configured to compare the voltage of the terminal and each of the plurality of reference voltages; and an encoder (2) configured to convert each of outputs of the plurality of comparators into the digital data.

The semiconductor integrated circuit device of the third configuration may have a configuration (fourth configuration) that the internal resistor is the pull-up resistor, and the first constant voltage and a second constant voltage applied to a first end of the resistor ladder circuit have the same voltage value.

The semiconductor integrated circuit device of the third configuration may have a configuration (fifth configuration) that the internal resistor is the pull-down resistor, the pull-up resistor is externally connected to the terminal, and the first constant voltage and a second constant voltage applied to a first end of the resistor ladder circuit have the same voltage value.

The semiconductor integrated circuit device of any one of the third to fifth configurations may have a configuration (sixth configuration) that if a predetermined voltage is applied to the terminal, the encoder is configured to output a signal corresponding to the predetermined voltage.

The semiconductor integrated circuit device of any one of the third to sixth configurations may have a configuration (seventh configuration) that when the ground voltage is applied to the terminal, the encoder is configured to output a signal corresponding to the ground voltage.

The semiconductor integrated circuit device of any one of the third to seventh configurations may have a configuration (eighth configuration) that each of the plurality of comparators is a chopper type comparator, and the device further includes: a bootstrap circuit (B1) configured to supply a boot voltage to a gate of a switch (SW3) which is an NMOS transistor provided in the chopper type comparator.

The semiconductor integrated circuit device of any one of the third to eighth configurations may have a configuration (ninth configuration) that the device further includes a filter circuit (F1) provided between the terminal and the AD converter.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.

Claims

1. A semiconductor integrated circuit device comprising: a terminal;an internal resistor that is either a pull-up resistor including a first end which is connected to the terminal and a second end to which a first constant voltage is applied or a pull-down resistor including a first end which is connected to the terminal and a second end to which a ground voltage is applied; andan AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

2. The semiconductor integrated circuit device of claim 1, wherein the internal resistor is configured to be trimmable, and wherein the device further comprises:a nonvolatile storage part configured to store trimming setting.

3. The semiconductor integrated circuit device of claim 1, wherein the AD converter includes: a resistor ladder circuit configured to generate a plurality of reference voltages;a plurality of comparators configured to compare the voltage of the terminal and each of the plurality of reference voltages; andan encoder configured to convert each of outputs of the plurality of comparators into the digital data.

4. The semiconductor integrated circuit device of claim 3, wherein the internal resistor is the pull-up resistor, and wherein the first constant voltage and a second constant voltage applied to a first end of the resistor ladder circuit have the same voltage value.

5. The semiconductor integrated circuit device of claim 3, wherein the internal resistor is the pull-down resistor, wherein the pull-up resistor is externally connected to the terminal, andwherein the first constant voltage and a second constant voltage applied to a first end of the resistor ladder circuit have the same voltage value.

6. The semiconductor integrated circuit device of claim 3, wherein if a predetermined voltage is applied to the terminal, the encoder is configured to output a signal corresponding to the predetermined voltage.

7. The semiconductor integrated circuit device of claim 3, wherein if the ground voltage is applied to the terminal, the encoder is configured to output a signal corresponding to the ground voltage.

8. The semiconductor integrated circuit device of claim 3, wherein each of the plurality of comparators is a chopper type comparator, and the device further comprises:a bootstrap circuit configured to supply a boot voltage to a gate of a switch which is an NMOS transistor provided in the chopper type comparator.

9. The semiconductor integrated circuit device of claim 3, further comprising: a filter circuit provided between the terminal and the AD converter.