TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device which operates in synchronism with a clock, and more particularly to a semiconductor integrated circuit device which is capable of changing at least one of a power supply voltage, a clock frequency, and a threshold value.
BACKGROUND ART
Semiconductor integrated circuit devices which are predominant at present comprise an integrated assembly of CMOS (Complementary Metal-Oxide Semiconductor) transistors. The semiconductor integrated circuit device has such a tendency that its power consumption increases as the number of transistors which makes up the semiconductor integrated circuit increases. There has been a strong demand for a reduction in the power consumption of the semiconductor integrated circuit device. With the development in recent years of the low-power CMOS device technology, there has been proposed a power supply control scheme for reducing the power consumption of a semiconductor integrated circuit device by supplying a required minimum power supply voltage to each circuit block of the semiconductor integrated circuit device. For example, T. Kuroda et al. have proposed a power supply control scheme for dynamically controlling a power supply voltage in order to equalize a critical path delay to a lower limit entering a clock cycle in a semiconductor integrated circuit device [T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama; “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 454-462, March 1998]. In the semiconductor integrated circuit device to which the scheme of Kuroda et al. is applied, a reference current for controlling a threshold voltage is fixed to a leak current value as a target in a transistor device. Therefore, there is no optimization of the threshold voltage in this semiconductor integrated circuit device.
With semiconductor devices being progressively scaled, the proportion of a leakage power in the total power consumption of a semiconductor device is growing. The leakage power refers to an electric power consumed due to a leakage current in the semiconductor device. K. Nose et al. have reported that it is effective to set the proportion of a leakage power in the total power to 30% at maximum [K. Nose, and T. Sakurai; “Optimization Of VDD and VTH for Low-Power and High-Speed Applications,” ASP-DAC, pp. 469-474, January 2000]. The results accomplished by K. Nose et al. are based on a theoretical analysis, and they have not clearly specified how to realize such a semiconductor integrated circuit device.
JP-A-2001-345693 discloses a semiconductor integrated circuit device in which an association table (TBL) representing a combination of clock frequencies, power supply voltages, and substrate bias voltages is prepared in advance, and the clock frequency, power supply voltage, and substrate bias voltage can be controlled by referring to the association table. It should be noted that JP-A-2001-345693 corresponds to the specifications of U.S. Pat. No. 6,774,705 and U.S. Pat. No. 6,943,613.
DISCLOSURE OF THE INVENTION
Problems to be Solved by the Invention
For reducing the power consumption of a semiconductor integrated circuit device, it is important not only to control a power supply voltage, but also to control a threshold voltage. In the semiconductor integrated circuit device disclosed in JP-A-2001-345693, the power supply voltage and the substrate bias voltage are controlled, and the substrate bias voltage is controlled to change the threshold voltage. However, the disclosed semiconductor integrated circuit device is problematic in that since the association table is employed, data relative to a combination of power supply voltages and substrate bias voltages are required in advance. The power supply voltage and the substrate bias voltage for minimizing the power consumption of the semiconductor integrated circuit device differ from semiconductor integrated circuit device to semiconductor integrated circuit device due to various factors involved in the fabrication process for semiconductor integrated circuit devices.
Therefore, the data of the association table need to be determined based on actually measured values. Preparing a large amount of association table data greatly complicates the fabrication process for semiconductor integrated circuit devices, and increases the manufacturing cost of the semiconductor integrated circuit devices.
It is an object of the present invention to provide a semiconductor integrated circuit device which is capable of optimizing a power supply voltage and a threshold voltage for minimizing an operational power with respect to a given operation clock frequency either without an association table or with a small number of association table data.
Means for Solving the Problems
A semiconductor integrated circuit device according to the present invention includes: switching current observation means for observing a switching current in the semiconductor integrated circuit device; leakage current observation means for observing a leakage current in the semiconductor integrated circuit device; comparing means for comparing the switching current and the leakage current with each other; and threshold voltage control means for controlling a threshold voltage of a circuit element of the semiconductor integrated circuit device to make the ratio of the switching current and the leakage current constant.
In the semiconductor integrated circuit device, it is possible to minimize the operating power by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency.
Another semiconductor integrated circuit device according to the present invention includes: switching current observation means for observing a switching current in the semiconductor integrated circuit device; leakage current observation means for observing a leakage current in the semiconductor integrated circuit device; comparing means for comparing the switching current and the leakage current with each other; threshold voltage control means for controlling a threshold voltage of a circuit element of the semiconductor integrated circuit device to make the ratio of the switching current and the leakage current constant; delay observation means for observing a delay amount in the semiconductor integrated circuit device; and power supply voltage control means for controlling a power supply voltage used to operate the semiconductor integrated circuit device in order to keep the delay amount in a predetermined range.
In the semiconductor integrated circuit device, the threshold voltage is controlled to make the ratio of the switching current and the leakage current constant at a given clock frequency, and the power supply voltage is controlled to guarantee the operating speed, thus making it possible to minimize the operating power while guaranteeing the operating speed.
In the present invention, the switching current observation means, the leakage current observation means, and the delay observation means comprise circuit elements that are identical in construction to those used in each of circuit blocks for performing functions of the semiconductor integrated circuit device, for example. The switching current observation means, the leakage current observation means, and the delay observation means should preferably be fabricated, in the semiconductor integrated circuit device, simultaneously with those circuit blocks by the same fabrication process as each circuit block. With this arrangement, the switching current observed by the switching current observation means, the leakage current observed by the leakage current observation means, and the delay amount observed by the delay observation means are representative of switching currents, leakage currents, and delay amounts in the respective circuit blocks of the semiconductor integrated circuit device regardless of manufacturing variations of the semiconductor integrated circuit device.
In the present invention, circuit elements to be controlled for the threshold voltage are, for example, a pMOS transistor and an nMOS transistor in the semiconductor integrated circuit device. By controlling substrate bias voltages of the semiconductor integrated circuit device, e.g., by controlling a bias voltage VPW applied to a p-well formed in the substrate and a bias voltage VNW applied to an n-well formed in the substrate, the threshold voltages of these transistors can be varied. If these transistors are floating gate transistors, then the threshold voltage control means may vary the floating gate voltages of those transistors. If these transistors are multigate structure transistors, then the threshold voltage control means may vary the voltages of some gates of the plural gates of the transistors.
When the power supply voltage VDD of the semiconductor integrated circuit device is controlled, the voltage difference between the substrate voltage and the source voltage (VDD) of the pMOS transistor is varied. The substrate voltage of the pMOS transistor is the bias voltage VNW applied to the n-well. The threshold value of the PMOS transistor can also be varied when the power supply voltage is controlled to vary the potential difference between the substrate voltage and the source voltage. Similarly, when the GND power supply voltage is controlled, the voltage difference between the substrate voltage and the source voltage (GND) of the nMOS transistor is varied. Here, the substrate voltage of the nMOS transistor is the bias voltage VPW applied to the p-well. The threshold value of the nMOS transistor can also be varied by controlling the GND power supply voltage.
According to the present invention, the threshold voltage is dynamically controlled to keep the ratio of the leakage current and the switching current constant, thereby making it possible to achieve a ratio for minimizing the operational power at all times depending on changes in operational environments including the temperature, the power supply voltage, the operating frequency, etc. According to the present invention, therefore, there is provided a semiconductor integrated circuit device which is capable of minimizing the operational power by keeping the ratio of the leakage current and the switching current constant.
As a result of dynamically controlling the threshold voltage as described above, it is possible to reduce adverse effects of process variations and changes in operational environments including the temperature, the power supply voltage, etc. According to the present invention, therefore, there is provided a semiconductor integrated circuit device which is capable of reducing effects of variations caused by the fabrication process, the temperature, the power supply voltage, etc. by keeping the ratio of the leakage current and the switching current constant.
According to the present invention, furthermore, the delay observation means and the power supply voltage control means are provided, and the power supply voltage control means is controlled preferentially with respect to the threshold voltage control means to supply a power supply voltage for maintaining, at all times, an operating condition in which a critical path delay is smaller than a necessary clock cycle. According to the present invention, therefore, there is provided a semiconductor integrated circuit device which is capable of keeping a speed performance required by a circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a first exemplary embodiment of the present invention;
FIG. 2 is a flowchart showing an operation sequence of the semiconductor integrated circuit device according to the first exemplary embodiment;
FIG. 3 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a second exemplary embodiment of the present invention;
FIG. 4 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a third exemplary embodiment of the present invention;
FIG. 5 is a flowchart showing an operation sequence of the semiconductor integrated circuit device according to the third exemplary embodiment;
FIG. 6 is a flowchart showing another operation sequence of the semiconductor integrated circuit device according to the third exemplary embodiment;
FIG. 7 is a flowchart showing still another operation sequence of the semiconductor integrated circuit device according to the third exemplary embodiment;
FIG. 8 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a fourth exemplary embodiment of the present invention;
FIG. 9 is a circuit diagram showing an example of a switching current observer;
FIG. 10 is a circuit diagram showing another example of the switching current observer;
FIG. 11 is a circuit diagram showing still another example of the switching current observer;
FIG. 12 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 11;
FIG. 13 is a circuit diagram showing yet another example of the switching current observer;
FIG. 14 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 13;
FIG. 15 is a circuit diagram showing yet still another example of the switching current observer;
FIG. 16 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 15;
FIG. 17 is a circuit diagram showing a further example of the switching current observer;
FIG. 18 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 17;
FIG. 19 is a circuit diagram showing a still further example of the switching current observer;
FIG. 20 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 19;
FIG. 21 is a circuit diagram showing a yet still further example of the switching current observer;
FIG. 22 is a timing chart showing an operation sequence of the switching current observer shown in FIG. 21;
FIG. 23 is a circuit diagram showing an example of a reference current generator;
FIG. 24 is a circuit diagram showing another example of the control logic circuit in the reference current generator;
FIG. 25 is a circuit diagram showing another example of the switching current observer;
FIG. 26 is a circuit diagram showing still another example of the switching current observer;
FIG. 27 is a circuit diagram showing an arrangement of a switching current-leakage current comparing semiconductor integrated circuit device based on the present invention;
FIG. 28 is a circuit diagram showing an example of a leakage current observer;
FIG. 29 is a circuit diagram showing another example of the leakage current observer;
FIG. 30 is a circuit diagram showing still another example of the leakage current observer;
FIG. 31 is a circuit diagram showing yet another example of the leakage current observer;
FIG. 32 is a circuit diagram showing yet still another example of the leakage current observer;
FIG. 33 is a circuit diagram showing a further example of the leakage current observer;
FIG. 34 is a circuit diagram showing a still further example of the leakage current observer;
FIG. 35 is a circuit diagram showing a yet further example of the leakage current observer;
FIG. 36 is a circuit diagram showing a yet still further example of the leakage current observer;
FIG. 37 is a circuit diagram showing still another example of the leakage current observer;
FIG. 38 is a circuit diagram showing an another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device based on the present invention;
FIG. 39 is a circuit diagram showing still another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device;
FIG. 40 is a circuit diagram showing yet another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device;
FIG. 41 is a circuit diagram showing yet still another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device;
FIG. 42 is a circuit diagram showing a further example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device;
FIG. 43 is a circuit diagram showing yet another example of the leakage current observer;
FIG. 44 is a circuit diagram showing yet still another example of the leakage current observer;
FIG. 45 is a circuit diagram showing an arrangement of a delay observer and a control switcher;
FIG. 46 is a timing chart showing an operation sequence of a delay measurer and the control switcher in the circuit shown in FIG. 45;
FIG. 47 is a graph showing the relationship between an operational current, and a switching current and a leakage current which are components of the operational current at a constant operational rate;
FIG. 48 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a fifth exemplary embodiment of the present invention;
FIG. 49 is a block diagram showing an arrangement of a semiconductor integrated circuit device according to a sixth exemplary embodiment of the present invention;
FIG. 50 is a block diagram showing an example of a threshold value compensator;
FIG. 51 is a block diagram showing an arrangement of an additional portion of the control switcher;
FIG. 52 is a block diagram showing another example of the arrangement of the additional portion of the control switcher;
FIG. 53 is a circuit diagram showing a delay measurer and a control switcher;
FIG. 54 is a truth table showing an operation sequence of the delay measurer and the control switcher in the circuit shown in FIG. 53; and
FIG. 55 is a timing chart showing the operation sequence of the delay measurer and the control switcher in the circuit shown in FIG. 53.
DESCRIPTION OF REFERENCE CHARACTERS
1 Switching current observer
2 Leakage current observer
3, 61, 63, 631 to 636 Comparator
4 Threshold voltage controller
5 Delay observer
6 Power supply voltage controller
8 Power supply line
9 Substrate bias line
10 Control switcher
20 Selector switch
21 Precharging pMOS transistor
22 Capacitor (C)
23 Precharging nMOS transistor
24 Reference current generating circuit
25 Comparing circuit
26, 53 Register (REG)
27 Leakage current generating circuit
28 Reference current generating circuit
40 Threshold voltage compensator
41 Reference current source
42, 276 pMOS current mirror circuit
43, 275 nMOS current mirror circuit
44 pMOS switch
45 nMOS switch
46, 64 Control unit
47 Shift register unit
48 Counter unit
49 External setting signal
51 Critical path circuit
52 Delay circuit
54 Control circuit
63 Holding unit
241 to 243, 271, 273, 281 to 283 nMOS transistor
244 to 246, 272, 274, 284 to 286 pMOS transistor
277 Differential amplifier
611, 612 A/D (analog/digital) converter
613 Subtractor
621, 623, 625 Upper limit data holding unit
622, 624, 626 Lower limit data holding unit
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred exemplary embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows an overall arrangement of a semiconductor integrated circuit device according to a first exemplary embodiment of the present invention. The semiconductor integrated circuit device includes power supply line 8 for being supplied with power supply voltage VDD and substrate bias line 9 for supplying substrate bias potentials VPW, VNW into a semiconductor integrated circuit. Though not shown, the semiconductor integrated circuit device includes a circuit function part for realizing functions to be originally performed by the semiconductor integrated circuit device, as a CMOS logic circuit. Power supply line 8 supplies a power supply voltage to the circuit function part for operating the circuit function part. The circuit function part includes p-well regions and n-well regions formed in a semiconductor substrate, for example. Substrate bias line 9 applies a substrate bias voltage to these well regions. The circuit function part is also supplied with clock signal CLK as an operating clock. If the semiconductor integrated circuit device includes a plurality of circuit blocks each controlled for power consumption, then each of these circuit blocks corresponds to the circuit function part.
The semiconductor integrated circuit device also includes: switching current observer 1 for being supplied with power supply voltage VDD and clock signal CLK and observing a switching current in the semiconductor integrated circuit device; leakage current observer 2 for being supplied with power supply voltage VDD and substrate bias potentials VPW, VNW and observing a leakage current in the semiconductor integrated circuit device; comparator (comparing circuit) 3 for comparing the switching current and the leakage current with each other; threshold voltage controller 4 for controlling the threshold voltage of each of MOS transistors of the semiconductor integrated circuit device to keep constant the ratio of the switching current and the leakage current; delay observer 5 for being supplied with power supply voltage VDD and substrate bias potentials VPW, VNW and observing a delay amount in the semiconductor integrated circuit device; and power supply voltage controller 6 for controlling the power supply voltage used to operate the semiconductor integrated circuit device to keep the delay amount in a predetermined range. Threshold voltage controller 4 controls the threshold voltage by varying the potential of substrate bias line 9. Power supply voltage controller 6 varies power supply voltage VDD supplied to power supply line 8. Comparator 3 is also supplied with power supply voltage VDD for use as a reference for the comparing operation of comparator 3.
Each of switching current observer 1, leakage current observer 2, and delay observer 5 has circuit elements that are identical in construction to those used in the circuit function part, and is fabricated simultaneously with the circuit function part in the semiconductor integrated circuit device by the same fabrication process as with the circuit function part. Therefore, though switching current observer 1 does not measure an actual switching current in the circuit function part, it can observe a switching current which is substantially the same as the switching current in the circuit function part. Similarly, leakage current observer 2 observes a leakage current which is substantially the same as a leakage current in the circuit function part, and delay observer 5 observes a delay amount which is substantially the same as a signal delay amount in the circuit function part. When power supply voltage VDD at power supply line 8 or substrate bias potentials VPW, VNW at substrate bias line 9 vary or the frequency of clock signal CLK varies, the switching current, the leakage current, and the delay amount in the circuit function part also vary. The switching current observed by switching current observer 1, the leakage current observed by leakage current observer 2, and the delay observed by delay observer 5 also vary in response to these changes at the circuit function part.
In the semiconductor integrated circuit device, comparator 3 performs comparison to ascertain whether the ratio of the results observed by switching current observer 1 and leakage current observer 2 is of a predetermined value or not, and threshold voltage controller 4 controls the threshold voltage (i.e., the substrate bias potentials) to cause the switching current and the leakage current to have a constant ratio. Delay observer 5 performs observation to ascertain whether a critical path delay falls in an operating clock period or not. Depending on the observed result, power supply voltage observer 6 controls power supply voltage VDD of power supply line 8 such that the critical path delay is smaller than the operating clock period and power supply voltage VDD is as low as possible.
Operation of the semiconductor integrated circuit device will be described below with reference to a flowchart shown in FIG. 2. FIG. 2 shows a sequence for controlling power supply voltage VDD and threshold voltage Vt depending on the operation clock.
In Step 11, power supply voltage VDD and threshold voltage Vt are set to initial values. The initial values may be standard values, or values for guaranteeing normal operation, or a maximum power supply voltage and a minimum threshold voltage, respectively. In Step 12, clock signal CLK is supplied to delay observer 5. In Step 15, delay observer 5 determines whether the delay amount is appropriate or not, i.e., whether the critical path delay is smaller than the clock period or not. If the critical path delay is smaller than the clock period, then the circuit to be controlled is in an operable state and can start to operate.
If the delay amount is not appropriate in Step 15, then control goes to Step 14 in which power supply voltage controller 6 controls power supply voltage VDD to equalize the critical path delay to a lower limit smaller than the clock period with respect to the transistor of the threshold voltage at the time. Then, control goes back to Step 15. On the contrary, if the delay amount is appropriate in Step 15, then comparator 3 determines in Step 16 whether ratio ILEAK/ISW of leakage current ILEAK and switching current ISW is a predetermined ratio, i.e., a target value, with respect to the operating frequency and the power supply voltage. If ratio ILEAK/ISW is the predetermined ratio, then the sequence is put to an end. Otherwise, control goes to Step 13 in which threshold voltage controller 4 controls threshold voltage Vth to equalize the ratio of the leakage current and the switching current to the target value at this time. If ratio ILEAK/ISW is of a constant value determined by the operating frequency and the power supply voltage at the time, then the semiconductor integrated circuit device is now in a state capable of operating with lower electric power. After Step 13 is executed, control goes to Step 14.
A synchronous circuit has an essential requirement for rate guarantee, and needs to satisfy the condition that a critical path delay is smaller than a clock period under threshold voltage control. Therefore, after Step 13 is executed, control goes to Step 14. If the operating clock frequency varies, particularly if the frequency becomes higher, then it is preferable to shut down the circuit to be controlled, and to resume its operation after it is confirmed that the critical path delay is smaller than the clock period and the semiconductor integrated circuit device is in the operable state.
In the present exemplary embodiment, if a transistor of the semiconductor integrated circuit device is a floating gate transistor, then threshold voltage controller 4 may vary the threshold value by varying the floating gate voltage of the floating gate transistor. If a transistor of the semiconductor integrated circuit device is a multigate structure transistor, then threshold voltage controller 4 may vary the threshold value by varying the voltage of one or some of the gates of the transistor.
A second exemplary embodiment of the present invention will be described below. FIG. 3 shows an overall arrangement of a semiconductor integrated circuit device according to the second exemplary embodiment. The semiconductor integrated circuit device shown in FIG. 3 is of an arrangement formed by removing delay observer 5 and power supply voltage controller 6 from the semiconductor integrated circuit device shown in FIG. 1. The semiconductor integrated circuit device is given power supply voltage VDD together with clock signal CLK (frequency f). Based on the results observed by switching current observer 1 and leakage current observer 2, comparator 3 compares them to ascertain whether the ratio of the switching current and the leakage current is of a predetermined value or not, and threshold voltage controller 4 controls the threshold voltage such that the ratio of the leakage current and the switching current is the predetermined value.
A third exemplary embodiment of the present invention will be described below. FIG. 4 shows an overall arrangement of a semiconductor integrated circuit device according to the third exemplary embodiment. In the semiconductor integrated circuit device according to the first exemplary embodiment shown in FIG. 1, threshold voltage controller 4 and power supply voltage controller 6 can independently control the operation. The semiconductor integrated circuit device according to the third exemplary embodiment includes control switcher 10 which performs switching operation to prioritize one of the power supply voltage control and the threshold voltage control. It is assumed that the threshold voltage control is performed only if the operating speed satisfies a certain rate performance, i.e., if the operating speed satisfies tD1<Tclk<tD2. If the operating speed fails to satisfy the rate performance, i.e., if Tclk<tD0 or tD3<Tclk, because the threshold voltage control has been carried out or because of a temperature change, then the power supply voltage control is carried out. Since control switcher 10 switches exclusively between the power supply voltage control and the threshold voltage control, the control system maintains its stability. Here, the clock period is represented by Tclk, the critical path delay by tD-1, a margin D0 added delay by tD0, a margin D1 added delay by tD1, a margin D2 added delay by tD2, and a margin D3 added delay by tD3.
FIG. 5 is a flowchart showing an operation sequence of the semiconductor integrated circuit device shown in FIG. 4. After Steps 11, 12 are executed in the same manner as shown in FIG. 2, it is determined whether tD1<Tclk<tD2 is satisfied or not in Step 151. If it is satisfied, the threshold voltage control is carried out in Step 13. Then, it is determined whether a deviation occurs from the rate performance in Step 152. If Tclk<tD0 or tD3<Tclk, then it is judged that a deviation occurs from the rate performance. If a deviation occurs from the rate performance, then control goes back to Step 151. If no deviation occurs, then control may go back to Step 13. If tD1<Tclk<tD2 is not satisfied in Step 151, then the power supply voltage control is carried out in Step 14, after which Step 151 is executed again.
In the third exemplary embodiment, control switcher 10 may output operability signal Ready under the condition that the critical path delay is smaller than the clock period (tD-1<Tclk). If ratio ILEAK/ISW of switching current (ISW) and leakage current (ILEAK) is appropriate, then control switcher 10 may output high-power-efficiency signal ECO. FIG. 6 is a flowchart showing an operation sequence for such a case. According to the operation sequence shown in FIG. 6, Step 153 for determining whether tD-1<Tclk is satisfied or not is added before Step 151 of the operation sequence shown in FIG. 5. If tD-1<Tclk is satisfied, then Ready=1 in Step 171, and thereafter Step 151 is executed. If tD-1<Tclk is not satisfied, then Ready=0 in Step 172, and thereafter Step 151 is executed. Step 16 for determining whether ratio ILEAK/ISW is of an appropriate value or not is added before Step 152. If ratio ILEAK/ISW is of an appropriate value, then ECO=1 in Step 181, and thereafter Step 152 is executed. If ratio ILEAK/ISW is not of an appropriate value, then ECO=0 in Step 182, and thereafter Step 152 is executed.
If the power supply voltage reaches a control limit (an upper limit or a lower limit) in the power supply control, then in case rate priority is given, the power supply control may switch to the threshold voltage control to realize the necessary rate performance. FIG. 7 is a flowchart showing an operation sequence for performing such control. The operation sequence shown in FIG. 7 includes Step 19 for determining whether power supply voltage VDD is between predetermined upper and lower limits or not, Step 19 being added after Step 172 and before Step 151 in the operation sequence shown in FIG. 6. If the power supply voltage is in the range between the upper and lower limits in Step 19, control goes to Step 151. Otherwise, the threshold voltage control is carried out in Step 131, after which control returns to Step 153.
In the third exemplary embodiment, the above control process may be dispensed with, and the control switcher may simply switch alternately between the power supply voltage control and the threshold voltage control.
A fourth exemplary embodiment of the present invention will be described below. FIG. 8 shows an overall arrangement of a semiconductor integrated circuit device according to the fourth exemplary embodiment. The semiconductor integrated circuit device shown in FIG. 8 is of an arrangement formed by removing switching current observer 1, leakage current observer 2, comparator 3, and delay observer 5 from the semiconductor integrated circuit device shown in FIG. 4, and comprises threshold voltage controller 4, power supply voltage controller 6, and control switcher 10 as major components. In this semiconductor integrated circuit device, control switcher 10 switches exclusively between the threshold voltage control and the power supply voltage control to guarantee the stability of the control system.
Structural details of the semiconductor integrated circuit devices according to the above exemplary embodiments will be described below.
FIG. 9 shows an example of an arrangement of switching current observer 1. Switching current observer 1 includes precharging pMOS transistor 21 and capacitor (C) 22 that are connected in series to each other with respect to power supply voltage VDD. The period of a half cycle of clock signal CLK is used as an evaluation period after capacitor C is precharged or predischarged. For detecting whether the potential of capacitor C is VDD/2 or not in the evaluation period after capacitor C is precharged, the circuit is equivalent to a current source of C×VDD×f, which is regarded as representing switching current ISW, where f indicates the frequency of clock signal CLK (clock frequency). For detecting whether the potential of capacitor C is VDD/2 or not in the evaluation period after capacitor C is predischarged, the switching current observer may be of an arrangement including precharging nMOS transistor 23 and capacitor (C) 22 that are connected parallel to each other, as shown in FIG. 10.
As still another example, switching current observer comprises precharging PMOS transistor 21, capacitor (C) 22, reference current generating circuit 24 for generating reference current IREF, comparing circuit 25, and register (REG) 26, as shown in FIG. 11. In this circuit, pMOS transistor 21 and capacitor 22 are connected in series to each other between power supply voltage VDD and the ground potential, and reference current generating circuit 24 is connected parallel to capacitor C. Comparing circuit 25 compares voltage VA at a junction (comparison node) between pMOS transistor 21 and capacitor 22 with a one-half value of power supply voltage VDD, i.e., VDD/2. The comparison result is read into register 26 in synchronism with clock signal CLK. The value of reference current IREF increases or decreases depending on the comparison result.
FIG. 12 is a timing chart showing an operation sequence of the circuit shown in FIG. 11.
Periods in which clock signal CLK is low are precharging periods during which comparison node voltage VA changes to power supply voltage VDD. During evaluation periods after the precharging periods, comparison node voltage VA drops depending on capacitor C and reference current IREF. Comparing circuit 25 compares VA and VDD/2 with each other for their magnitude. After T/2, i.e., at a negative-going edge of clock signal CLK, register 26 latches the comparison result. T represents the time of one periodic cycle of clock signal CLK. If the register data is high, an Up/Down signal goes Up, increasing reference current IREF. If the register data is low, an Up/Down signal goes Down, decreasing reference current IREF. The signal flows through the feedback loop each time a clock pulse is applied. However, if the response of the circuit, particularly the response of reference current generating circuit 24, is slow, then it is necessary to decimate the reading of the Up/Down control signal in order to keep the circuit stable in operation.
Similarly, as shown in FIG. 13, switching current observer may comprise capacitor (C) 22, predischarging nMOS transistor 23 connected parallel to capacitor (C), reference current generating circuit 24 for generating reference current IREF, comparing circuit 25, and register 26. Reference current IREF generated by reference current generating circuit 24 is supplied to the parallel-connected assembly of capacitor (C) 22 and nMOS transistor 23. FIG. 14 is a timing chart showing an operation sequence of the circuit shown in FIG. 13. Periods in which clock signal CLK is high are predischarging periods during which comparison node voltage VA changes to ground potential GND. During evaluation periods after the predischarging periods, comparison node voltage VA rises depending on capacitor C and reference current IREF. Comparing circuit 25 compares VA and VDD/2 with each other for their magnitude. After T/2, i.e., at a positive-going edge of clock signal CLK, register 26 latches the comparison result. If the register data is high, an Up/Down signal goes Down, decreasing reference current IREF. If the register data is low, an Up/Down signal goes Up, increasing reference current IREF. As with the case shown in FIG. 12, if the response of the circuit, particularly the response of reference current generating circuit 24, is slow, then it is necessary to decimate the reading of the Up/Down control signal in order to keep the circuit stable in operation.
FIG. 15 shows yet still another example of the arrangement of the switching current observer. The circuit shown in FIG. 15 includes two comparing circuits 25 in the circuit shown in FIG. 11. One of the comparing circuits compares reference voltage VDD/2+Δ with VA and generates an Up signal. The other comparing circuit compares reference voltage VDD/2−Δ with VA and generates a Down signal.
FIG. 16 is a timing chart showing an operation sequence of the circuit shown in FIG. 15. In the circuit shown in FIG. 15, Up and Down signals are separately generated to provide a hold state. If VA is between VDD/2−Δ and VDD/2−Δ at a negative-going edge of clock signal CLK, then the circuit is in the hold state.
Likewise, as shown in FIG. 17, the arrangement shown in FIG. 13 may include two comparing circuits 25. FIG. 18 is a timing chart showing an operation sequence of the circuit shown in FIG. 17. In this circuit, Up and Down signals are also separately generated. If VA is between VDD/2−Δ and VDD/2−Δ at a positive-going edge of clock signal CLK, then the circuit is in the hold state.
FIG. 19 shows a still further example of the arrangement of the switching current observer. The circuit shown in FIG. 19 comprises two sets of circuits each shown in FIG. 11, providing a current mirror circuit. One of the circuits uses reference current IREF/α to generate an Up signal, and the other circuit uses reference current IREF·α to generate a Down signal. The comparison node voltage in one of the circuits is represented by VA, whereas the comparison node voltage in the other circuit by VB. Here, nMOS transistors 241 to 243 make up a current mirror. Reference current IREF generated by reference current generating circuit 24 flows through nMOS transistor 241, causing nMOS transistor 242 of one of the circuits to generate reference current IREF/α, and causing nMOS transistor 243 of the other circuit to generate reference current IREF·α.
FIG. 20 is a timing chart showing an operation sequence of the circuit shown in FIG. 19. In the circuit shown in FIG. 19, Up and Down signals are also separately generated to provide a hold state.
Similarly, an arrangement shown in FIG. 21 includes two sets of circuits each shown in FIG. 13, providing a current mirror circuit wherein one of the circuits uses reference current IREF/α to generate an Up signal, and the other circuit uses reference current IREF·α to generate a Down signal. Here, pMOS transistors 244 to 246 make up a current mirror. FIG. 22 is a timing chart showing an operation sequence of the circuit shown in FIG. 21. In the circuit shown in FIG. 21, Up and Down signals are also separately generated to provide a hold state.
Exemplary arrangements of reference current generating circuit 24 used in the above switching current observers will be described below.
As shown in FIG. 23, reference current generating circuit 24 comprises reference current source 41, current mirror arrays 42, 43, current switch arrays 44, 45, and control logic circuit 46. The total current can be controlled by controlling the turn-on and turn-off of current switch arrays 44, 45. A current value can be set by external setting signals 49. Control logic circuit 46 includes shift registers 47 for shifting up 1 or shifting down 0 depending on the Up/Down signal to increase or decrease the reference current value.
Similarly, as shown in FIG. 24, control logic circuit 46 may be of an arrangement including counter 48. Clock signal CLK0 for controlling the registers is either identical to clock signal CLK of switching current observer 1 or a clock signal having a frequency lower than clock signal CLK, and is determined to satisfy the stability of the feedback loop.
Further, another example of the arrangement of switching current observer 1 will be described below. FIG. 25 shows a switching current observer comprising a plurality of unit circuits each including precharging pMOS transistor 21, capacitor (C) 22, reference current generating circuit 28 for generating a reference current, comparing circuit 25, and register 26. In each of the unit circuits, pMOS transistor 21 and capacitor 22 are connected in series to each other between power supply voltage VDD and the ground potential, and reference current generating circuit 28 is connected parallel to capacitor C. Comparing circuit 25 compares voltage VA at a junction (comparison node) between pMOS transistor 21 and capacitor 22 with a one-half value of power supply voltage VDD, i.e., VDD/2. The comparison result is read into register 26 in synchronism with clock signal CLK. The reference current value generated by reference current generating circuit 28 differs from unit circuit to unit circuit. Reference currents provided at a plurality of levels allow a bit string to be generated depending on the switching current.
Similarly, in a switching current observer shown in FIG. 26, each unit circuit comprises capacitor (C) 22, precharging nMOS transistor 23 connected parallel to capacitor C, reference current generating circuit 24 for generating reference current IREF, comparing circuit 25, and register 26. Reference current IREF generated by reference current generating circuit 24 is supplied to the parallel-connected assembly of capacitor 22 and nMOS transistor 23.
FIG. 27 shows an example of an arrangement of a switching current-leakage current comparing semiconductor integrated circuit device based on the present invention. The circuit shown in FIG. 27 comprises precharging pMOS transistor 21, capacitor (C) 22, leakage current generating circuit 27, comparing circuit 25, and register 26. Leakage current generating circuit 27 may be a leakage current observing circuit as it may observe a leakage current and output a current depending on the observed result. pMOS transistor 21 and capacitor 22 are connected in series to each other between power supply voltage VDD and the ground potential, and leakage current generating circuit 27 is connected parallel to capacitor C. Comparing circuit 25 compares voltage VA at a junction (comparison node) between pMOS transistor 21 and capacitor 22 with a one-half value (VDD/2) of power supply voltage VDD. The comparison result is read into register 26 in synchronism with clock signal CLK.
Arrangements of the leakage current observer according to the present invention will be described below. FIGS. 28 to 37 show arrangements of the leakage current observer.
The circuit shown in FIG. 28 comprises nMOS transistor 271 in an off-state with the gate terminal and the source terminal being connected to each other. A current flowing through nMOS transistor 271 in the off-state is leakage current ILEAK. The circuit shown in FIG. 29 comprises pMOS transistor 272 in the circuit design shown in FIG. 28.
In the MOS transistor constituting the leakage current observer, it is possible to apply a bias between the gate and the source when the leakage current is small and the layout scale has to be increased to observe the leakage current or when the leakage current is too large. The circuit shown in FIG. 30 is of an arrangement in which biased nMOS transistor 273 is used in the circuit design shown in FIG. 28. Likewise, the circuit shown in FIG. 31 is of an arrangement in which biased PMOS transistor 274 is used in the circuit design shown in FIG. 29.
The circuit shown in FIG. 32 includes current mirror 275 added to the circuit shown in FIG. 29 for changing the direction in which the leakage current flows. Similarly, the circuit shown in FIG. 33 includes current mirror 276 added to the circuit shown in FIG. 28 for changing the direction in which the leakage current flows.
The circuit shown in FIG. 34 is of an arrangement in which current mirrors 275, 276 are connected to the circuit shown in FIG. 28 for making the drain-to-source voltage independent of the comparison voltage of a comparing circuit that is connected to the leakage current observer. Similarly, the circuit shown in FIG. 35 is of an arrangement in which current mirrors 275, 276 are connected to the circuit shown in FIG. 29 for making the drain-to-source voltage independent of the comparison voltage of a comparing circuit that is connected to the leakage current observer.
The circuit shown in FIG. 36 is of an arrangement in which differential amplifier 277 is inserted in current mirror 275 of the circuit shown in FIG. 32 for applying the power supply voltage to the drain-to-source voltage. Ground potential GND is supplied to the other input terminal of differential amplifier 277. Similarly, the circuit shown in FIG. 37 is of an arrangement in which differential amplifier 277 is inserted in current mirror 276 of the circuit shown in FIG. 33 for applying power supply voltage VDD to the drain-to-source voltage. Power supply voltage VDD is supplied to the other input terminal of differential amplifier 277.
FIG. 38 shows another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device based on the present invention. The circuit shown in FIG. 38 is similar to the circuit shown in FIG. 27, and comprises capacitor (C) 22, precharging nMOS transistor 23 connected parallel to capacitor C, leakage current generating circuit 27 connected to the parallel-connected assembly of capacitor 22 and precharging nMOS transistor 23, comparing circuit 25, and register 26.
FIG. 39 shows yet another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device. The circuit shown in FIG. 39 includes two comparing circuits 25 in the circuit shown in FIG. 27. One of the comparing circuits compares reference voltage VDD/2+Δ with VA and generates an Up signal. The other comparing circuit compares reference voltage VDD/2−Δ with VA and generates a Down signal. In this circuit, Up and Down signals are separately generated to provide a hold state with a fixed threshold value. Similarly, as shown in FIG. 40, two comparing circuits 25 may be provided in the arrangement shown in FIG. 38.
FIG. 41 shows yet still another example of the arrangement of the switching current-leakage current comparing semiconductor integrated circuit device. The circuit shown in FIG. 41 includes two circuits each shown in FIG. 27, providing a current mirror circuit. One of the circuits uses leakage current ILEAK/α to generate an Up signal, and the other circuit uses leakage current ILEAK·α to generate a Down signal. The comparison node voltage in one of the circuits is represented by VA, whereas the comparison node voltage in the other circuit by VB. Here, nMOS transistors 281 to 283 make up a current mirror. Leakage current ILEAK generated by leakage current generating circuit 27 flows through nMOS transistor 281, causing nMOS transistor 282 of one of the circuits to generate leakage current ILEAK/α and causing nMOS transistor 283 of the other circuit to generate leakage current ILEAK·α. In this circuit, Up and Down signals are also separately generated to provide a hold state with a fixed threshold value.
Likewise, a circuit shown in FIG. 42 includes two circuits each shown in FIG. 38, providing a current mirror circuit. One of the circuits uses leakage current ILEAK/α to generate an Up signal, and the other circuit uses leakage current ILEAK·α to generate a Down signal. Here, pMOS transistors 284 to 286 make up a current mirror.
A switching current observer shown in FIG. 43 comprises a plurality of unit circuits each including leakage current generating circuit (leakage current generating transistor) 27 and reference current generating circuit 28. Reference currents provided at a plurality of levels allow a bit string to be generated depending on the leakage current. Similarly, a switching current observer shown in FIG. 44 comprises a plurality of unit circuits each including leakage current generating circuit (leakage current generating transistor) 27 and reference current generating circuit 28.
In each of the above exemplary embodiments, if the comparing circuit compares currents, then the comparing circuit can be realized by connecting a comparison current line and comparing the node thereof using a voltage comparing circuit. The voltage comparing circuit can be realized by a differential amplifying circuit and a buffer circuit.
The threshold voltage control circuit can be realized by a charge pump or a regulator for controlling the substrate bias potential. The substrate bias potential is controlled in a range from a forward potential to a reverse potential. The substrate bias potential may be controlled only in a range of reverse potentials or may be controlled only in a range of forward potentials. Upper and lower limits may be provided in the range of substrate bias potentials.
The power supply voltage control circuit can be realized by a regulator for controlling the power supply voltage.
The arrangements of the comparing circuit, the threshold voltage control circuit, and the power supply voltage control circuit are well known to the person skilled in the art, and will not be described below.
FIG. 45 shows an example of the arrangement of the delay observer and the control switcher. The illustrated circuit comprises critical path circuit 51, margin delay circuits 52, registers 53, and control circuit 54. Delay circuits 52 are provided as four series-connected stages connected to the output of critical path circuit 51 for generating signals tD-1, tD0, tD1, tD2, tD3. Signals tD-1, tD0, tD1, tD2, tD3 are read into register 53 in synchronism with clock CLK, and supplied to control circuit 54. Control circuit 54 outputs a power supply voltage control enable signal (PSCE) and a threshold voltage control enable signal (BBCE) and also outputs an up signal and a down signal for increasing and decreasing the power supply voltage according to the flowchart shown in FIG. 5, and outputs an operability signal (Ready) according to the flowchart shown in FIG. 6. Use of a RESET signal can reliably start operating from the power supply voltage control mode. A timing chart for outputting BBCE is shown in FIG. 46.
As shown in FIG. 47, under the condition of a constant operating speed, the operating current of the semiconductor integrated circuit device, i.e., total current ITOTAL comprises switching current ISW and leakage current ILEAK as its components. The operating current of the semiconductor integrated circuit device becomes minimum at certain power supply voltage VDD and threshold voltage VTH corresponding thereto.
A semiconductor integrated circuit device according to still another exemplary embodiment of the present invention will be described below. FIG. 48 shows an overall arrangement of a semiconductor integrated circuit device according to a fifth exemplary embodiment of the present invention. This semiconductor integrated circuit device is similar to the circuit shown in FIG. 4, but differs therefrom in that in the power supply voltage control, control switcher 10 supplies the same control signal as the control signal supplied from delay 25 observer 5 to power supply voltage controller 6 to threshold voltage controller 4 to control the substrate voltage for compensating for a change in the threshold value due to a change in the power supply voltage. In the threshold voltage control, the control signal from comparator 3 is supplied to threshold voltage controller 4 to control the substrate voltage, as with the cases described above. For enabling the control of the substrate voltage in this manner, the semiconductor integrated circuit device includes selector switch 20 for selectively inputting the control signal from comparator 3 and the control signal from delay observer 5 to threshold voltage controller 4. Selector switch 20 is controlled by control switching signal SEL from control switcher 10 to select and supply either one of the control signals to threshold voltage controller 4.
FIG. 49 shows an overall arrangement of a semiconductor integrated circuit device according to a sixth exemplary embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 49 is similar to the circuit shown in FIG. 4, but differs therefrom in that it includes threshold voltage compensator 40 for compensating for a change in threshold value VTH due to a change in power supply voltage VDD in the power supply voltage control. Threshold voltage compensator 40 is supplied with power supply voltage VDD and generates a control signal to be supplied to threshold voltage controller 4 for changing the threshold value in accordance with a change in power supply voltage VDD. In the power voltage control, control switcher 10 supplies the control signal from threshold voltage compensator 40 to threshold voltage controller 4 to control the substrate voltage for compensating for a change in the threshold value due to a change in the power supply voltage. In the threshold voltage control, the control signal from comparator 3 is supplied to threshold voltage controller 4 to control the substrate voltage, as with the cases described above. For enabling the control of the substrate voltage in this manner, the semiconductor integrated circuit device includes selector switch 20 for selectively inputting the control signal from comparator 3 and the control signal from threshold voltage compensator to threshold voltage controller 4. Selector switch 20 is controlled by control switching signal SEL from control switcher 10 to select and supply either one of the control signals to threshold voltage controller 4.
FIG. 50 shows an example of an arrangement of threshold value compensator 40. Threshold value compensator 40 comprises: comparator 61 which is supplied with substrate voltage (n-well bias voltage) VNW and power supply voltage (source voltage) VDD and determines voltage VBS representing the difference between the substrate voltage and the source voltage (power supply voltage) upon switching to the power supply voltage control; holding unit 62 for holding voltage VBS representing the difference; comparator 63 for comparing voltages VBS before and after switching to the power supply voltage control by comparing the output of comparator 61 and the value held in holding unit 62; and control unit 64 for generating an Up or Down control signal to increase or decrease the substrate voltage (n-well bias voltage VNW) depending on the comparison result from comparator 63. Here, holding unit 62 is supplied with control switching signal SEL, determines switching to the power supply voltage control based on control switching signal SEL, and holds the output from comparator 61.
Comparator 61 comprises A/D (analog/digital) converter 611 for converting power supply voltage VDD into a digital value, A/D (analog/digital) converter 612 for converting substrate voltage VNW into a digital value, and subtractor 613 for determining the difference between the output from A/D converter 611 and the output from A/D converter 612.
FIG. 51 shows another example of the arrangement of control switcher 10 according to the present invention. Control switcher 10 switches between the power supply voltage control and the threshold voltage control in the manner described in the exemplary embodiments described above, and also switches the control depending on whether the value of substrate-to-source voltage VBS of the transistor is in a predetermined range or not. Therefore, FIG. 51 shows only a portion of control switcher 10 for performing control mode switching depending on substrate-to-source voltage VBS, i.e., an additional portion. The circuit portion shown in FIG. 51 is supplied with power supply voltage control enable signal PSCE and threshold voltage control enable signal BBCE. These signals are supplied from, for example, the circuit shown in FIG. 45, i.e., the control switcher exclusive of the additional portion of the example shown in FIG. 51.
The circuit shown in FIG. 51 switches from the power supply voltage control to the threshold voltage control or from the threshold voltage control to the power supply voltage control to control substrate-to-source voltage VBS Of the transistor to fall into a predetermined range when VBS reaches a predetermined range limit, i.e., an upper limit or a lower limit. Specifically, the circuit shown in FIG. 51 comprises: comparator 61 for being supplied with power supply voltage VDD (or GND power supply voltage) and the substrate voltage and determining voltage VBS; upper limit data storage unit 621 for storing an allowable upper limit for VBS; a lower limit data storage unit 622 for storing an allowable lower limit for VBS; comparators 631, 632 for comparing VBS with the upper and lower limits; and control unit 64 for being supplied with power supply voltage control enable signal PSCE and threshold voltage control enable signal BBCE and outputting power supply voltage control enable signal PSCE′ or threshold voltage control enable signal BBCE′ depending on the comparison results from comparators 631, 632. Here, the substrate voltage represents n-well bias voltage VNW or p-well bias voltage VPW.
FIG. 52 shows still another control switcher according to the present invention. As with the case of FIG. 51, FIG. 52 shows the additional portion of the control switcher. Control switcher 10 shown in FIG. 52 operates to switch to the threshold voltage control when power supply voltage VDD reaches predetermined upper and lower limits in the power supply voltage control, and to switch to the power supply voltage control when the threshold voltage or the substrate voltage reaches predetermined upper and lower limits in the threshold voltage control. The substrate voltage represents n-well bias voltage VNW or p-well bias voltage VPW. By thus operating, the circuit shown in FIG. 52 makes it possible to change to an optimum power supply voltage or an optimum threshold voltage which has been difficult to achieve due to the dead zone of delay observer 5.
Control switcher 10 shown in FIG. 52 comprises: upper limit data storage unit 623 and lower limit data storage unit 624 for holding upper and lower limit values, respectively, for the power supply voltage; comparators 633, 634 for comparing power supply voltage VDD (or GND power supply voltage) with the upper and lower limits values stored in storage units 623, 624; upper limit data storage unit 625 and lower limit data storage unit 626 for holding upper and lower limit values, respectively, for the substrate voltage; comparators 635, 636 for comparing the substrate voltage with the upper and lower limits values stored in storage units 625, 626; and control unit 64 for being supplied with power supply voltage control enable signal PSCE and threshold voltage control enable signal BBCE and outputting power supply voltage control enable signal PSCE′ or threshold voltage control enable signal BBCE′ depending on the comparison results from comparators 633 to 636.
FIG. 53 shows yet another example of the arrangement of the delay measurer and the control switcher according to the present invention. As with the circuit shown in FIG. 45, the circuit comprises: input register 53 which is synchronized with clock CLK; critical path circuit 51 connected to the output of input register 53; a plurality of cascaded delay circuits 52, one end of the cascaded connection of delay circuits being connected to the output of critical path circuit 51; output register 53 which is synchronized with clock CLK that is connected to the output of critical path circuit 51 and the respective outputs of delay circuits 52; and a control circuit provided on the output side of output register 53 for generating respective signals such as error, Up, Down, PSCE (and SEL), BBCE, etc. The delay measurer determines a delay amount based on the timing relationship between the output values from respective delay circuits 52 and clock CLK. Particularly, the circuit is supplied with output D-3′ of critical path circuit 51 and outputs D-2′, D-1′, D1′, D2′ of the respective delay circuits, and output register 53 determines the delay amount from the relationship between the edge of clock CLK and the edges of the outputs of the respective delay circuits. For example, the circuit determines whether the edge of clock CLK is present prior to the edge of D-2′, or between the edge of D-1′ and the edge of D1′, or subsequent to the edge of D2′. If the edge of clock CLK is present prior to the edge of D-2′ or subsequent to the edge of D2′, then the control switcher switches to the power supply voltage (VDD) control, and if the edge of clock CLK is present between the edge of D-1′ and the edge of D1′, then the control switcher switches to the threshold voltage (VTH) control.
FIG. 54 is a truth table showing an operation sequence of the delay measurer and the control switcher in the circuit shown in FIG. 53. FIG. 55 is a timing chart showing the operation sequence of the delay measurer and the control switcher in the circuit shown in FIG. 53. As shown, according to the relationship between the clock period and the delay as determined by the delay observer, switching takes placed between the power supply voltage control and the threshold voltage control to perform the power supply voltage control and the threshold voltage control for converging to the power supply voltage and the threshold voltage to minimize the operational power.
INDUSTRIAL APPLICABILITY
Applications of the present invention include mobile devices such as cellular phone and PDA (personal digital assistant).
Patent Application
20080191791
