SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract

A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an embodiment of the present invention;

FIG. 2 is a circuit diagram of an exemplary clock switching circuit;

FIG. 3 is a table used to describe exemplary operations of a selection circuit;

FIG. 4 is a drawing used to describe exemplary operations of the exemplary clock switching circuit; and

FIG. 5 is a drawing used to describe a conventional clock signal switching method.

Claims

1. A semiconductor integrated circuit device, comprising: a selection circuit that is supplied with a first clock signal and a second clock signal having different phases, a selection signal, and a switching signal to be changed in synchronization with an output clock signal, and is configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal; andan output fixing circuit configured to generate a pulse based on the switching signal and an output signal from the selection circuit which pulse is maintained at a high level or a low level during a period between a time when the output signal from the selection circuit falls or rises after the switching signal is changed and a time when the fallen or risen output signal from the selection circuit successively rises or falls, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.

2. The semiconductor integrated circuit device as claimed in claim 1, further comprising: an external terminal configured to supply the selection signal.

3. The semiconductor integrated circuit device as claimed in claim 2, further comprising: a register configured to retain and supply the switching signal.

4. The semiconductor integrated circuit device as claimed in claim 3, wherein the selection circuit includes a first logical circuit configured to perform an exclusive NOR operation on the selection signal and the switching signal;a second logical circuit configured to perform an AND operation on the first clock signal and an output signal from the first logical circuit;a third logical circuit configured to perform an AND operation on the second clock signal and an inverted signal of the output signal from the first logical unit; anda fourth logical circuit configured to perform an OR operation on the output signal from the second logical circuit and the output signal from the third logical unit.

5. The semiconductor integrated circuit device as claimed in claim 4, wherein the output fixing circuit includes a first flip-flop configured to latch the switching signal at a falling edge of the output signal from the selection circuit;a second flip-flop configured to latch an output signal from the first flip-flop at a rising edge of the output signal from the selection circuit;a fifth logical circuit configured to perform an exclusive OR operation on the switching signal and an output signal from the second flip-flop and to output a result of the exclusive OR operation as the pulse; anda sixth logical circuit configured to perform an OR operation on the pulse from the fifth logical circuit and the output signal from the selection circuit and to output a result of the OR operation as the output clock signal.