Semiconductor integrated circuit device

Abstract

Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power supply system different from the one power supply system, and a circuit that restrains a current flowing from the output circuit into the signal line when an ESD stress is applied from the output circuit to a signal transmitting/receiving portion of the input circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing an example of a configuration of a control circuit in the first embodiment of the present invention;

FIG. 3 is a diagram showing another example of the configuration of the control circuit in the first embodiment of the present invention;

FIG. 4 is a diagram showing an example of other configuration in the first embodiment of the present invention;

FIG. 5 is a diagram showing a configuration of a circuit according to a second embodiment of the present invention;

FIG. 6 is a diagram showing an example of a configuration of a control circuit in the second embodiment of the present invention;

FIG. 7 is a diagram showing other configuration of the control circuit in the second embodiment of the present invention;

FIG. 8 is a diagram showing a configuration of a circuit according to a third embodiment of the present invention;

FIG. 9 is a diagram showing an example of a configuration of a control circuit in the third embodiment of the present invention;

FIG. 10 is a diagram showing other configuration of the control circuit in the third embodiment of the present invention;

FIG. 11 is a diagram showing a configuration of a circuit according to a fourth embodiment of the present invention;

FIG. 12 is a diagram showing an example of a configuration of a control circuit in the fourth embodiment of the present invention;

FIG. 13 is a diagram showing other configuration of the control circuit in the fourth embodiment of the present invention;

FIG. 14 is a diagram showing a configuration of a circuit according to a fifth embodiment of the present invention;

FIG. 15 is a diagram showing an example of a configuration of a control circuit in the fifth embodiment of the present invention;

FIG. 16 is a diagram showing other configuration of the control circuit in the fifth embodiment of the present invention;

FIG. 17 is a diagram showing a configuration of a circuit according to a sixth embodiment of the present invention;

FIG. 18 is a diagram showing an example of a configuration of a control circuit in the sixth embodiment of the present invention;

FIG. 19 is a diagram showing other configuration of the control circuit in the sixth embodiment of the present invention;

FIGS. 20A, 20B, 20C and 20D include diagrams showing layout configurations in the embodiment of the present invention;

FIGS. 21A, 21B, 21C and 21D include diagrams showing layout configurations in the embodiment of the present invention;

FIG. 22 is a diagram showing a configuration of a circuit according to a seventh embodiment of the present invention;

FIG. 23 is a diagram showing a configuration of a circuit according to an eighth embodiment of the present invention;

FIG. 24 is a diagram showing a configuration of a circuit according to a ninth embodiment of the present invention;

FIG. 25 is a diagram showing a configuration disclosed in Patent Document 1; and

FIG. 26 is a diagram showing a configuration disclosed in Patent Document 1.

Claims

1. A semiconductor integrated circuit device comprising: a plurality of power supply systems;a signal line through which signal transfer is performed between a circuit in one power supply system and a circuit in an other power supply system; anda circuit that restrains a current flowing from the circuit in said one power supply system into said signal line when an abnormal voltage is applied to said one power supply system.

2. The semiconductor integrated circuit according to claim 1, wherein said control circuit that restrains a current comprises: a circuit that restrains the current flowing from one transistor in said one power supply system into an other transistor in said other power system, said one transistor outputting a signal to said signal line, said other transistor receiving the signal through said signal line.

3. The semiconductor integrated circuit device according to claim 2, wherein said circuit that restrains a current comprises: a circuit that restrains the current flowing into said other transistor in said other power supply system when the abnormal voltage is applied to said other power supply system.

4. A semiconductor integrated circuit device comprising: an output circuit with power thereof supplied from a first power supply system;an input circuit with power thereof supplied from a second power supply system;a signal line through which signal transfer is performed between the output circuit and the input circuit; anda circuit that restrains a current flowing into said signal line when an ESD (Electro-Static Discharge) stress is applied to a signal transmitting/receiving portion of said output circuit and said input circuit.

5. The semiconductor integrated circuit device according to claim 4, wherein said circuit that restrains a current comprises: a transistor with a current thereof being adjustably controlled according to a signal supplied to a control terminal thereof, said transistor being disposed at least one of between said output circuit and a high potential side power supply terminal in said one power supply system and between said output circuit and a low potential side power supply terminal in said one power supply system; anda control circuit that sets said transistor in an ON state at a time of a normal operation, and that changes a signal level at the control terminal of said transistor to limit the current that flows into said signal line, when the ESD stress is applied.

6. The semiconductor integrated circuit device according to claim 4, wherein said circuit that restrains a current comprises: a transistor with a current thereof being adjustably controlled according to a signal supplied to a control terminal thereof, said transistor being disposed at least one of between said input circuit and a high potential side power supply terminal in said other power supply system and between said input circuit and a low potential side power supply terminal in said other power supply system; anda control circuit that sets said transistor in an ON state at a time of a normal operation and changes a signal level at the control terminal of said transistor when the ESD stress is applied, thereby limiting the current that flows into said signal line.

7. The semiconductor integrated circuit device according to claim 5, wherein at least two cascade connected transistors are arranged at least one of between said signal line and the high potential side power supply terminal and between said signal line and the low potential side power supply terminal.

8. The semiconductor integrated circuit device according to claim 6, wherein at least two cascade connected transistors are arranged at least one of between said signal line and the high potential side power supply terminal and between said signal line and the low potential side power supply terminal.

9. The semiconductor integrated circuit device according to claim 5, wherein said control circuit includes a series circuit comprising a capacitance element and a resistance element, disposed between the high potential side power supply terminal in said one power supply system and the low potential side power supply terminal in said one power supply system, and a connecting point between said capacitance element and said resistance element is connected to the control terminal of the transistor.

10. The semiconductor integrated circuit device according to claim 6, wherein said control circuit includes a series circuit comprising a capacitance element and a resistance element, disposed between the high potential side power supply terminal in said other power supply system and the low potential side power supply terminal in said other power supply system, and a connecting point between said capacitance element and said resistance element is connected to the control terminal of the transistor.

11. The semiconductor integrated circuit device according to claim 5, wherein said control circuit includes a series circuit comprising a diode and a resistance element, disposed between the high potential side power supply terminal in said one power supply system and the low potential side power supply terminal in said one power supply system, and a connecting point between said diode and said resistance element is connected to the control terminal of the transistor.

12. The semiconductor integrated circuit device according to claim 6, wherein said control circuit includes a series circuit comprising a diode and a resistance element, disposed between the high potential side power supply terminal in said other power supply system and the low potential side power supply terminal in said other power supply system, and a connecting point between said diode and said resistance element is connected to the control terminal of the transistor.

13. The semiconductor integrated circuit device according to claim 5, wherein one of source and drain diffusion layers of the transistor and a tap that gives a potential to a well with the diffusion layer formed therein are arranged in contact with each other, the transistor being connected at least one of between said output circuit and the high potential side power supply terminal in said one power supply system and between said output circuit and the low potential side power supply terminal in said one power supply system, said tap being of a conductive type opposite to a conductive type of the diffusion layer.

14. The semiconductor integrated circuit device according to claim 6, wherein one of source and drain diffusion layers of the transistor and a tap that gives a potential to a well with the diffusion layer formed therein are arranged in contact with each other, the transistor being connected at least one of between said input circuit and the high potential side power supply terminal in said other power supply system and between said input circuit and the low potential side power supply terminal in said other power supply system, said tap being of a conductive type opposite to a conductive type of the diffusion layers.

15. The semiconductor integrated circuit device according to claim 4, wherein said output circuit comprises an inverter circuit that outputs an inverted signal of an input signal to said signal line.

16. The semiconductor integrated circuit device according to claim 4, wherein said output circuit includes: a first transistor arranged between said signal line and a high potential side power supply terminal in said one power supply system; anda second transistor arranged between said signal line and a low potential side power supply terminal in said one power supply system, an output of said output circuit being connected to said signal line; and wherein said circuit that restrains a current comprises:a control circuit that generates a signal to be supplied to control terminals of said first and second transistors so that said first and second transistors complementarily turn on and off in response to an input signal input to said output circuit and to be output to said signal line at a time of a normal operation, and adjustably controls a level at a control terminal of at least one of said first transistor and said second transistor, when an ESD stress is applied to said one power supply system, thereby limiting a current flowing from said output circuit to said signal line by the application of the ESD stress.

17. The semiconductor integrated circuit device according to claim 16, wherein said control circuit comprises: a series circuit comprising a capacitance element and a resistance element, disposed between said high potential side power supply terminal in said one power supply system and said low potential side power supply terminal in said one power supply system; anda logic circuit that generates a signal based on a potential at a connecting point between said capacitance element and said resistance element and the input signal, said logic circuit generating the signal that sets said first transistor in an ON state and sets said second transistor in an OFF state, when the potential at said connecting point is of a level in which the application of the ESD stress is not detected and when the input signal is of a first value, and generating the signal that sets said first transistor in an OFF state and sets said second transistor in an ON state, when the potential at said connecting point is of a level in which the application of the ESD stress is not detected and when the input signal is of a second value, said logic circuit outputting to said control terminals of said first and second transistors the signal that sets at least one of said first transistor and said second transistor in an OFF state, when the potential at said connecting point is a level is of a level in which the application of the ESD stress is detected.

18. The semiconductor integrated circuit device according to claim 4, wherein an ESD protection element is disposed between high and low potential side power supply terminals of said output circuit in said one power supply system and an ESD protection element is disposed between high and low potential side power supply terminals of said input circuit in said other power supply system.