Claims
- 1. A semiconductor integrated circuit device having at least one capacitor, comprising:
- a first semiconductor layer of a first conductivity type having a relatively high impurity concentration in a range of 1.times.10.sup.16 through 1.times.10.sup.21 /cm.sup.3 ;
- a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of 1.times.10.sup.14 through 1.times.10.sup.16 /cm.sup.3 ;
- a groove having sidewall surface areas extending through said second semiconductor layer and into said first semiconductor layer;
- an oxide layer formed on said sidewall surface areas of said groove;
- a capacitor electrode in said groove bounded by said oxide layer lining said groove; and
- a third semiconductor layer of a second conductivity type surrounding said groove and a depletion layer surrounding said third semiconductor layer;
- wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by the depletion layer between said third semiconductor layer and said second semiconductor layer.
- 2. A semiconductor integrated circuit device in accordance with claim 1, wherein
- said device includes memory cells each having a single transistor and a single capacitor.
- 3. A semiconductor integrated circuit device having at least one capacitor, comprising:
- a first semiconductor layer of a first conductivity type having a relatively high impurity concentration in a range of 1.times.10.sup.16 through 1.times.10.sup.21 /cm.sup.3 ;
- a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of 1.times.10.sup.14 through 1.times.10.sup.16 /cm.sup.3 ;
- a groove having sidewall surface areas extending perpendicular to the plane of an interface of said first and second semiconductor layers,
- an oxide layer formed on said sidewall surface areas of said groove;
- a capacitor electrode in said groove bounded by said oxide layer lining said groove; and
- a third semiconductor layer of a second conductivity type surrounding said groove and a depletion layer surrounding said third semiconductor layer, said depletion layer being narrower in a portion proximate said first semiconductor layer than in a portion proximate said second semiconductor layer;
- wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by said the depletion layer between said third semiconductor layer and said second semiconductor layer.
- 4. A semiconductor integrated circuit device in accordance with claim 3, wherein
- said device includes memory cells each having a single transistor and a single capacitor.
- 5. A semiconductor integrated circuit device having at least one capacitor, comprising:
- a first semiconductor layer of a first conductivity type having a relatively high impurity concentration of in a range of 1.times.10.sup.16 through 1.times.10.sup.21 /cm.sup.3 ;
- a second semiconductor layer of said first conductivity type having a thickness of at least 2 microns formed on said first semiconductor layer and having a relatively low impurity concentration in a range of in a range of 1.times.10.sup.14 through 1.times.10.sup.16 /cm.sup.3 ;
- a groove having sidewall surface areas extending through said second semiconductor layer and into said first semiconductor layer;
- an oxide layer formed on said sidewall surface areas of said groove;
- a capacitor electrode in said groove bounded by said oxide layer lining said groove; and
- a third semiconductor layer of a second conductivity type, formed in response to the application of a relatively high voltage to said capacitor electrode, surrounding said groove and a depletion layer surrounding said third semiconductor layer.
- 6. A semiconductor integrated circuit device in accordance with claim 5 wherein a storage capacitance is formed between said capacitor electrode and said third semiconductor layer, a first junction capacitance is formed by the depletion layer between said third semiconductor layer and said first semiconductor layer and a second junction capacitance is formed by said the depletion layer between said third semiconductor layer and said second semiconductor layer.
- 7. A semiconductor integrated circuit device in accordance with claim 6, wherein
- said device includes memory cells each having a single transistor and a single capacitor.
Priority Claims (1)
Number |
Date |
Country |
Kind |
59-78928 |
Apr 1984 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/232,551 filed Aug. 15, 1988 and now abandoned, which is a continuation of application Ser. No. 07/047,607 filed May 1, 1987 and now abandoned, which is a continuation of application Ser. No. 06/694,322 filed Jan. 24, 1985 and now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (7)
Number |
Date |
Country |
0085988 |
Aug 1973 |
EPX |
0088451 |
Sep 1983 |
EPX |
2318912 |
Jan 1974 |
DEX |
3414057 |
Oct 1984 |
DEX |
57-01252 |
Jan 1982 |
JPX |
57-45269 |
Mar 1982 |
JPX |
2114814 |
Feb 1982 |
GBX |
Non-Patent Literature Citations (5)
Entry |
Electronics, vol. 54, #13, pp. 103-105, by Rao, Jun. 30, 1981. |
Sze, Physics of Semiconductor Devices, 1981, p. 32. |
H. H. Chao et al., IBM Technical Disclosure Bulletin, vol. 26, No. 5 (10/83). |
P. F. Landler, IBM Technical Disclosure Bulletin, vol. 17, No. 11 (4/75). |
IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984, "Trench Node One-Device Memory Cell Process", by B. El-Kareh et al., pp. 4699-4701. |
Continuations (3)
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Number |
Date |
Country |
Parent |
232551 |
Aug 1988 |
|
Parent |
47607 |
May 1987 |
|
Parent |
694322 |
Jan 1985 |
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