This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-321128 which was filed on Dec. 17, 2008, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and to a test method for that circuit.
2. Description of Related Art
One example of an operation test of a receive circuit mounted in a semiconductor circuit is disclosed in patent document (Japanese Patent Application Laid Open No. 2006-303786) The data transmit-receive circuit disclosed in patent document makes the serial transmission data loop back to the receive circuit to test the receive circuit.
The data transmit-receive circuit in patent document however utilizes multiple gates as shown in
This method therefore has the problem that when temperature or production conditions have changed during the semiconductor circuit test, the analog components are drastically affected causing a change in their operation making it impossible to perform a stable quantitative evaluation. For example when making an evaluation test of semiconductor circuits, the tests are always made at a fixed delay (quantity) so that the delay (quantity) must be reset for each LSI being tested, which so that the test program cannot run efficiently.
A semiconductor integrated circuit of an exemplary aspect according to the present invention includes an oscillation circuit for generating multiple clocks possessing mutually different phases. The semiconductor integrated circuit selects a single clock from among the multiple clocks to use for sending the transmission signal and utilizes that single clock to send the transmission signal.
By guaranteeing the phase difference among the multiple clocks generated by the oscillation circuit, and selecting a single clock from among those multiple clocks for sending the transmission signal, the test method for semiconductor integrated circuit of the present invention can make an efficient and stable quantitative evaluation without being affected by the semiconductor integrated circuit production conditions or other factors.
The test method for semiconductor integrated circuits of the present invention includes an oscillation circuit for generating multiple clocks of mutually different phases, a transmit circuit for sending the transmission signal, and a receive circuit for receiving the transmission signal sent by the transmit circuit during the loopback test operation and is characterized by a step for selecting a single clock from the multiple clocks for use in sending the transmit signal, and for sending that transmission signal by utilizing the selected clock, and a step for performing the received processing signal by utilizing the multiple clocks.
The test method for the semiconductor integrated circuit of the present invention guarantees the phase differences among the multiple clocks generated by the oscillation circuit, and by selecting and utilizing a single clock from among these multiple clocks to use in sending the transmission signal, can constantly obtain transmission signals received at the receive circuit at a fixed delay quantity and therefore make an efficient and stable quantitative evaluation without being affected by the semiconductor integrated circuit production conditions or other factors.
The semiconductor integrated circuit and the test method of the present invention can therefore provide a test method and semiconductor integrated circuit capable of making efficient and stable quantitative evaluations.
The above and other exemplary aspects, advantages and features of the present invention will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:
The semiconductor integrated circuit 1 contains an RF interface circuit 3, an internal logic circuit 4, a PLL (Phase Locked Loop) circuit 5, and LVDS buffer 6 made up of an LVDS circuit, and a switch 9. The RF interface circuit 3 is an interface for carrying out clock-less, high-speed synchronous communication, and includes a transmit circuit (TX) 7, and a receive circuit (RX) 8. The transmit circuit (TX) 7, and a receive circuit (RX) 8 are described in detail later on.
The internal logic circuit 2 generates processing data (IQ Parallel) processed within the system and outputs it to the transmit circuit (TX) 7. The data signal IQ Parallel is for example parallel data with a bit width of 8 bits. The internal logic circuit 2 performs signal processing (for example, decoding including a path search of receive data) based on the parallel data IQ Parallel output from the receive circuit (RX) 8, and generates data signals or control signals utilized in latter stage circuits (not shown in drawings).
The PLL circuit 5 generates a standard clock FCLK_M and a multiphase clock FCLK_P [n-1:0]. The PLL circuit 5 outputs the generated standard clock FCLK_M and a multiphase clock FCLK_P [n-1:0] to the RF interface circuit 3. In the first exemplary embodiment, the standard clock FCLK_M and a multiphase clock FCLK_P [n-1:0] are high-speed clocks obtained by frequency-multiplication of the reference clocks. It is noted that n is natural number, for example. The multiphase clock FCLK_P [n-1:0] consists of multiple clocks at the same speed and possessing mutually different phases of 360°/n each; The n as described in the first exemplary embodiment is 8. The output from the PLL circuit 5 therefore consists of a bit width of one bit, and a bit width of eight bits, and each bit corresponds to a single clock phase.
The LVDS buffer 6 preferably converts the transmission signal (IQ Serial) sent from the transmit circuit (TX) 7, to a low voltage differential signaling (LVDS) serial signal. The LVDS buffer 6 preferably converts the transmission signal (IQ Serial) sent to the receive circuit (RX) 8 to a low voltage differential signaling (LVDS) serial signal. Here, the data signal IQ Serial is serial data. The serial transmission signal from the transmit circuit (TX) 7 for example is differentially amplified by the LVDS buffer 6 and sent as shown in
In the first exemplary embodiment, the semiconductor integrated circuit 1 contains a switch 9, and a switch 10 between the semiconductor integrated circuit 1 and the other device 2. A loopback test can in this way be made on the semiconductor integrated circuit 1 by setting the switch 9 to ON. The semiconductor integrated circuit 1 and the other device 2 mounted on the substrate can be made to perform the loopback test by turning the switch 9 to OFF and the switch 10 to ON. Utilizing the switch 10 allows sending and receiving the transmission signals between the transmit circuit (TX) 7 and the receive circuit (RX) 8 by way of the LVDS buffer 6 during the loopback test so that a test of the LVDS buffer 6 can be made at the same time.
The structure of the transmit circuit (TX) 7 of the first exemplary embodiment is described next while referring to
The transmit circuit (TX) 7 as shown in
The phase adjuster unit 11 selects a single clock FCLK_P from among the multiphase clocks FCLK_P [n-1:0]. This phase adjuster unit 11 switches the test operation. The phase adjuster unit 11 is for example a register. A test operation switching signal ADJEN and a clock select signal PHSEL [n-1:0] are set within the phase adjuster unit 11. The phase adjuster unit 11 outputs the ADJEN signal for example shows 1 during loopback test operation and outputs an ADJEN signal for example showing 0 during normal operation. One example of the clock select signal PHSEL [n-1:0] may be the signal (PHSEL7, PHSEL6, PHSEL5, . . . , PHSEL0)=(0, 0, 0, 0, 0, 0, 0, 1). The bit farthest to the left on the bit string indicates the MSB (Most Significant Bit) and the bit farthest to the right indicates the LSB (Least Significant Bit). This example shows the first clock FCLK_P0 counting from the LSB was selected. The test operation switching signal ADJEN and a clock select signal PHSEL [n-1:0] may be set based on the specified signal from the internal logic circuit 4, or may be set by the tester performing the test.
In the first exemplary embodiment, the transmit circuit (TX) 7 here places the IQ Parallel (data) generated here by the internal logic circuit 4 in a frames format and sends it as the transmission signal. The transmission signals now in a frame format are in the sync word area and the payload area contained within the data string. The system sends the payload following the synch word. The IQ Parallel generated in the internal logic circuit 4 is input to the transmit circuit (TX) 7 as shown in
The frame counter 12 estimates the frame start position based on the packet length of the frame, and outputs a select signal SYNC_IQ_SEL for switching between the SYNC data section and the IQ data section. The selector 13 selects the data signal based on the select signal SYNC_IQ_SEL and, outputs the selected data signal as parallel data (SYNC_IQ) to the parallel-serial converter (P/S) 14_M, and parallel-serial converter (P/S) 14_P0 through parallel-serial converter (P/S) 14_Pn-1.
The frame counter 12 outputs the control signal DLOAD_M, the control signals DLOAD_P0 through control signals DLOAD_Pn-1 to each of the parallel-serial converters (P/S). The control signal DLOAD_M, and the control signals DLOAD_P0 through control signals DLOAD_Pn-1 signify signals that allow each parallel-serial converter (P/S) to load the SYNC_IQ. A single signal among the control signal DLOAD_M, and the control signals DLOAD_P0 through control signals DLOAD_Pn-1 operate exclusively as the data load signal. The frame counter 12 sets the control signal DLOAD_M, and control signals DLOAD_P0 through control signals DLOAD_Pn-1 based on the test operation switching signal ADJEN and the clock select signal PHSEL [n-1:0]. During the loopback test operation, the frame counter 12 constantly outputs 0 from the DLOAD_M signal and the DLOAD_P signal corresponding for example to the clocks that were not selected; and also outputs a control signal only from the DLOAD_P signal corresponding to the selected clock. During normal operation, the frame counter 12 outputs a control signal only from the DLOAD_M signal, and also outputs 0 from the DLOAD_P signal corresponding to the multiphase clock.
The parallel-serial converter (P/S) 14_M operates in synchronization with the standard clock FCLK_M. The parallel-serial converter (P/S) 14_P0 through parallel-serial converter (P/S) 14_Pn-1 operate in synchronization with the respective multiphase clocks FCLK_P [n-1:0]. Namely, each of the parallel-serial converters (P/S) synchronizes with the respectively supplied clock to convert the loaded parallel data (SYNC_IQ) to serial data (SYNC_IQ). The OR circuit 17 logically sums the output from each parallel-serial converter (P/S), and this output from OR circuit 17 is output as IQ Serial.
The parallel-serial converter (P/S) 14_M and parallel-serial converters (P/S) 14_P0 through parallel-serial converters (P/S) 14_Pn-1 contain multiple selectors and multiple flip-flops. The parallel-serial converter (P/S) 14_M for example contains the selectors 15_M_1 through selectors 15_M_k, and the flip-flops 16_M_1 through flip-flops 16_M_k. Each of the data contained in the SYNC_IQ is respectively input to the selectors 15_M_1 through selector 15_M_k. Also, the control signals DLOAD_M are respectively input to the selectors 15_M_1 through selector 15_M_k. These selectors 15_M_1 through selectors 15_M_k select the input data signals based on the control signals DLOAD_M, and output the selected data signals respectively to the flip-flops 16_M_1 through flip-flops 16_M_k. The standard clock FCLK_M is supplied respectively to the flip-flops 16_M_1 through flip-flops 16_M_k, and these flip-flops 16_M_1 through flip-flops 16_M_k then operate synchronously with the standard clock FCLK_M. A Reset signal is input to the flip-flops 16_M_1 through flip-flops 16_M_k and inputting this Reset signal clears the values in the flip-flops.
The operation state in which the transmit circuit (TX) 7 generates the IQ Serial is described here while referring to
The structure of the receive circuit (RX) 8 of the first exemplary embodiment is described next while referring to
The synchronization detector unit 21 receives the transmission signals at multiple clocks of mutually different phases. The synchronization detector 21 then samples the sync (synchronization) words serving as the synchronized information contained in the received transmission signal at the multiple clocks of mutually different phases, and compares the sampling results with a pre-established synchronization pattern. If there is a clock corresponding to the synchronization pattern and matching synchronized word, then the clock at that sampling is identified from among the multiple clocks as the selected candidate clock. The synchronization detector 21 in other words, samples the synch (synchronization) words input at n number of clocks FCLK_P [n-1:0] of mutually different phases. The synchronization detector 21 outputs to the clock phase selector unit 22, OKFLG [n-1:0] as a signal showing at which clock among n number of clocks of different phases, the pre-established synchronization pattern was correctly sampled. The OKFLG [n-1:0] for example becomes a bit 1 signal for a clock where the pre-established synchronization pattern was correctly sampled; and becomes a bit 0 signal for clocks where the applicable synchronization pattern was not correctly sampled.
The clock phase selector unit 22 selects a single clock for use in sampling the transmission signal from among the clocks FCLK_P [n-1:0] that sampled synchronization word matching the synchronization pattern. More specifically, the clock phase selector unit 22 receives the output signal OKFLG [n-1:0] from the synchronization detector 21 and selects a single clock for use in sampling from among the multiple FCLK_P [n-1:0]. The clock phase selector unit 22 outputs the select signal CLKSEL [n-1:0] indicating the selected clock, to the selector 25 of FIFO unit 24. The select signal CLKSEL [n-1:0] is a parallel signal indicating the output from the clock phase selector unit 22. The select signal CLKSEL [n-1:0] is transmitted in parallel by way of n number of signal lines. The clock selected for sampling for example is indicated by 1, and clocks not selected for sampling are indicated by 0. In one possible case for example, the clock phase selector unit 22 may select a single phase clock FCLK_P [n-1:0] from among eight phase clocks FCLK_P [n-1:0] and receive a signal (OKFLG7, OKFLG6, OKFLG5, . . . , OKFLG0)=(0, 1, 1, 1, 1, 1, 0, 0) as the output signal OKFLG [n-1:0] from the synchronization detector 21. The clock phase selector 22 may in this case select the clock FCLK_P4 for safe sampling in the center among the selectable clocks FCLK_P2 through 6. The clock phase selector 22 may then output (CLKSEL7, CLKSEL6, CLKSEL5, . . . , CLKSEL0)=(0, 0, 0, 1, 0, 0, 0, 0) as the select signal CLKSEL [n-1:0]. The bit on the left end is the most significant bit (MSB), and indicates whether or not the clock FLCK_P7 input to the synchronization detector 21 was selected. The bit on the right end is the least significant bit and indicates whether or not the clock FCLK_P0 input to the synchronization detector 21 was selected. In other words, in this example the clock phase selector 22 selects 1 which is the fifth bit counting from the LSB so that the clock phase selector 22 selects the clock FCLK_P4 input to the synchronization detector 21. This result indicates that the selector 25 will be operated by the clock FCLK_P4 which is the fifth bit counting from the LSB.
The clock handoff unit 23 receives the data signal output from the synchronization detector 21 at the clock FCLK_P [n-1:0] and performs asynchronous handoff processing to handoff the received data signal to the standard clock FCLK_M. A circuit in a latter stage after (downstream) the clock handoff unit 23 is operated at a single phase of the phase standard clock FCLK_M. In contrast, a circuit in a stage prior (upstream) to the clock handoff unit is operated at the multiphase clock FCLK_P [n-1:0] so that the clock handoff unit 23 performs the asynchronous handoff processing to the standard clock FCLK_M.
The FIFO unit 24 contains a selector 25, and a serial-parallel converter (S/P converter) 26. The selector 25 selects the data signal output by the clock handoff unit 23 based on the select clock CLKSEL [n-1:0], and outputs the selected data to the S/P converter 26. The S/P converter 26 synchronizes the serial data sampled in the FIFO unit 24, with the internal circuit standard clock SCLK, and converts it to parallel data (IQ Parallel) and outputs it.
In the semiconductor integrated circuit of the first exemplary embodiment described above, the PLL circuit 5 guarantees the phase difference between the sampling clocks utilizing the clock in transmit processing by the transmit circuit (TX) 7 and the sampling by the receiver circuit (RX) 8. By then using a single clock selected from the sampling clocks for generating the timing of serial transmit data sent by the transmit circuit (TX), a fixed delay can be constantly obtained without sustaining effects caused by production variations in the semiconductor integrated circuit 1. A quantitative clock evaluation can therefore be made with the clock operating the receive circuit (RX) 8 and the testing can be performed with more stability and efficiency.
The semiconductor integrated circuit (more specifically the baseband IC) of the second exemplary embodiment is described next. The semiconductor integrated circuit of the second exemplary embodiment differs from the semiconductor integrated circuit 1 of the first exemplary embodiment only in the transmit circuit (TX). Therefore only the structure and operation of the transmit circuit of the second exemplary embodiment are described next, and a description of the structure and operation where identical to the first exemplary embodiment is omitted.
The transmit circuit (TX) 7 as shown in
The phase adjuster unit 31 selects a single clock FCLK_P from the multiphase clock FCLK_P [n-1:0] to select. The phase adjuster unit 31 also switches the test operation. The structure of the phase adjuster unit 31 is for example a register. The test operation switching signal ADJEN and the clock select signal PHSEL [n-1:0] are set within the phase adjuster unit 31. During the loopback test, the phase adjuster unit 31 outputs an ADJEN signal for example indicating 1, and during normal operation outputs an ADJEN signal for example indicating 0. Moreover, one possible example of a clock select signal PHSEL [n-1:0] is (PHSEL7, PHSEL6, PHSEL5, . . . , PHSEL0)=(0, 0, 0, 0, 0, 0, 0, 1) signal. The bit farthest to the left on the bit string indicates the MSB (Most Significant Bit) and the bit farthest to the right indicates the LSB (Least Significant Bit). This example shows that the first clock FCLK_P0 counting from the LSB was selected. The test operation switching signal ADJEN and a clock select signal PHSEL [n-1:0] may be set based on the specified signal from the internal logic circuit 4, or may be set by the tester performing the test.
The clock selector (CLKMUX) 32 is made up of a selector 33 and a selector 34. The selector 33 selects a single clock from the multiphase clock FCLK_P [n-1:0].
The selector 34 outputs a single clock from the clocks selected by the standard clock FCLK_M and the selector 33, based on the test operation switching signal and outputs that single clock as TXCLK.
In this second exemplary embodiment, the transmit circuit (TX) 7 here also changes the IQ Parallel (data) generated by the internal logic circuit 4 into a frames format and sends it as the transmission signal. The transmission signals now in a frame format are in the sync word area and the payload area contained within the data string. The system sends the payload following the synch word. The IQ Parallel (data) generated in the internal logic circuit 4 is input to the transmit circuit (TX) 7 as shown in
The frame counter 35 estimates the frame start position based on the packet length of the frame, and outputs a select signal SYNC_IQ_SEL that switches between the SYNC data section and the IQ data section. The selector 36 selects the data signal based on the select signal SYNC_IQ_SEL and, outputs the selected data signal as parallel data (SYNC_IQ) to the parallel-serial converter (P/S) 37.
The frame counter 35 outputs the control signal DLOAD to the parallel-serial converter (P/S) 37 so that the parallel-serial converter (P/S) 37 can load the SYNC_IQ.
The parallel-serial converter (P/S) 37 operates in synchronization with the clock TXCLK that was selected by the clock selector (CLKMUX) 32. The parallel-serial converter (P/S) 37 in other words synchronizes with the supplied clock TXCLK and converts the loaded parallel data (SYNC_IQ) to serial data (SYNC_IQ). The parallel-serial converter (P/S) 37 outputs the converted serial data as IQ serial (data signal).
The parallel-serial converter (P/S) 37 contains the selectors 38_1 through selectors 38_k, and the flip-flops 39_1 through flip-flops 39_k. The parallel-serial converter (P/S) 37 inputs each of the data contained in the SYNC_IQ respectively to the selectors 38_1 through selectors 38—k. Also, the control signal DLOAD is respectively input to the selectors 38_1 through selectors 38—k. The selectors 38_1 through selectors 38—k select the data signals that were input based on the control signal DLOAD, and output the signal data respectively to the flip-flops 39_1 through flip-flops 39—k. The clock TXCLK is supplied to the flip-flops 39_1 through flip-flops 39—k, and these flip-flops 39_1 through flip-flops 39—k operate in synchronization with this clock TXCLK. A Reset signal is input to the flip-flops 39_1 through flip-flops 39—k, and inputting this Reset signal clears the values in the flip-flops.
The operation state in which the transmit circuit (TX) 7 generates the IQ Serial (data signal) is described here while referring to
In the semiconductor integrated circuit of the second exemplary embodiment described above, the PLL circuit 5 guarantees the phase difference between the sampling clocks utilizing the clock in transmit processing by the transmit circuit (TX) 7 and the sampling clock by the receiver circuit (RX) 8. By then using the single clock selected from the sampling clocks for generating the timing of serial transmit data sent by the transmit circuit (TX), a fixed delay (quantity) can be constantly obtained without sustaining effects caused by production variations in the semiconductor integrated circuit 1. A quantitative clock evaluation can therefore be made with the clock operating the receive circuit (RX) 8, and the testing can be performed with more stability and efficiency.
In the transmit circuit (TX) 7 of the second exemplary embodiment, the phase adjuster unit 31 selects a single clock TXCLK from among multiple clocks, and operates one of the serial-parallel converters (P/S) 37 while switching the selected clock so that unlike the transmit circuit 7 of the first exemplary embodiment, multiple parallel-serial converters are not required, and a further increase in the circuit scale of the transmit circuit (TX) 7 is prevented.
The effect of the present invention is described next in detail while referring to
The EYE pattern for the entire frame in
In the process for receiving the transmission signal, the synchronization detector unit 21 in the receive circuit (RX) 8 of the present invention detects synchronization by utilizing the eight clocks FCLK_P0 through 7. Moreover, the synchronization detector unit 21 of receive circuit (RX) 8 identifies clocks where synchronization was detected as selected clock candidates. Next, the clock phase selector unit 22 of the receive circuit (RX) 8 selects one sampling clock for use in sampling transmission signals among the identified selected clock candidates. The clock handoff unit 23 of the receive circuit (RX) 8 then utilizes the eight clocks FCLK_P0 through 7 to carry out the clock handoff. The FIFO unit then uses the selected sampling clocks to sample the received signals.
More specifically, when making a loopback test during the semiconductor integrated circuit screening evaluation in a state where the transmission signal clock is the fixed clock, the circuits formed for each (and every) sampling clock (synchronization detector unit, clock handoff unit, etc.) are seen as unneeded paths and so not evaluated. However during actual usage after production, these paths of course are no longer unneeded paths and become regular circuit paths that were overlooked during the screening and therefore might cause glitches or malfunctions when marketed as products. In the clock handover processor unit for example, data acquired from circuits supplied with clocks other than the center phase of Eye pattern 100a is judged to have poor reliability, and the received data does not propagate to circuit in stages subsequent (downstream) of data selector 25 in FIFO unit 24. Also, when making screening evaluations in the FIFO unit 24 by applying expectation value judgments to parallel signals that were serial-parallel converted; those data lines not propagating to the FIFO unit 24 are not considered part of the evaluation. Moreover, in the clock phase selector 22, only limited timing decisions and phase select algorithm validity decisions can be made when there are no state transitions within combination circuits due to use of fixed input signals.
The present invention is further not limited only to the above described exemplary embodiments and needless to say, all manner of changes and adaptations not departing from the scope of the present invention are allowable.
Further, it is noted that Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.
Number | Date | Country | Kind |
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2008-321128 | Dec 2008 | JP | national |