Claims
- 1. A semiconductor integrated circuit comprising:
an internal main bus; first and second microprocessors sharing said internal main bus; a first debug serial bus with one end thereof connected to said first microprocessor; a second debug serial bus with one end thereof connected to said second microprocessor; and a debugging module connected to the other ends of said first and second debug serial buses and transferring at least a debugging program and debugging data to said first microprocessor via said first debug serial bus and to said second microprocessor via said second debug serial bus.
- 2. The semiconductor integrated circuit of claim 1 further comprising a dedicated external debugging terminal which connects said debugging module and a debugging tool for controlling a debugging task in accordance with a debugging program.
- 3. The semiconductor integrated circuit of claim 1, wherein said debugging module is directly connected to said internal main bus.
- 4. The semiconductor integrated circuit of claim 2, wherein said debugging module is directly connected to said internal main bus, and said debugging module carries out directly the memory access which said debugging tool sends for said internal main bus.
- 5. The semiconductor integrated circuit of claim 1 further comprising a memory controller, a direct memory access controller and an input / output controller, all of which are connected to said internal main bus.
- 6. The semiconductor integrated circuit of claim 1 further comprising:
a first debug supporting unit provided in said first microprocessor and controlling a debugging function of said first microprocessor; and a second debug supporting unit provided in said second microprocessor and controlling a debugging function of said second microprocessor; a first debug controlling bus which connects said first debug supporting unit and said debugging module; and a second debug controlling bus which connects said second debug supporting unit and said debugging module.
- 7. The semiconductor integrated circuit of claim 5 further comprising:
a first debug supporting unit provided in said first microprocessor and controlling a debugging function of said first microprocessor; and a second debug supporting unit provided in said second microprocessor and controlling a debugging function of said second microprocessor; a first debug controlling bus which connects said first debug supporting unit and said debugging module; and a second debug controlling bus which connects said second debug supporting unit and said debugging module.
- 8. The semiconductor integrated circuit of claim 7, wherein said debugging module comprises:
an external debug interface connected to an external debugging tool; a multi-debug control register connected to said external debug interface and said first and second microprocessors; a debug control register, an address register, a byte enabling register and a data register, all of which are connected to said external debug interface; a debug serial bus converting circuit connected to said debugging control register; a debug serial bus selector connected to said multi-debug control register, said debug serial bus converting circuit and said first and second debug serial buses; and an internal direct memory access controller connected to said debug control register, said address register, said byte enabling register, said data register and said internal main bus.
- 9. The semiconductor integrated circuit of claim 6, wherein said debugging module monitors not only a debug state of said first microprocessor via said first debug controlling bus but also a debug state of said second microprocessor via said second debug controlling bus, and demands debugging interruption signal for shifting to a debugging mode.
- 10. The semiconductor integrated circuit of claim 7, wherein said debugging module monitors not only a debug state of said first microprocessor via said first debug controlling bus but also a debug state of said second microprocessor via said second debug controlling bus, and demands debugging interruption signal for shifting to a debugging mode.
- 11. The semiconductor integrated circuit of claim 8, wherein said debugging module monitors not only a debug state of said first microprocessor via said first debug controlling bus but also a debug state of said second microprocessor via said second debug controlling bus, and demands debugging interruption signal for shifting to a debugging mode.
- 12. The semiconductor integrated circuit of claim 1, wherein said debugging module optionally demands each of said first and second microprocessors to delay returning to a user mode from a debugging mode.
- 13. The semiconductor integrated circuit of claim 1, wherein: said first microprocessor comprises a first bus interface unit connected not only to a microprocessor core thereof but also to said first debug serial bus and said internal main bus; and said second microprocessor comprises a second bus interface unit connected not only to a microprocessor core thereof but also to said second debug serial bus and said internal main bus.
- 14. The semiconductor integrated circuit of claim 13, wherein:
said first bus interface unit comprises an internal main bus/debug serial bus controlling circuit connected to said debugging module and said microprocessor core, a parallel-to-serial converting circuit connected to said debugging module and said internal main bus/debug serial bus controlling circuit, a serial-to-parallel converting circuit connected to said debugging module and said parallel-to-serial converting circuit, and a selector connected to said microprocessor core, said internal main bus/debug serial bus controlling circuit, said parallel-to-serial converting circuit and said serial-to-parallel converting circuit; and said second bus interface unit comprises an internal main bus I/O debug serial bus controlling circuit connected to said debugging module and said microprocessor core, a parallel-to-serial converting circuit connected to said debugging module and said main bus/debug serial bus controlling circuit, a serial-to-parallel converting circuit connected to said debugging module and said parallel-to-serial converting circuit, and a selector connected to said microprocessor core, said internal main bus/debug serial bas controlling circuit, said parallel-to-serial converting circuit and said serial-to-parallel converting circuit.
- 15. A system board comprising:
a wiring board; a semiconductor integrated circuit which comprises an internal main bus, first and second microprocessors sharing said internal main bus, a first debug serial bus with one end thereof connected to said first microprocessor, a second debug serial bus with one end thereof connected to said second microprocessor, and a debugging module connected to the other ends of said first and second debug serial buses and transferring at least a debugging program and debugging data to said first microprocessor via said first debug serial bus, and to said second microprocessor via said second debug serial bus; and a memory mounted on said wiring board and storing at least debugging data.
- 16. The system board of claim 15 further comprising an input/output interface circuit mounted on said wiring board.
- 17. The system board of claim 15 further comprising a dedicated debug interface terminal which connects said debugging module of said semiconductor integrated circuit and a debugging tool for controlling a debugging operation in accordance with a debugging program.
- 18. The system board of claim 15, wherein said semiconductor integrated circuit further comprises a memory controller, a direct memory access controller and an input/output controller, all of which are connected to said internal main bus.
- 19. The system board of claim 18, wherein said semiconductor integrated circuit further comprises:
a first debug supporting unit provided in said first microprocessor and controlling a debugging function of said first microprocessor; and a second debug supporting unit provided in said second microprocessor and controlling a debugging function of said second microprocessor; a first debug controlling bus which connects said first debug supporting unit and said debugging module; and a second debug controlling bus which connects said second debugging support unit and said debugging module.
- 20. A debugging system comprising:
a wiring board; a semiconductor integrated circuit which is mounted on said wiring board and comprises: an internal main bus; first and second microprocessors sharing said main internal bus; a first debug serial bus with one end thereof connected to said first microprocessor; a second debug serial bus with one end thereof connected to said second microprocessor; and a debugging module connected to the other ends of said first and second debug serial buses and transferring at least a debugging program and debugging data to said first microprocessor via said first debug serial bus, and to said second microprocessor via said second debug serial bus; a memory mounted on said wiring board and storing at least debugging data; and a debugging tool connected to said debugging module of said semiconductor integrated circuit.
- 21. The debugging system of claim 20, wherein said semiconductor integrated circuit further comprises a memory controller, a direct memory access controller and an input/output controller, all of which are connected to said internal main bus.
- 22. The debugging system of claim 20, wherein said semiconductor integrated circuit further comprises:
a first debug supporting unit provided in said first microprocessor and controlling a debugging function of said first microprocessor; and a second debug supporting unit provided in said second microprocessor and controlling a debugging function of said second microprocessor; a first debug controlling bus which connects said first debug supporting unit and said debugging module; and a second debug controlling bus which connects said second debug supporting unit and said debugging module.
Priority Claims (1)
Number |
Date |
Country |
Kind |
P2000-402630 |
Dec 2000 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-402630 filed on Dec. 28, 2000, the entire contents of which are incorporated herein by reference.