Patent Application
20060087366
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and to a method of generating different voltages, and in particular, to a semiconductor integrated circuit which generates a boosted voltage and which generates a converted voltage based on the boosted voltage in order to activate a liquid crystal panel, and to a method of generating the boosted voltage and the converted voltage. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-307333 filed on Oct. 21, 2004, which is herein incorporated by reference.
2. Description of the Related Art
However, since the step-down circuit 630 generates the step-down voltage VEE based only on the boosted voltage VDD which is output from the boost circuit 620, electrical charge in the boosted voltage VDD may be consumed. Therefore, the boosted voltage VDD may be decreased. On such an occasion, a plurality of parasitic bipolar transistors 710 and 720 may appear in a semiconductor substrate 600 on which the boost circuit 620 and the step-down circuit 630 are disposed as shown in
According to an aspect of the present invention, for achieving the above-mentioned object, there is provided a semiconductor integrated circuit which includes a first electrical source terminal and a second electrical source terminal. The first electrical source terminal receives a first external power supply voltage. The second electrical source terminal receives a second external power supply voltage less than the first external power supply voltage. The semiconductor integrated circuit further includes a first voltage generating circuit which is coupled to the first electrical source terminal. The first voltage generating circuit generates a boosted voltage based on the first external power supply voltage. The boosted voltage is greater than the first external power supply voltage. The semiconductor integrated circuit still further includes a second voltage generating circuit which is coupled to the first electrical source terminal and the first voltage generating circuit. The second voltage generating circuit generates a first converted output voltage and a second converted output voltage that are different than the boosted voltage and different from each other. The second voltage generating circuit generates the first converted output voltage based on the first external power supply voltage. The second voltage generating circuit generates the second converted output voltage based on the boosted voltage after the first converted output voltage is generated.
According to another aspect of the present invention, for achieving the above-mentioned object, there is provided a generating method of different voltages. In the method, a boosted voltage is generated based on a first external power supply voltage which is greater than a second external power supply voltage. The boosted voltage is greater than the first external power supply voltage. A first converted output voltage is generated based on the first external power supply voltage. The first converted output voltage is different than the boosted voltage. After the first converted output voltage is generated, a second converted output voltage which is different than the first converted output voltage is generated based on the boosted voltage. The second converted output voltage is different than the boosted voltage.
The above and further aspects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
Embodiments of the present invention will be described hereinafter with references to the accompanying drawings. The drawings used for this description illustrate major characteristic parts of embodiments in order that the present invention will be easily understood. However, the invention is not limited by these drawings.
The control circuit 110 includes an NAND circuit 111, an inverter 112 and a timing adjustment circuit 113 which are coupled in series. The NAND circuit 111 receives an external control signal CP and a standby signal STBY and then executes a logical operation between the external control signal CP and the standby signal STBY. The external control signal CP is used for boosting the first external power supply voltage VCC1. The inverter 112 inverts an output logical signal of the NAND circuit 112. The timing adjustment circuit 113 generates a first adjustment signal 113a and a second adjustment signal 113b in accordance with a signal which is output from the inverter 112, in order to suppress a consumption current from increasing in the first voltage generating circuit 120, when the external control signal CP transitions.
The control circuit 110 further includes a plurality of inverters 114, 116-1 through 116-3, 117, 119-1 through 119-3 and level shift circuits 115 and 118. The inverter 114 inverts the first adjustment signal 113a in accordance the second external power supply voltage VCC2 and the ground voltage VSS, and then provides an output signal to the first voltage generating circuit 120. The level shift circuit 115 and the inverters 116-1 through 116-3 are coupled in series. The level shift circuit 115 inverts the first adjustment signal 113a. An output signal of the level shift circuit 115 is provided to the first voltage generating circuit 120 through the inverters 116-1 and 116-2 and is also provided to the second voltage generating circuit 130 through the inverters 116-1 through 116-3. The inverters 116-1 through 116-3 operate in accordance with the boosted voltage VDD and the first converted output voltage VEE1 or the second converted output voltage VEE2. The inverter 117 inverts the second adjustment signal 113b in accordance the second external power supply voltage VCC2 and the ground voltage VSS, and then provides an output signal to the first voltage generating circuit 120. The level shift circuit 118 and the inverters 119-1 through 119-3 are coupled in series. The level shift circuit 118 inverts the second adjustment signal 113b. An output signal of the level shift circuit 118 is provided to the second voltage generating circuit 130 through the inverters 119-1 and 119-2 and is also provided to the first voltage generating circuit 120 through the inverters 119-1 through 119-3. The inverters 116-1 through 116-3 and 119-1 through 119-3 operate in accordance with the boosted voltage VDD and the first converted output voltage VEE1 or the second converted output voltage VEE2.
The first voltage generating circuit 120 includes a first boosting transistor 121, a second boosting transistor 122, a PMOS transistor 123 and an NMOS transistor 124. In this example, the first boosting transistor 121 and the second boosting transistor 122 are PMOS transistors. The first boosting transistor 121 includes a gate electrode which is coupled to the inverter 114 of the control circuit 110, a source electrode is coupled to the second electrical source terminal T2 and a drain electrode which is coupled to a first node 120a. The first boosting transistor 121 receives the second external power supply voltage VCC2 as its substrate voltage. The second boosting transistor 122 includes a gate electrode which is coupled to the inverter 119-3 of the control circuit 110, a source electrode which is coupled to the first electrical source terminal T1 and a drain electrode which is coupled to a second node 120b. The second boosting transistor 122 receives the boosted voltage VDD as its substrate voltage. The PMOS transistor 123 includes a gate electrode which is coupled to the inverter 116-2 of the control circuit 110, a source electrode which is coupled to an output terminal 125 of the first voltage generating circuit 120 and a drain electrode which is coupled to the second node 120b. The PMOS transistor 123 receives the boosted voltage VDD as its substrate voltage. The NMOS transistor 124 includes a gate electrode which is coupled to the inverter 117 of the control circuit 110, a source electrode which is coupled to the reference electrical source terminal T0 and a drain electrode which is coupled to the first node 120a. The NMOS transistor 124 receives the ground voltage VSS as its substrate voltage. The first voltage generating circuit 120 further includes a capacitor C1 which is coupled between the first node 120a and the second node 120b.
The second voltage generating circuit 130 includes an adjustment circuit 140 and a step-down circuit 150. The adjustment circuit 140 includes a counting circuit 141, an NAND circuit 142, an inverter 143, a level shift circuit 144 and an inverter 145 which are coupled in series. The counting circuit 141 receives the standby signal STBY and an output signal from the inverter 112 of the control circuit 110 in order to count the number of the transitions of the external control signal CP. In this example, the counting circuit 141 counts a number of rising transitions of the external control signal CP and provide an output signal to the NAND circuit 142 when the number exceeds a predetermined number. The NAND circuit 142 executes a logical operation between the standby signal STBY and an output signal from the counting circuit 141. The inverter 143 inverts an output signal from the NAND circuit 142. The level shift circuit 144 inverts an output signal from the inverter 143. The inverter 145 inverts an output signal from the level shift circuit 144. The inverter 145 operates in accordance with the boosted voltage VDD and the first converted output voltage VEE1 or the second converted output voltage VEE2. The step-down circuit 150 includes an inverter 151, an NAND circuit 152, a NOR circuit 153, a first converting transistor 158, a second converting transistor 154, a plurality of NMOS transistors 155 through 157, and a capacitor C2. In this example, the first converting transistor 158 is an NMOS transistor and the second converting transistor 154 is a PMOS transistor. The inverter 151 is coupled to the inverter 116-2 of the control circuit 110 so as to invert the output signal from the inverter 116-2. The NAND circuit 152 is coupled to the inverter 151 and the inverter 145 of the adjustment circuit 140 so as to execute a logical operation between output signals from the inverters 145 and 151. The NOR circuit 153 is coupled to the inverter 151 and the inverter 145 of the adjustment circuit 140 so as to execute a logical operation between the output signals from the inverters 145 and 151. The first converting transistor 158 includes a gate electrode which is coupled to the NOR circuit 153, a source electrode which is coupled to the first electrical source terminal T1 and a drain electrode which is coupled to a third node 130a. The first converting transistor 158 receives the first converted output voltage VEE1 or the second converted output voltage VEE2 as its substrate voltage. The second converting transistor 154 includes a gate electrode which is coupled to the NAND circuit 152, a source electrode which is coupled to the output terminal 125 of the first voltage generating circuit 120 and a drain electrode which is coupled to the third node 130a. The second converting transistor 154 receives the boosted voltage VDD as its substrate voltage. That is, the first converting transistor 158 and the second converting transistor 154 are coupled in series between the output terminal 125 of the first voltage generating circuit 120 and the first electrical source terminal T1. Also, the source electrode of the first converting transistor 158 receives the first external power supply voltage VCC1, and the source electrode of the second converting transistor 154 receives the boosted voltage VDD. The NMOS transistor 155 includes a gate electrode which is coupled to the inverter 119-2 of the control circuit 110, a source electrode which is coupled to the reference electrical source terminal T0 and a drain electrode which is coupled to the third node 130a. The NMOS transistor 155 receives the first converted output voltage VEE1 or the second converted output voltage VEE2 as its substrate voltage. That is, the second converting transistor 154 and the NMOS transistor 155 are coupled in series between the output terminal 125 of the first voltage generating circuit 120 and the reference electrical source terminal T0. The NMOS transistor 156 includes a gate electrode which is coupled to the inverter 116-3 of the control circuit 110, a source electrode which is coupled to the reference electrical source terminal T0 and a drain electrode which is coupled to a fourth node 130b. The NMOS transistor 156 receives the first converted output voltage VEE1 or the second converted output voltage VEE2 as its substrate voltage. The NMOS transistor 157 includes a gate electrode which is coupled to the inverter 119-2 of the control circuit 110, a source electrode which is coupled to the fourth node and a drain electrode which is coupled to an output terminal 159 of the second voltage generating circuit 130. The NMOS transistor 157 receives the first converted output voltage VEE1 or the second converted output voltage VEE2 as its substrate voltage. The capacitor C2 includes one electrode which is coupled to the third node 130a and another electrode which is coupled to the fourth node 130b.
The operation of the semiconductor integrated circuit 100 according to the first preferred embodiment of the present invention is described below. FIG. 4 is a signal waveform diagram for describing the operation of the semiconductor integrated circuit 100 in
First of all, the generation of the boosting voltage VDD in the semiconductor integrated circuit 100 is described below. In the semiconductor integrated circuit 100, the external control signal CP can be input to the semiconductor integrated circuit 100 after the standby signal STBY is turned from a “Low” level (hereinafter referred to as the “L” level) to a “High” level (hereinafter referred to as the “H” level). Hereupon, when the standby signal STBY is kept at the “L” level, the semiconductor integrated circuit 100 is in a standby state. When the external control signal CP is turned from the “L” level to the “H” level, the timing adjustment circuit 113 receives a signal which is turned to the “H” level through the NAND circuit 111 and the inverter 112. Then, the second adjustment signal 113b is turned from the “L” level to the “H” level. That is, the inverter 117 provides the output signal which is turned to the “L” level. Therefore, the NMOS transistor 124 of the first voltage generating circuit 120 is turned OFF. Hereupon, when the NMOS transistor 124 is turned OFF, an electrical current does not pass through the NMOS transistor 124. Shortly after the transition of the second adjustment signal 113b, the first adjustment signal 113a is turned from the “L” level to the “H” level. That is, the inverter 114 provides the output signal which is turned to the “L” level. Therefore, the first boosting transistor (PMOS transistor) 121 of the first voltage generating circuit 120 is turned ON. Hereupon, when the first boosting transistor 121 is turned ON, an electrical current passes through the first boosting transistor 121. As described above, since the NMOS transistor 124 is turned OFF and the first boosting transistor 121 is turned ON, an electrical potential of the first node 120a is increased from the ground voltage VSS to the second external power supply voltage VCC2. Meanwhile, the second boosting transistor (PMOS transistor) 122 is turned ON and the PMOS transistor 123 is turned OFF, before the first and second adjustment signals 113a and 113b are turned to the “H” level. That is, an electrical potential of the second node 120b is kept at the first external power supply voltage VCC1 before the first and second adjustment signals 113a and 113b are turned to the “H” level as shown in
Thereafter, the external control signal CP is turned from the “H” level to the “L” level, and then the first adjustment signal 113a is turned from the “H” level to the “L” level. That is, the inverter 114 provides the output signal which is turned to the “H” level. Therefore, the first boosting transistor 121 of the first voltage generating circuit 120 is turned OFF. Shortly after the transition of the first adjustment signal 113a, the second adjustment signal 113b is turned from the “H” level to the “L” level. That is, the inverter 117 provides the output signal which is turned to the “H” level. Therefore, the NMOS transistor 124 of the first voltage generating circuit 120 is turned ON. Accordingly, the electrical potential of the second node 120b temporarily becomes less than the first external power supply voltage VCC1 through the capacitor C1 as shown in
Next, the generation of the first converted output voltage VEE1 or the second converted output voltage VEE2 in the semiconductor integrated circuit 100 is described below. When the standby signal STBY is turned from the “L” level to the “H” level, the external control signal CP can be input to the semiconductor integrated circuit 100 and the counting circuit 141 of the adjustment circuit 140 can operate in order to count a number of transitions of the external control signal CP. Before the counted number of the counting circuit 141 does not exceed the predetermined number, the counting circuit 141 provides the output signal which is kept at the “L” level to the NAND circuit 142. Since the standby signal STBY is kept at the “H” level at this time, the NOR circuit 153 of the step-down circuit 150 receives an adjustment signal S140 which is kept at the “L” level through the inverter 143, the level shift circuit 144 and the inverter 145.
When the external control signal CP is turned from the “L” level to the “H” level, the inverter 116-2 of the control circuit 110 provides the signal which is kept at the “L” level to the NOR circuit 153. Therefore, the gate electrode of the first converting transistor 158 receives a signal which is turned to the “H” level from the NOR circuit 153. That is, the first converting transistor 158 is turned ON. Also, since the inverter 116-2 of the control circuit 110 provides the signal which is kept at the “L” level to the inverter 151, the NAND circuit 152 receives a signal which is turned to the “H” level from the inverter 151. Meanwhile, the NAND circuit 152 receives the adjustment signal S140 from the inverter 145 of the adjustment circuit 140. Therefore, the gate electrode of the second converting transistor 154 receives a signal which is turned to the “H” level from the NAND circuit 152. That is, the second converting transistor 154 is turned OFF. Furthermore, at this time, the gate electrode of the NMOS transistor 155 receives a signal which is turned to the “L” level from the inverter 119-2 of the control circuit 110. That is, the NMOS transistor 155 is turned OFF. Accordingly, an electrical potential of the third node 130a is increased to the first external power supply voltage VCC1 from which a threshold voltage Vt of the first converting transistor 158 is subtracted. That is, the capacitor C2 is charged by the first external power supply voltage VCC1. As a result, an electrical potential of the fourth node 130b begins to increase through the capacitor C2, toward the first external power supply voltage VCC1 from which the threshold voltage Vt of the first converting transistor 158 is subtracted. However, on the other hand, when the first adjustment signal 113a is turned from the “L” level to the “H” level, the gate electrode of the NMOS transistor 156 receives a signal which is turned to the “H” level from the inverter 116-3 of the control circuit 110. Likewise, when the second adjustment signal 113b is turned from the “L” level to the “H” level, the gate electrode of the NMOS transistor 157 receives a signal which is turned to the “L” level from the inverter 119-2 of the control circuit 110. That is, the NMOS transistor 156 is turned ON and the NMOS transistor 157 is turned OFF. Accordingly, the electrical potential of the fourth node 130b is kept at the ground voltage VSS.
Then, the external control signal CP is turned from the “H” level to the “L” level, and then the first adjustment signal 113a is turned from the “H” level to the “L” level. At this time, the NOR circuit 153 of the step-down circuit 150 receives a signal which is turned to the “H” level from the inverter 116-2 of the control circuit 110. Therefore, the gate electrode of the first converting transistor 158 receives a signal which is turned to the “L” level from the NOR circuit 153. That is, the first converting transistor 158 is turned OFF. Shortly after the transition of the first adjustment signal 113a, the second adjustment signal 113b is turned from the “H” level to the “L” level. Therefore, the gate electrode of the NMOS 155 receives a signal which is turned to the “H” level from the inverter 119-2 of the control circuit 110. That is, the NMOS transistor 155 is turned ON. As a result, the electrical potential of the third node 130a is turned, from the first external power supply voltage VCC1 from which the threshold voltage Vt of the first converting transistor 158 is subtracted, toward the ground voltage VSS as shown in
Thereafter, when the counted number of the counting circuit 141 exceeds the predetermined number, the counting circuit 141 generates the output signal which is turned from the “L” level to the “H” level for the NAND circuit 142. Since the standby signal STBY is kept at the “H” level at this time, the adjustment signal S140 is turned from the “L” level to the “H” level. At this time, the gate electrode of the first converting transistor 158 receives the signal which is turned to the “L” level from the NOR circuit 153. That is, the first converting transistor 158 is turned OFF. Also, though the gate electrode of the second converting transistor 154 receives the signal which is turned to the “H” level from the NAND circuit 152, the boosted voltage VDD is so great that difference in potential between the gate electrode and the source electrode of the second converting transistor 154 exceeds the threshold voltage Vt of the second converting transistor 154. That is, the second converting transistor 154 is turned ON. As a result, the electrical potential of the third node 130a is changed based on the boosted voltage VDD which is output from the first voltage generating circuit 120. That is, the second converted output voltage VEE2 is generated from the output terminal 159, based on the boosted voltage VDD. By further repeating the operation as described above in the semiconductor integrated circuit 100, the electrical potential of the output terminal 159 of the second voltage generating circuit 130 may be decreased substantially until an electrical potential which is less than the ground voltage VSS by the boosted voltage VDD.
According to the first preferred embodiment, the second voltage generating circuit is coupled to the first electrical source terminal and the first voltage generating circuit to generate the converted voltage which is different than the boosted voltage. That is, the second voltage generating circuit generates a first converted output voltage based on the first external power supply voltage, and thereafter generates a second converted output voltage based on the boosted voltage. Therefore, the parasitic bipolar transistors may be suppressed from appearing in the semiconductor integrated circuit, even if the electrical charge in the boosted voltage is consumed to be decreased. As a result, the latch-up phenomenon may be suppressed from appearing in the semiconductor integrated circuit. Also, since it is not necessary that the diode is coupled to the output terminal of the first voltage generating circuit, the costs and processes to manufacture the semiconductor integrated circuit may be decreased.
The semiconductor integrated circuit 200 includes a control circuit 210, a first voltage generating circuit 220 and a second voltage generating circuit 230. The first voltage generating circuit 220 generates the boosted voltage VDD based on the first external power supply voltage VCC1 and the second external power supply voltage VCC2. The second voltage generating circuit 230 generates the first converted output voltage VEE1 based on the first external power supply voltage VCC1 and generates the second converted output voltage VEE2 based on the boosted voltage VDD, as well as the first and second voltage generating circuits 120 and 130 according to the first preferred embodiment.
The second voltage generating circuit 230 includes the adjustment circuit 240 and a step-down circuit 250. The step-down circuit 250 is similar to the step-down circuit 150 according to the first preferred embodiment. The adjustment circuit 240 includes a monitoring circuit 241, a level shift circuit 242 and an inverter 243 which are coupled in series. The monitoring circuit 241 is coupled to the output terminal 225 of the first voltage generating circuit 220, in order to monitor changes in the boosted voltage VDD and control the first converting transistor 258 and the second converting transistor 254 of the step-down circuit 250 in accordance with the changes in the boosted voltage VDD. The level shift circuit 242 inverts an output signal which is output from the monitoring circuit 241. The inverter 243 generates an adjustment signal S240 based on a signal which is output from the level shift circuit 242, for the NAND circuit 252 and the NOR circuit 253 of the step-down circuit 250.
The operation of the semiconductor integrated circuit 200 according to the second preferred embodiment of the present invention is described below.
While the boosted voltage VDD is increased by the first voltage generating circuit 220, the change in the boosted voltage VDD is monitored by the monitoring circuit 241. The monitoring circuit 241 provides the output signal which is kept at the “L” level to the level shift circuit 242 before the boosted voltage VDD does not exceed a predetermined level. Meanwhile, the monitoring circuit 241 provides the output signal which is kept at the “H” level to the level shift circuit 242 after the boosted voltage VDD exceeds the predetermined level. When the standby signal STBY is turned from the “L” level to the “H” level and the external control signal CP is turned from the “L” level to the “H” level, the inverter 216-2 of the control circuit 210 provides the signal which is kept at the “L” level to the NOR circuit 253 of the step-down circuit 250. On the other hand, as shown in
Then, the external control signal CP is turned from the “H” level to the “L” level, and then the first adjustment signal 213a is turned from the “H” level to the “L” level. At this time, the NOR circuit 253 of the step-down circuit 250 receives a signal which is turned to the “H” level from the inverter 216-2 of the control circuit 210. Therefore, the gate electrode of the first converting transistor 258 receives a signal which is turned to the “L” level from the NOR circuit 253. That is, the first converting transistor 258 is turned OFF. Shortly after the transition of the first adjustment signal 213a, the second adjustment signal 213b is turned from the “H” level to the “L” level. Therefore, the gate electrode of the NMOS 255 receives a signal which is turned to the “H” level from the inverter 219-2 of the control circuit 210. That is, the NMOS transistor 255 is turned ON. As a result, the electrical potential of the third node 230a is turned, from the first external power supply voltage VCC1 from which the threshold voltage Vt of the first converting transistor 258 is subtracted, toward the ground voltage VSS as shown in
Thereafter, after the boosted voltage VDD exceeds the predetermined level, the PMOS transistor 403 is turned ON. Then, the electrical potential of the first intermediate node N1 is turned to the “H” level, and the electrical potential of the second intermediate node N2 is turned to the “L” level. Therefore, the NOR circuit 410 generates the signal which is turned to the “H” level so that the NMOS transistor 404 is turned OFF. Accordingly, the inverter 409 generates a signal which is kept at the “H” level. That is, the monitoring circuit 241 provides the output signal which is kept at the “H” level as the adjustment signal S240, to the level shift circuit 242, after the boosted voltage VDD exceeds the predetermined level. At this time, the gate electrode of the first converting transistor 258 receives the signal which is turned to the “L” level from the NOR circuit 253. That is, the first converting transistor 258 is turned OFF. Also, though the gate electrode of the second converting transistor 254 receives the signal which is turned to the “H” level from the NAND circuit 252, the boosted voltage VDD is so great that difference in potential between the gate electrode and the source electrode of the second converting transistor 254 exceeds the threshold voltage Vt of the second converting transistor 254. That is, the second converting transistor 254 is turned ON. As a result, the electrical potential of the third node 230a is changed based on the boosted voltage VDD which is output from the first voltage generating circuit 220. That is, the second converted output voltage VEE2 is generated from the output terminal 259, based on the boosted voltage VDD. By further repeating the operation as described above in the semiconductor integrated circuit 200, the electrical potential of the output terminal 259 of the second voltage generating circuit 230 may be decreased substantially until an electrical potential which is less than the ground voltage VSS by the boosted voltage VDD.
According to the second preferred embodiment, the second voltage generating circuit is coupled to the first electrical source terminal and the first voltage generating circuit to generate the converted voltage which is different than the boosted voltage. That is, the second voltage generating circuit generates the first converted output voltage based on the first external power supply voltage, and thereafter generates the second converted output voltage based on the boosted voltage. Therefore, the parasitic bipolar transistors may be suppressed from appearing in the semiconductor integrated circuit, even if the electrical charge in the boosted voltage is consumed to be decreased. As a result, the latch-up phenomenon may be suppressed from appearing in the semiconductor integrated circuit. Also, since it is not necessary that the diode is coupled to the output terminal of the first voltage generating circuit, the costs and processes to manufacture the semiconductor integrated circuit may be decreased.
| Number | Date | Country | Kind |
|---|---|---|---|
| 307333/2004 | Oct 2004 | JP | national |
