Claims
- 1. A semiconductor integrated circuit comprising:
a power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a detection signal output circuit which receives the output voltages of said power supply voltage detecting circuit, and outputs a first detection signal when said power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to a second voltage lower than the first voltage.
- 2. The semiconductor integrated circuit according to claim 1, wherein the detection signal output circuit comprises a Schmitt trigger circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-230478 |
Aug 1998 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent application Ser. No. 10/200,152, filed Jul. 23, 2002, which is a divisional of U.S. patent application Ser. No. 10/023,946, filed Dec. 21, 2001 (now abandoned), which is a divisional of U.S. patent application Ser. No. 09/375,370, filed Aug. 17, 1999, now U.S. Pat. No. 6,351,179, issued Feb. 26, 2002, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 10-230478, filed Aug. 17, 1998, the entire contents of which are incorporated herein by reference.
Divisions (2)
|
Number |
Date |
Country |
Parent |
10023946 |
Dec 2001 |
US |
Child |
10200152 |
Jul 2002 |
US |
Parent |
09375370 |
Aug 1999 |
US |
Child |
10023946 |
Dec 2001 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
10200152 |
Jul 2002 |
US |
Child |
10443820 |
May 2003 |
US |