The present application claims priority from Japanese patent application No. 2005-100526 filed on Mar. 31, 2005, the content of which is hereby incorporated by reference into this application.
The present invention relates to a semiconductor integrated circuit, and particularly to a technique effective when applied to a semiconductor integrated circuit equipped with a temperature sensor circuit.
As an example of a temperature detector or sensor circuit using a temperature coefficient of a forward voltage of a pn junction based on a bandgap, there has been known a patent document 1 (Japanese Unexamined Patent Publication No. Hei 07(1995)-218347). As an example illustrative of a reference voltage circuit and a temperature sensor circuit using the same, there has been known a patent document 2 (Japanese Unexamined Patent Publication No. 10(1998)-009967).
The patent documents 1 and 2 are disclosed assuming that a temperature sense signal is compared with a reference voltage having no temperature dependence. Therefore, a temperature gradient of the temperature sense signal is uniquely determined by a resistance ratio between resistive elements set so as to cancel the temperature dependence. It is thus not possible to arbitrarily set the temperature gradient. There is no idea that a temperature sense signal is outputted from outside a semiconductor integrated circuit, and there is a limit to its uses. When the temperature sensor circuit is mounted in a CMOS integrated circuit, an input offset of an operational amplifier configured by a CMOS circuit, which performs amplification/feedback, varies greatly, and a trimming circuit for correcting it is required. From the viewpoint of these, the usability thereof becomes poor where the temperature sensor circuit is mounted in the CMOS integrated circuit in particular.
An object of the present invention is to provide a semiconductor integrated circuit equipped with a temperature sensor circuit suitable for a CMOS process and capable of setting an arbitrary temperature gradient. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a representative one of the inventions disclosed in the present application will briefly be explained as follows: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and each of second transistors each having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common. A temperature sense voltage is formed from a connecting point of the first and second resistors.
A temperature sense signal resistant to offset of a differential amplifier circuit and having an arbitrary temperature gradient is obtained and a circuit can be configured in a CMOS process.
A circuit diagram of one embodiment of a temperature detector or sensor circuit according to the present invention is shown in
The temperature sensor circuit according to the present embodiment comprises a bandgap generating section and an amplification/feedback section. The bandgap generating section comprises npn type bipolar transistors npn0 and npn1 through npnm, and resistors R1 through R4. The transistors npn0 and npn1 through npnm are constituted of transistors identical in size to one another. The transistors npn1 through npnm are connected in parallel. Thus, these transistors npn0 and npn1 through npnm respectively constitute a first transistor comprised of the transistor npn0, and second transistors each formed in a size equal to m times the size of the first transistor. That is, when the same emitter currents Ie1 and Ie2 are caused to flow through the first transistor npn0 and the second transistors npn1 through npnm, an emitter current density of the first transistor npn0 is set large so as to reach m times the emitter current density of each of the second transistors npn through npnm in correspondence with such a size ratio as described above. On the contrary, the emitter current densities of the second transistors npn1 through npnm are set small to 1/m of the emitter current density of the first transistor.
In association with the difference between the emitter current densities of the transistors, base-to-emitter voltages Vbe1 and Vbe2 of the first transistor npn0 and second transistors npn1 through npnm are held in such a relationship that the base-to-emitter voltage Vbe1 of the first transistor npn0 is increased by a constant voltage ΔVbe corresponding to a silicon bandgap. The bases of the first transistor npn0 and second transistors npn1 through npnm are connected in common. The emitters of the second transistors npn1 through npnm are connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the emitter of the first transitory npn0. Thus, the constant voltage ΔVbe is applied across the resistor R3, where the corresponding constant current Ie2 is formed. The resistor R4 is provided between the emitter of the first transistor npn0 and a ground potential gnd of the circuit.
The resistors R1 and R2 formed so as to have the same resistance value are respectively provided between the collectors of the first transistor npn0 and second transistors npn1 through npnm and a power supply voltage Vext supplied from an external terminal. Collector voltages of the first transistor npn0 and second transistors npn1 through npnm are supplied to their corresponding positive-phase and negative-phase inputs (+) and (−) of a differential amplifier circuit Ampnd of a CMOS configuration, where amplification/feedback thereof is performed. That is, a signal outputted from the differential amplifier circuit Ampnd is fed back to the bases of the first transitory npn0 and second transistors npn1 through npnm.
The operation of the bandgap generating section or circuit is as follows. The base-to-emitter voltage Vbe of each bipolar transistor has a characteristic of a voltage coefficient negative relative to the temperature. If this is corrected based on the difference ΔVbe between the base-to-emitter voltages Vbe1 and Vbe2 each having a voltage coefficient positive relative to the temperature, then a reference voltage Vbgr independent on the temperature can be obtained from the output of the differential amplifier circuit Ampnd. The first transistor and second transistors shown in
When the voltage outputted from the CMOS differential amplifier circuit Ampnd is assumed to be a reference voltage Vbgr in the present embodiment, the following equation (1) is established:
Vbgr=Vbe1+Ie·R4=Vbe1+(Ie1+Ie2)·R4 (1)
Now, the emitter current Ie2 is given as expressed in the following equation (2) from the difference ΔVbe between the base-to-emitter voltages Vbe1 and Vbe2 of the first transistor npn0 and second transistors npn1 through npnm. The emitter current Ie2 is set so as to be Ie2=Ie1.
Ie2=ΔVbe/R3=kT/q·ln(m)/R3 (2)
Substituting the above equation (2) in the equation (1) yields the following equation (3).
If the resistance value of the resistor R4 is set so as to cancel a negative temperature coefficient of the first term in the equation (1), then the reference voltage Vbgr independent on the temperature can be obtained. That is, the voltage generated at the resistor R4 is a voltage having such a positive temperature coefficient as to cancel the negative temperature coefficient of the Vbe2. This therefore means that a temperature detect or sense signal Vtsense having a positive temperature coefficient can be obtained by the resistor R4. From the equation (2), it is important that an error between the emitter currents Ie2 and Ie1 needs to be small to obtain a high-accuracy constant voltage ΔVbe. The temperature sense signal Vtsense and the reference voltage Vbgr are formed based on such a ΔVbe. In order to obtain the reference voltage Vbgr from the equation (3), a resistance ratio between R3 and R4 is selected so as to cancel the negative voltage coefficient of the base-to-emitter voltage Vbe2 of the first transistor, whereby the reference voltage Vbgr low in temperature dependence can be obtained.
The present embodiment does not persist in the fixedly setting of the output voltage of the differential amplifier circuit Ampnd to the temperature-compensated reference voltage Vbgr as described above. That is, the resistance value of the resistor R4 is not uniquely determined for the temperature compensation. Since the emitter current Ie1 of the first transistor npn0 and the emitter current Ie2 of each of the second transistors npn1 through npnm are controlled so as to be equal to each other in the feedback circuit, the temperature sense signal Vtsense formed by the resistor R4 is determined from the following equation (4):
Vtsense=(Ie1+Ie2)·R4=2kT/q·R4/R3·ln(m) (4)
In the equation (4), the temperature sense signal Vtsense means that its temperature gradient can be set by the resistance ratio of R4/R3. That is, the temperature characteristic of the temperature sense signal Vtsense, indicating the relationship between a temperature T (° C.) and a voltage V, which is shown in
There may be cases where when the CMOS differential amplifier circuit is used as the differential amplifier circuit which performs amplification/feedback in such a bandgap circuit, an offset voltage Vos occurs due to variations in the threshold voltage Vth of a MOS transistor of an input section. Incidentally, Vos in
On the other hand, in the reference voltage generator as shown in the patent document 2, an offset voltage Vos is amplified by a feedback amplifier circuit and the emitter current values of two pairs of transistors, forming ΔVbe are erroneously corrected by such a feedback operation. Therefore, the circuit described in the patent document 1 is unfit for the circuit using the elements formed in the CMOS process. It is considered that when formed in the CMOS process, a circuit for trimming or the like is additionally required.
Incidentally, when the circuit shown in
The influence of the offset voltage Vos on the temperature sense signal Vtsense can be expressed in the following equations (5) and (6). In the equations, R1=R2=R, and hFE indicates current amplification gains of the first transistor and second transistors.
dVtsense/dVos=(R4/αR)·(1+2/ln(m))˜R4/αR (5)
α=hFE/hFE+1 (6)
If adequate numeric values are assumed as design values for the resistance values and current amplification gain hFE like, for example, R1=R2=500 KΩ, R3=30 kΩ and R4=150 kΩ, and hFE=10 in the equation (5), a variation is calculated as approximately 0.33. Incidentally, although variations in resistor and hFE per se due to a semiconductor manufacturing process also exist in general, the variations become small as compared with pair variations of a differential MOSFET pair of an amplifier, and the like.
A circuit diagram of another embodiment of a temperature sensor circuit according to the present invention is shown in
The collectors and bases of the third and fourth transistors are connected to a circuit's ground potential gnd to provide a diode configuration. One end of the resistor R3 is connected to the emitters of the fourth transistors pnp1 through pnpm and the resistor R2 is connected to the other end thereof to provide or form a series configuration. One end of the resistor R1 is connected to the emitter of the third transistor pnp0. The other ends of the resistors R1 and R2 are connected to the drain of the driver MOSFET pm10 in common. And an emitter voltage Vbe1 of the third transistor and a potential at a connecting point of the resistors R3 and R2 are inputted to the differential amplifier circuit Amppd from which its output signal is fed back to the gate of the driver MOSFET pm10.
Since the differential amplifier circuit Amppd functions so as to make both input voltages equal to each other in the present embodiment, a voltage ΔVbe corresponding to a difference between a base-to-emitter voltage Vbe1 of the third transistor pnp0 and a base-to-emitter voltage Vbe2 of each of the fourth transistors pnp1 through pnpm is supplied to the resistor R3 to form an emitter current Ie2 corresponding to a constant current. A current generated from the driver MOSFET pm10 is supplied in such a manner that the current Ie2 and an emitter current Ie1 of the third transistor pnp0 become equal to each other with R1=R2. That is, the output voltage of the differential amplifier circuit Amppd is formed in such a manner that the drain current of the driver MOSFET pm10 is equally distributed to the third transistor pnp0 and fourth transistors pnp1 through pnpm.
In the temperature sensor circuit, a temperature signal Vtemp is defined as a temperature sense signal Vtsense with the drain of the driver MOSFET pm10 as a reference voltage Vbgr as expressed in the following equation (7). In the equation (7), R1=R2=R.
Vtemp=Vbgr−Vtsense=kT/q·R/R3·ln (m) (7)
Since the present temperature sensor circuit also takes a bandgap reference type circuit configuration having a feedback loop, it has a difference in potential relatively large like the temperature signal Vtemp at both ends of the resistor R2. Therefore, the temperature sensor circuit is capable of producing an output at, for example, double gain and outputting it as the temperature signal Vtemp. Thus, when an equal current is caused to simply flow through diodes different in emitter ratio, an error can be reduced as compared with a method for gain-doubling a small potential difference obtained from voltages that appear on their current injection sides by means of an amplifier.
The influence of the output voltage Vtemp on a variation in offset voltage Vos similar to the above, of the differential amplifier circuit Amppd can be expressed in the following equation (8):
dVtemp/dVos=R/R3+1/ln (m) (8)
If adequate numeric values are assumed as design values for the resistance values like, for example, R=R1=R2=800KΩ, R3=100kΩ, and m=23 in the equation (8), a variation is calculated as approximately 8.32. Thus, when consideration is given to only the offset voltage Vos similar to the above, of the differential amplifier circuit Amppd, the adoption of the circuit configuration like the temperature sensor circuit shown in
A circuit diagram of a further embodiment of a temperature sensor circuit according to the present invention is shown in
A block diagram of one embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
The present embodiment is provided with the function of monitoring the temperature in the system LSI as an in-chip temperature by means of the temperature sensor circuit TSENSE and varying the frequency of the operating clock clk supplied to the central processing unit CPU to thereby suppress a rise in temperature in the system LSI. In the present embodiment, a voltage Vtsense0 directly proportional to the temperature of the temperature sensor circuit TSENSE placed within the system LSI (chip) is therefore transferred to an A/D converter ADC placed outside the chip through an analog buffer ABUF as a voltage Vtsensel. The A/D converter ADC converts the voltage Vtsensel to digital signals d0 through d(n-1) of n bits. The so-converted temperature information do through d(n-1) are transferred to the central processing unit CPU through the input/output interface I/O. That is, the central processing unit CPU receives therein a digital value corresponding to the voltage Vtsense0 directly proportional to the temperature.
The central processing unit CPU generates a clock control signal clkctrl by reference to temperature information on the received digital value, and a table showing a suitable relationship between each predetermined temperature and a clock frequency, or information indicative of a target temperature range and transfers it to the clock generator CLKGEN. The clock generator CLKGEN changes the operating clock clk supplied to the central processing unit CPU in accordance with the clock control signal clkctrl. When, for example, the temperature becomes higher than a constant value, the clock generator CLKGEN controls the frequency of the operating clock clk low to reduce current consumption, thereby decreasing the temperature. When the temperature becomes lower than the constant value in reverse, the clock generator CLKGEN raises the frequency of the operating clock clk to increase current consumption, thereby making an operating speed fast.
A block diagram of another embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A block diagram of a further embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A block diagram of a still further embodiment of a semiconductor integrated circuit equipped with temperature sensor circuits according to the present invention is shown in
A block diagram of a still further embodiment of a semiconductor integrated circuit equipped with temperature sensor circuits according to the present invention is shown in
A block diagram of a still further embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A block diagram of a still further embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A schematic chip layout diagram of one embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A schematic chip layout diagram of another embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A schematic chip layout diagram of a further embodiment of a semiconductor integrated circuit equipped with a temperature sensor circuit according to the present invention is shown in
A schematic chip layout diagram of a still further embodiment of a semiconductor integrated circuit equipped with temperature sensor circuits according to the present invention is shown in
A circuit diagram of one embodiment of a differential amplifier circuit used in a temperature sensor circuit according to the present invention is shown in
A circuit diagram of another embodiment of a differential amplifier circuit used in a temperature sensor circuit according to the present invention is shown in
A circuit diagram of one embodiment of an analog buffer provided in a semiconductor integrated circuit according to the present invention is shown in
A driver section comprises P channel type MOS transistors pm420 and pm430 and N channel type MOS transistors nm420 and nm430, and nm440 and nm450. An output signal out of the driver section is fed back 100% to the basic amplifier section Ampp so that a voltage follower circuit is configured. A voltage supplied to an input in is current-amplified and outputted as an output voltage. A constant current i400 determines an operating current for the basis amplifier section Ampp, and a constant current source i410 determines an operating current for the driver section.
A circuit diagram of one embodiment of an internal voltage setting circuit mounted in a semiconductor integrated circuit according to the present invention is shown in
A basic circuit configuration of the internal voltage setting circuit VREFBUF corresponds to a basic amplifier section Ampn, a driver MOS transistor pm1000, and resistors R300 through R313, R400 and R500. Reference voltage set signals vset0 and vset1 sent from the central processing unit CPU or the like are converted to power supply voltage Vext levels through level shifters LU0 and LU1. Based on those converted into the power supply voltage Vext levels, reference voltages Vref can be switched by pass gates nm0 and pm0 comprised of parallel-configured P channel and N channel MOS transistors, and the like through inverters inv0 through inv13 and logic circuits such as NAND gates nand1 through nand4.
A circuit diagram showing one embodiment of a regulator mounted in a semiconductor integrated circuit according to the present invention is shown in
A schematic device sectional view showing one embodiment of a semiconductor integrated circuit according to the present invention is shown in
These bipolar transistors and MOS transistors are formed by a CMOS process. The npn type bipolar transistor npn0 or the like is constituted of a substrate type structure having an emitter region based on n+, corresponding to each of source and drain regions of the N channel MOS transistor, a base region based on p+ and a P well PW corresponding to a substrate gate (channel section), and a collector region comprising n+, an N well NW for isolation and a deep N well DNW, which correspond to the source and drain regions. Although a p type substrate PSUB is generally supplied with a ground potential gnd, a potential other than one for the p type substrate PSUB can be supplied as a collector potential unlike a parasitic pnp bipolar transistor of a substrate type. That is, the present circuit configuration can be provided as such a circuit configuration that each transistor is connected to the resistors R1 and R2 as shown in
The N channel MOS transistor is configured in such a manner that the n+ regions formed in the P well PW are defined as its source and drain, and a gate electrode constituted of polysilicon polySi is provided on a semiconductor region interposed therebetween through a gate insulating film interposed therebetween. The P well PW is provided with p+ and supplied with a bias voltage (well voltage). The P channel MOS transistor is configured in such a manner that the p+ regions formed in the N well NW are defined as its source and drain, and a gate electrode constituted of polysilicon polySi is provided on a semiconductor region interposed therebetween through a gate insulating film interposed therebetween. The N well NW is provided with n+ and supplied with a bias voltage (well voltage).
A schematic device sectional view illustrating another embodiment of a semiconductor integrated circuit according to the present invention is shown in
A schematic device sectional view depicting a further embodiment of a semiconductor integrated circuit according to the present invention is shown in
While the invention made above by the present inventors has been described specifically on the basis of the preferred embodiments, the present invention is not limited to the embodiments referred to above. Various changes can be made thereto within the scope not departing from the gist thereof. In addition to the case in which the same current is caused to flow through the first and second transistors and the difference between current densities is provided according to an area ratio as in the above embodiment, for example, the first and second transistors are set to the same size and the emitter currents may be caused to flow therethrough at a constant ratio. An area ratio and a current ratio may be utilized in combination. The present invention can widely be used in a temperature sensor circuit mounted in a semiconductor integrated circuit formed in a CMOS process, and various semiconductor integrated circuits each having a circuit built therein, which is formed for reference voltage generation.
Number | Date | Country | Kind |
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2005-100526 | Mar 2005 | JP | national |
Number | Date | Country | |
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Parent | 11390276 | Mar 2006 | US |
Child | 11727559 | Mar 2007 | US |