J.H. Pasternak et al, “CMOS Differential Pass-Transistor Logic Design”, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 216-222. |
K. Yano et al, “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 388-395. |
K. Yano et al, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs”, IEEE 1994 Custom Integrated Circuts Conference, 1994, pp. 603-606. |
Proceedings of the 1994 IEICE Fall Conference, Institute of Electronics, Information and Communication Engineers (IEICE), p. 64, Sasaki et al. “Lean Integration With Pass Transistors”. |