BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a conventional semiconductor junction device that may be used as a transient voltage suppressor for low voltage applications.
FIG. 2 is a cross-sectional view showing an p+ doped semiconductor substrate on which the junction device will be formed.
FIG. 3 shows a p− epi layer that is formed on the substrate.
FIG. 4 shows a PAD oxide layer is formed on the p− epi layer of FIG. 3.
FIG. 5 shows a nitride layer formed on the PAD oxide layer.
FIG. 6 shows a photoresist pattern coated on the nitride layer to define a region in which an interface will be formed.
FIG. 7 shows the nitride layer and the PAD oxide layer after they have been etched.
FIG. 8 shows the device after the nitride layer has been removed and the field oxide formed.
FIG. 9 shows implantation of n-type impurities into the portion of the oxide and the P+ substrate in which the interface is to be formed.
FIG. 10 shows a metal barrier layer formed on the oxide and the interface region.
FIGS. 11 and 12 show the results of a simulation performed on a conventional semiconductor junction device and a semiconductor junction device in accordance with the present invention, respectively.
DETAILED DESCRIPTION
The present inventors have recognized that by altering the manner in which the oxide layer of a semiconductor junction device is formed, the field reducing region located below the field oxide regions can be arranged so that it surrounds the corner of the n+/p+ interface, thereby reducing the leakage current that arises. In particular, the inventors have determined that a local oxidation of silicon (LOCOS) process can be used to form the oxide layer. LOCOS processes are widely used for device isolation applications in the semiconductor industry. In LOCOS processes, a thin layer of silicon oxide (SiO2) is initially grown over the wafer or substrate surface. This thin oxide layer is often referred to as a pad oxide and functions for inhibiting the transition of stresses between the silicon substrate and the subsequently deposited nitride layer. Following this, a layer of silicon nitride is deposited on top of the pad oxide layer and lithographically defined to form an oxidation mask over the active device regions of the wafer. The nitride layer prevents the oxidation of active areas during the isolation oxide growth. The nitride layer is etched from the area between the active areas where an isolating SiO2 layer, which is known as a field oxide, is to be thermally grown over the wafer. In a LOCOS process, the oxidation is generally performed in an oxidation furnace at a temperature range between about 800 C and 1100 C. At this temperature range, wafers are exposed to oxidizing species, such as oxygen or water steam, to grow the field oxides.
FIGS. 2-10 show one example of a process that may be employed to fabricate a semiconductor junction device in accordance with the present invention, which uses a LOCOS insulating region.
FIG. 2 is a cross-sectional view showing a p+ doped semiconductor substrate 202. In FIG. 3 a p-epi layer 204 is formed on the substrate 202 and will define the field reducing region. The p− epi layer 204 is formed in a blanket ion implantation process by implanting n-type ion species into the p+ substrate 202. The dosage and implant energy may be, respectively, from 0 (without implant) to 5×1014 cm2 and 10-200 keV for an arsenic or phosphorus ion implant. Hence, the impurity concentration in the p+ doped substrate 202 is higher than that in the p− epi layer 204.
Next, in FIG. 4, a LOCOS process is begun in which a PAD oxide layer 206 is formed on the p− epi layer 204. PAD oxide layers are generally thermally grown oxides layers that are employed to separate adjacent layers on a substrate or wafer. As previously noted, in the context of a LOCOS process, a PAD oxide is a thin layer of silicon dioxide located beneath a layer of silicon nitride and above the silicon substrate. This layer of oxide serves as a pad or “buffer” to prevent the overlaying silicon nitride (which is in tension) form adversely affecting the silicon substrate. The PAD oxide layer 206 will generally range in thickness from 3000 to 10,000 angstroms.
Referring to FIG. 5, the LOCOS process continues by depositing a nitride layer 220 on the PAD oxide layer 206. In FIG. 6, a photoresist pattern 222 is coated on the nitride layer 220 to define the region in which the Schottky interface will be formed. Subsequently, as shown in FIG. 7, an etch back step is performed to etch the nitride layer 220 by using the photoresist pattern 222 as a mask.
After the etch back step, the photoresist pattern 222 is stripped away and a thermal oxidation process is followed by using the nitride layer 220 as a mask, as is shown in FIGS. 7 and 8. During the thermal oxidation process, a pair of thick field oxide regions 216 are formed by using the nitride layer 220 as a mask. In addition, the ions in the p-region 204 and p+ substrate 202 are driven in both lateral and longitudinal directions into the substrate 202 and results in extending the regions thereof. The nitride layer 220 is then removed, as shown in FIG. 8.
Referring to FIG. 9, an implant process is used to form an n+ junction layer 208 by implanting n-type impurities (e.g., phosphorus ions) into the portion of the oxide and the P+ substrate 202 in which the Schottky interface is to be formed. During this implant process the pad oxide 206 serves not only as a buffer layer between the silicon substrate 202 and the nitride layer 220, but also as a sacrificial oxide for ion implantation to prevent damage to the silicon substrate. After implantation, the pad oxide 206 is removed.
The dosage and implant energy may be about 1×1015 to 1×1016/cm2 and 10-200 keV for arsenic or phosphorus ions. Finally, after implantation a refractory metal barrier layer 210 is deposited in FIG. 10. The refractory metal, can be, for instance, Ti, Ni, Cr, Mo, Pt, Zr, W etc., Subsequently, a top metal layer (not shown) overlies the Schottky barrier layer 210 and serves as an anode. A metal layer is also formed on the backside of substrate to function as a cathode electrode.
As seen in FIG. 10 the small region near the oxide 216 at the interface between the n+ junction layer 208 and the p+ substrate 202 is now surrounded by the field reducing region 204. Simulations have confirmed that the leakage current is reduced in the present invention in comparison to the conventional semiconductor junction device depicted in FIG. 1. For instance, FIG. 11 shows the current distribution at the corner of the junction in the conventional junction device. FIG. 12 shows the current distribution at the corner of the junction in the junction device of the present invention. As the figures indicate, the current density is more uniform in the present invention and thus the leakage current is suppressed.
Another advantage that arises from using a LOCOS process to fabricate the semiconductor junction device depicted above is that only a single photoresist mask is required. In contrast, when the conventional technique is employed two or more masks are generally required.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Patent Application
20080036048
