SEMICONDUCTOR LASER APPARATUS

The disclosure of Japanese Patent Application No. 2008-295005 filed Nov. 19, 2008 including specification, drawings and claims is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to a switching power supply and a semiconductor device used for the same.

BACKGROUND OF THE INVENTION

A switching power supply is used for obtaining an output voltage having a voltage value different from the voltage value of an input power supply voltage. Generally, such a switching power supply generates a predetermined output voltage as follows: pulse width modulation (PWM) control is performed based on the feedback signal of an output voltage and a PWM signal is generated by the PWM control. After that, a main switching element is driven based on the PWM signal and an AC voltage is generated in an energy converter such as a coil and a transformer by driving the main switching element. Further, the AC voltage is rectified and smoothed, so that the predetermined output voltage is generated.

In such a switching power supply, at power-on, the main switching element is caused to perform a switching operation at the maximum on duty of the PWM signal to charge a smoothing capacitor on the output side. Thus an overshoot may occur on the output voltage or an inrush current, which is an excessive current, may occur at power-on. In the event of an overshoot on the output voltage, an output voltage higher than a predetermined value is generated for a certain period of time. The inrush current passes through an energy converter such as a coil and a transformer and the main switching element, so that these members may be broken.

To address this problem, soft start has been proposed in which the on duty of a PWM signal is gradually increased at power-on so as to reduce the overshoot of an output voltage and an inrush current at power-on in a switching power supply. For example, Japanese Patent No. 3251770 discloses a switching power supply for providing such soft start. Referring to FIG. 14, the following will describe the switching power supply of the prior art disclosed in Japanese Patent No. 3251770. FIG. 14 is a circuit diagram showing the switching power supply of the prior art.

As shown in FIG. 14, a power supply switch 102 and a capacitor 103 are provided outside an IC 100 so as to be connected to a terminal 101 of the IC 100. In the IC 100, a constant current source 104 connected to the terminal 101 is provided.

At power-on, the power supply switch 102 is turned off. When the power supply switch 102 is turned off, the capacitor 103 is charged by the constant current source 104. After that, when the voltage of the terminal 101 reaches at least a reference voltage Vf of a comparator 105, a bias circuit 106 starts supplying a power supply voltage Vcc to each circuit block in the IC 100. At power-off, the power supply switch 102 is turned on. When the power supply switch 102 is turned on, the capacitor 103 is discharged. After that, when the voltage of the terminal 101 falls below the reference voltage Vf of the comparator 105, the bias circuit 106 stops supplying the power supply voltage Vcc.

As shown in FIG. 14, the IC 100 includes a switching voltage generating section 111. The switching voltage generating section 111 is made up of a switching transistor 107 acting as a main switching element, a rectifier diode 108, a coil 109 acting as an energy converter, and a smoothing capacitor 110. The switching voltage generating section 111 generates an output voltage having a voltage value different from the voltage value of the power supply voltage Vcc supplied from the bias circuit 106. The output voltage is supplied to a desired circuit as a power supply voltage. The output voltage is also supplied as a feedback signal to an error amplifier 113 through a voltage divider circuit 112 made up of two resistors.

The error amplifier 113 compares the voltage supplied from the voltage divider circuit 112 with a reference voltage Vr, and generates an error signal having a voltage corresponding to a difference between the voltage supplied from the voltage divider circuit 112 and the reference voltage Vr. The error signal is supplied to a PWM comparator 114.

The PWM comparator 114 is a three-input comparator.

The error signal generated by the error amplifier 113, the voltage of the terminal 101, and a reference triangular wave generated by a triangular wave generator 115 are supplied to the PWM comparator 114. The PWM comparator 114 compares lower one of the voltage of the error signal and the voltage of the terminal 101 with the reference triangular wave.

The PWM comparator 114 compares the error signal and the reference triangular wave during a normal operation and generates a pulse signal as a duty ratio corresponding to the voltage of the error signal. The pulse signal is a PWM signal which is supplied to a transistor driver 116. The transistor driver 116 controls the on time of the switching transistor 107 according to the duty ratio of the PWM signal.

As has been discussed, when the power supply switch 102 is turned off at power-on, the voltage of the terminal 101 gradually increases. Thus at power-on, the PWM comparator 114 compares the gradually increasing voltage of the terminal 101 and the reference triangular wave, and generates the PWM signal with a gradually increasing on duty.

With the foregoing configuration, when the output voltage decreases in a normal operation, the voltage of the error signal and the on time of the switching transistor 107 increase, so that the output voltage increases. Contrarily, when the output voltage increases, the on time of the switching transistor 107 decreases, so that the output voltage decreases. Further, at power-on, a gradually increasing voltage of the external capacitor and the reference triangular wave are compared with each other by the PWM comparator and the PWM signal with a gradually increasing on duty is generated. Soft start is performed thus.

Switching power supplies proposed in the prior art perform soft start thus so as to gradually increase the on duty of a PWM signal at power-on.

Some switching power supplies have an overcurrent protection function for a drain current. The drain current is a current passing through a main switching element during the on period of the main switching element.

In a switching power supply having an overcurrent protection function, a soft start circuit has been proposed which suppresses the overcurrent detection value of a drain current at power-on so as to reduce an overshoot of an output voltage and an inrush current at power-on. Such a soft start circuit is disclosed in, for example, Japanese Patent Laid-Open No. 2006-288054.

The soft start circuit includes an error amplifier fed with a reference voltage and a feedback voltage, a first counter for increasing the reference voltage step by step, a comparator for comparing the error output signal of the error amplifier and a triangular wave, a second counter for periodically checking the comparator output signal of the comparator and counting up a count value when an increase in feedback voltage does not reach an increase in reference voltage, an output transistor in which continuity is controlled by the comparator output signal of the comparator, an overcurrent protection circuit for monitoring a drain current passing through the output transistor, a detected current value control circuit for setting, according to the count value of the second counter, the detected current value of the drain current passing through the output transistor, and a current comparator for comparing the drain current monitored by the overcurrent protection circuit and the detected current value set by the detected current value control circuit. In this configuration, the output transistor is a main switching element. The detected current value set by the detected current value control circuit is the overcurrent detection value of the drain current.

The soft start circuit increases the reference voltage of the error amplifier step by step and suppresses the detected current value at power-on. Thus it is possible to reduce an overshoot of the output voltage and an inrush current at power-on.

Moreover, the soft start circuit periodically compares the gradually increasing reference voltage and the feedback voltage. When an increase in feedback voltage does not reach an increase in reference voltage, the soft start circuit steps up the detected current value, which has been suppressed at power-on, as necessary. Thus the output voltage increases to a predetermined value whether a load is large or small.

DISCLOSURE OF THE INVENTION

However, the method of the prior art, in which the on duty of the PWM signal is gradually increased at power-on, has the following problem: in the case of a chopper switching power supply, even when the on duty of a PWM signal is minimized at power-on, a current passing through a main switching element at turn-on has a current value not lower than the rated current value of the main switching element, so that the main switching element may be broken.

To be specific, since an output voltage is nearly zero at power-on, a drain current passing through the main switching element is steeply inclined during the on period of the main switching element, so that the drain current has a high current value when the main switching element is turned off. When the main switching element is turned off, the current value of the drain current is maximized, that is, the drain current has the peak value. Further, when the output voltage is nearly zero, energy accumulated in a coil during the on period of the main switching element hardly decreases during the off period of the main switching element. Thus at power-on, the current waveform of the drain current is placed in continuous mode, so that the initial current value and the peak value of the drain current increase. Moreover, in the chopper switching power supply, when the current waveform of the drain current is placed in the continuous mode, a reverse recovery current Irr of a rectifier diode passes through the rectifier diode via the main switching element when the main switching element is turned on. The reverse recovery current Irr constitutes a part of a spike current. The spike current is obtained by adding, to the reverse recovery current, a current having been charged in a capacitance parasitic on the main switching element, the rectifier diode, and so on during the off period of the main switching element. When the main switching element is turned on, the main switching element is fed with a current having a current value obtained by adding the current value of a spike current component to the initial current value. The higher the initial current value, the higher the current value of the reverse recovery current Irr. Therefore, even when the on duty of the PWM signal is minimized at power-on, the current value of the current passing through the turned-on main switching element is increased in each switching period of the main switching element and the current value soon reaches at least the rated current value of the main switching element, so that the main switching element may be broken.

In the chopper switching power supply, generally, a switching loss is reduced using a fast recovery diode having a short reverse recovery time trr. Hereinafter, the fast recovery diode may be referred to as an FRD. When an FRD is used, the current value of the reverse recovery current Irr is further increased and the main switching element is more likely to be broken.

In the method of the prior art, the overcurrent detection value of the drain current is suppressed at power-on in the switching power supply having an overcurrent protection function for the drain current. The method of the prior art has the following problem: the drain current cannot be limited by the overcurrent detection value at power-on because the main switching element actually has the minimum on period. Thus the peak value of the drain current is not lower than the rated current value of the main switching element, so that the main switching element may be broken.

To be specific, a detection delay time is present from the time the drain current is detected to the time the main switching element is actually turned off. Further, the switching power supply having an overcurrent protection function normally prohibits the drain current from being turned off from the time the main switching element is turned on to the time a certain blanking time elapses, so that the main switching element is not turned off by the spike current. Thus even when the overcurrent detection value of the drain current is suppressed, the main switching element is always turned on in the minimum on period that is obtained by adding the detection delay time to the blanking time. As has been discussed, the current waveform of the drain current is placed in the continuous mode at power-on, so that the initial current value and the peak value of the drain current increase. Thus even when the overcurrent detection value of the drain current is reduced at power-on, minimum pulse driving is repeated in which the main switching element is driven in the minimum on period and the initial current value and the peak value of the drain current increase. Thus the peak value of the drain current gradually increases and soon reaches at least the rated current value of the main switching element, so that the main switching element may be broken.

When the switching power supply having an overcurrent protection function does not have a blanking period, the main switching element is erroneously turned off by the spike current. Thus in this case, a sufficient on time cannot be obtained and necessary energy is not transmitted to the output side, so that the output voltage does not reach a predetermined value and faulty start may occur.

The present invention has been devised in view of the problems of the prior art. An object of the present invention is to provide a switching power supply which can perform soft start for reducing an overshoot of an output voltage and an inrush current at power-on, and can prevent a main switching element from being degraded or damaged by a current not lower than the maximum permissible current value in a soft start period, and a semiconductor device used for the same.

In order to attain the object, a first switching power supply of the present invention includes:

a main switching element for switching a first DC voltage;

a converter circuit for converting the first DC voltage having been switched by the main switching element, to a second DC voltage having a voltage value different from the voltage value of the first DC voltage;

a control circuit for controlling the operation of the main switching element; and

an output voltage detection circuit for feeding back a feedback signal to the control circuit, the feedback signal indicating the voltage value of the second DC voltage,

the control circuit including:

an oscillator circuit for oscillating a signal for determining timing for turning on the main switching element;

an element current detection circuit for generating an element current detection signal indicating the current value of current passing through the main switching element;

a feedback signal control circuit for generating a signal at a signal level corresponding to the voltage value of the second DC voltage based on the feedback signal;

a clamping circuit for generating a clamp signal for fixing the maximum current value of the current passing through the main switching element;

a comparator for generating a signal for determining timing for turning off the main switching element, by comparing lower one of the signal level of the signal generated by the feedback signal control circuit and the signal level of the clamp signal generated by the clamping circuit with the signal level of the element current detection signal;

a switching control signal generating circuit for generating, based on the signal oscillated by the oscillator circuit, a signal for turning on the main switching element, and generating, based on the signal generated by the comparator, a signal for turning off the main switching element;

a driving circuit for generating a driving signal for driving the main switching element, based on the signal generated by the switching control signal generating circuit;

a blanking period generating circuit for prohibiting, based on the driving signal, the main switching element from being turned off from the time the main switching element is turned on to the time a blanking time elapses;

a soft start period generating circuit for generating a soft start period from the start of the oscillation of the main switching element to the lapse of a soft start time; and

a blanking time adjusting circuit for generating a signal for shortening the blanking time in the soft start period as compared with after the lapse of the soft start period.

The switching power supply configured thus can obtain a shorter blanking time than in a normal operation, from the start of the oscillation of the main switching element to the lapse of the soft start period. Thus the on time of the main switching element is shorter in the soft start period than in a normal operation, thereby suppressing the maximum current value of the element current passing through the main switching element, that is, the peak value of the current. Further, in the soft start period, the element current increases in each switching period but an increase in the element current in each switching period is suppressed. Thus it is possible to prevent the main switching element from being degraded or damaged by a current not lower than the maximum permissible current value. Even when the waveform of the element current is considerably inclined, that is, even when the element current increases at a high rate in each switching period or the second DC voltage serving as an output voltage is nearly zero and energy accumulated in an energy converter such as a coil and a transformer hardly decreases in the off period of the main switching element, the peak value of the element current is suppressed and an increase in the element current in each switching period is suppressed because the on time of the main switching element is short. Thus it is possible to prevent the main switching element from being degraded or damaged.

Further, the blanking time adjusting circuit may increase the blanking time in the soft start period from the minimum value at the start of the soft start period.

The switching power supply configured thus can gradually increase the blanking time during the soft start period and smoothly shift the blanking time to duration necessary for a normal operation after the lapse of the soft start period.

Moreover, the clamping circuit may reduce the signal level of the clamp signal in the soft start period as compared with after the lapse of the soft start period. Further, the clamping circuit may increase the signal level of the clamp signal in the soft start period from the minimum value at the start of the soft start period.

The switching power supply configured thus can suppress the current value of the element current passing during the off period of the main switching element, even when the current waveform of the element current passing through the main switching element is placed in continuous mode. Thus it is possible to reduce the current value of the initial current passing through the main switching element when the main switching element is turned on. The current waveform is placed in the continuous mode when the second DC voltage serving as the output voltage is nearly zero and the energy accumulated in the energy converter such as a coil and a transformer hardly decreases in the off period of the main switching element.

Moreover, when the signal level of the clamp signal increases in the soft start period, the signal level of the clamp signal is smoothly shifted to a signal level necessary for a normal operation after the lapse of the soft start period. Further, energy transmitted to the output side during the soft start period is gradually increased, so that the second DC voltage serving as the output voltage reaches a predetermined value and faulty start does not occur after the lapse of the soft start period.

Moreover, the blanking period generating circuit may disable one of the element current detection signal generated by the element current detection circuit and the signal generated by the comparator, from the time the main switching element is turned on to the time the blanking time elapses.

Further, the element current detection circuit may generate the element current detection signal based on the on voltage of the main switching element.

In the switching power supply configured thus, it is not necessary to use a detection resistor to detect the element current passing through the main switching element, thereby reducing a loss generated on the detection resistor.

Moreover, the element current detection circuit may include a sub-switching element which is driven with the main switching element in a shared manner and is fed with current having a current value smaller than the current value of the current passing through the main switching element, with a constant ratio relative to the current value of the current passing through the main switching element; and a resistor fed with the current passing through the sub-switching element, and the element current detection circuit may generate the element current detection signal based on a voltage generated on the resistor.

In the switching power supply configured thus, it is not necessary to use the resistor to directly detect the element current passing through the main switching element, thereby reducing a loss generated on the detection resistor. When the element current is detected based on the on voltage of the main switching element, the element current cannot be accurately detected until the input voltage of the main switching element is sufficiently reduced. Generally it takes several hundreds nsec to sufficiently reduce the input voltage of the main switching element, whereas the first switching power supply detects a current passing through the resistor, so that the element current can be accurately detected even immediately after the main switching element is turned on.

In order to attain the object, a second switching power supply includes:

a main switching element for switching a first DC voltage;

a control circuit for controlling the operation of the main switching element; and

an output voltage detection circuit for feeding back a feedback signal to the control circuit, the feedback signal indicating the voltage value of the second DC voltage,

the control circuit including:

an oscillator circuit for oscillating a signal for determining timing for turning on the main switching element;

a driving circuit for generating a driving signal for driving the main switching element; and

a soft start period generating circuit for generating a soft start period from the start of the oscillation of the main switching element to the lapse of a soft start time,

wherein the main switching element is turned on based on the signal oscillated by the oscillator circuit and is turned off based on the feedback signal, and

the driving circuit drives the main switching element such that a time for turning on the main switching element before the lapse of the soft start period is longer than after the lapse of the soft start period.

In the switching power supply configured thus, the turn-on time of the main switching element can be longer than in a normal operation, from the start of the oscillation of the main switching element to the lapse of the soft start period. Thus in a configuration where a reverse recovery current Irr of a rectifier diode passes through the rectifier diode via the main switching element when the main switching element is turned on, even the passage of the large reverse recovery current Irr does not increase the current value of the current passing through the main switching element when the main switching element is turned on. This is because the turn-on time of the main switching element is long and dV/dt and dI/dt are small. It is therefore possible to prevent the main switching element from being degraded or damaged by a current not lower than the maximum permissible current value.

Further, the converter circuit may be made up of a series circuit of a diode, a coil, and a capacitor.

Moreover, the driving circuit may reduce the turn-on drive capability of the main switching element until the lapse of the soft start period, as compared with after the lapse of the soft start period. Thus the turn-on time in the soft start period is longer than in a normal operation after the lapse of the soft start period.

Further, as in the first switching power supply, the control circuit includes:

an element current detection circuit for generating an element current detection signal indicating the current value of current passing through the main switching element;

a feedback signal control circuit for generating a signal at a signal level corresponding to the voltage value of the second DC voltage based on the feedback signal;

a clamping circuit for generating a clamp signal for fixing the maximum current value of the current passing through the main switching element;

a blanking period generating circuit for prohibiting, based on the driving signal generated by the driving circuit, the main switching element from being turned off from the time the main switching element is turned on to the time a blanking time elapses,

wherein the driving circuit may generate the driving signal based on the signal generated by the switching control signal generating circuit.

In this case, as in the first switching power supply, the clamping circuit may reduce the signal level of the clamp signal in the soft start period as compared with after the lapse of the soft start period. Further, the clamping circuit may increase the signal level of the clamp signal in the soft start period from the minimum value at the start of the soft start period.

Moreover, as in the first switching power supply, the control circuit may further include a blanking time adjusting circuit for generating a signal for reducing the blanking time in the soft start period as compared with after the lapse of the soft start period. Further, as in the first switching power supply, the blanking time adjusting circuit may increase the blanking time in the soft start period from the minimum value at the start of the soft start period.

The switching power supply configured thus can obtain a shorter blanking time than in a normal operation until the lapse of the soft start period. Thus the on time of the main switching element is shorter in the soft start period than in a normal operation, thereby suppressing the current value of the element current passing through the main switching element when the main switching element is turned off and suppressing an increase in the element current in each switching period. Thus it is possible to prevent the main switching element from being degraded or damaged by a current not lower than the maximum permissible current value.

When the blanking time is gradually increased during the soft start period, the blanking time is smoothly shifted to duration necessary for a normal operation after the lapse of the soft start period.

Moreover, as in the first switching power supply, the blanking period generating circuit may disable one of the element current detection signal generated by the element current detection circuit and the signal generated by the comparator, from the time the main switching element is turned on to the time the blanking time elapses.

Further, as in the first switching power supply, the element current detection circuit may generate the element current detection signal based on the on voltage of the main switching element.

Moreover, as in the first switching power supply, the element current detection circuit may include a sub-switching element which is driven with the main switching element in a shared manner and is fed with current having a current value smaller than the current value of the current passing through the main switching element, with a constant ratio relative to the current value of the current passing through the main switching element; and a resistor fed with the current passing through the sub-switching element, and the element current detection signal may be generated based on a voltage generated on the resistor.

In the switching power supply configured thus, it is not necessary to use the resistor to directly detect the element current passing through the main switching element, thereby reducing a loss generated on the detection resistor. When the element current is detected based on the on voltage of the main switching element, the element current cannot be accurately detected until the input voltage of the main switching element is sufficiently reduced, whereas the second switching power supply detects a current passing through the resistor, so that the element current can be accurately detected even immediately after the main switching element is turned on.

Further, the soft start period generating circuit may include a constant current source for charging an external capacitor provided outside the control circuit, and generate the soft start period based on the voltage of the external capacitor having been charged by the constant current source.

The switching power supply configured thus can adjust the soft start period according to a constant current value and the capacitance value of the external capacitor.

Moreover, the soft start period generating circuit may include a plurality of constant current sources for charging and discharging an external capacitor provided outside the control circuit; two comparators for detecting the upper limit and the lower limit of the voltage of the external capacitor; a plurality of switches for switching charging and discharging of the external capacitor based on signals generated by the two comparators; and a counter circuit for counting up a count value based on the signals generated by the two comparators, and the soft start period generating circuit may generate the soft start period based on the count value of the counter circuit.

The switching power supply configured thus can adjust the soft start period according to a constant current value, the capacitance value of the external capacitor, and the count value of the counter circuit. Thus the switching power supply can reduce the capacitance value of the external capacitor.

Further, the control circuit may include a regulator for keeping constant the voltage of a power supply for the control circuit based on the first DC voltage; and an external starting terminal, and the control circuit may determine timing for starting the oscillation of the main switching element based on a signal supplied to the external starting terminal.

In the switching power supply of the prior art shown in FIG. 14, the soft start capacitor 103 and the power supply switch 102 for turning on/off a power supply are connected to the single terminal 101 to reduce the number of terminals of the IC 100. However, a delay time occurs from the time the power supply switch 102 is turned off to the time the bias circuit 106 starts supplying the power supply voltage Vcc to each circuit block in the IC 100. The operation of the switching transistor 107 remains stopped from the time the bias circuit 106 starts supplying the power supply voltage Vcc to the time the voltage of the terminal 101 reaches at least the minimum potential of a reference triangular wave, so that the start of the oscillation of the main switching element is further delayed. As a result, a large delay time occurs from the time the power supply switch 102 is turned off to the time the switching transistor 107 actually starts operating.

Unlike in the prior art, as has been discussed, the control circuit for controlling the operation of the main switching element includes the regulator for keeping constant the voltage of the power supply for the control circuit based on the first DC voltage serving as an input power supply voltage; and the external starting terminal fed with a signal for determining timing for starting the oscillation of the main switching element, and the timing for starting the oscillation of the main switching element is determined based on the signal supplied to the external starting terminal, so that the supply of a power supply voltage to the control circuit can be started regardless of the timing for starting the oscillation of the main switching element. Thus it is possible to reduce a delay time from the time the signal supplied to the external starting terminal is generated to the time the main switching element actually starts an oscillation.

Moreover, the switching power supply in which the control circuit includes the regulator and the external starting terminal may include an external starting signal generating circuit for generating an external starting signal when the first DC voltage reaches a predetermined voltage, and the control circuit may determine the timing for starting the oscillation of the main switching element based on the signal supplied to the external starting terminal by the generation of the external starting signal.

A semiconductor device of the present invention is used for one of the switching power supplies, wherein the main switching element and the control circuit are formed on the same semiconductor substrate or are mounted into the same package.

In the semiconductor device configured thus, the main switching element and the control circuit can be mounted into the single package. Thus the switching power supply configured using the semiconductor device can considerably reduce the number of components of the switching power supply, thereby easily reducing the size, weight, and cost of the switching power supply.

According to the switching power supply and the semiconductor device of the present invention, it is possible to perform soft start for reducing an overshoot of an output voltage and an inrush current at power-on and prevent the main switching element from being degraded or damaged by a current not lower than the maximum permissible current value in the soft start period. Thus the switching power supply and the semiconductor device of the present invention are useful as a switching power supply having a soft start function for reducing an overshoot of an output voltage and an inrush current at power-on.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a waveform chart showing a drain current in a normal operation of the switching power supply according to the first embodiment of the present invention;

FIG. 3 is a waveform chart showing the drain current in the soft start period of the switching power supply according to the first embodiment of the present invention in the case where the drain current has a maximum detected current value smaller than that of a normal operation;

FIG. 4 is a waveform chart showing the drain current in the soft start period of the switching power supply according to the first embodiment of the present invention in the case where a blanking time is shorter than that of a normal operation;

FIG. 5 is a waveform chart showing the drain current in the soft start period of the switching power supply according to the first embodiment of the present invention in the case where a blanking time is shorter than that of a normal operation and the drain current has a maximum detected current value smaller than that of a normal operation;

FIG. 6 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a waveform chart showing, in discontinuous mode, a drain current and a regenerated current in a normal operation of the switching power supply according to the second embodiment of the present invention;

FIG. 8 is a waveform chart showing, in continuous mode, the drain current and the regenerated current in a normal operation of the switching power supply according to the second embodiment of the present invention;

FIG. 9 is a waveform chart showing a drain current in the soft start period of a typical chopper switching power supply according to the prior art;

FIG. 10 is a waveform chart showing the drain current in the soft start period of the switching power supply according to the second embodiment of the present invention;

FIG. 11 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a circuit diagram showing an example of a soft start period generating circuit provided in a switching power supply and a semiconductor device according to a fourth embodiment of the present invention;

FIG. 13 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to a fifth embodiment of the present invention; and

FIG. 14 is a circuit diagram showing a switching power supply of the prior art.

DESCRIPTION OF THE EMBODIMENTS

The following will describe embodiments of the present invention with reference to the accompanying drawings. The same members in the drawings are indicated by the same reference numerals and a redundant explanation is omitted. In the following embodiments, a flyback switching power supply and a chopper switching power supply will be exemplarily described. The present invention is not limited to the switching power supplies of these power systems. Further, the chopper switching power supply has an output load of positive polarity but the present invention is also applicable to a switching power supply having an output load of negative polarity. Moreover, the chopper switching power supply is a step-down switching power supply but the present invention is also applicable to a step-up switching power supply. Furthermore, the following embodiments are merely examples of the present invention and the arrangement and the like of the constituent members of the present invention are not limited by the following embodiments. The present invention can be modified in various ways within the scope of the claims.

First Embodiment

FIG. 1 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to a first embodiment of the present invention. In the switching power supply, PWM control of current mode is used as a method of controlling the switching operation of a main switching element.

As shown in FIG. 1, a switching transformer 1 has a primary winding 1a and a secondary winding 1b. The switching transformer 1 is an example of an energy converter. The primary winding la and the secondary winding 1b are opposite in polarity and the switching power supply is a flyback switching power supply.

One end of the primary winding 1a is connected to a terminal IN on a high potential side out of two terminals fed with an input power supply voltage VIN serving as a first DC voltage. Hereinafter, the terminal IN on the high potential side will be referred to as an input power supply terminal IN. The other end of the primary winding 1a is connected to the input terminal of a main switching element 2. The main switching element 2 has the input terminal, an output terminal, and a control terminal. The main switching element 2 is, for example, a high withstand voltage transistor. The output terminal of the main switching element 2 is connected to a terminal RETURN on a low potential side out of the two terminals fed with the input power supply voltage VIN. The control terminal of the main switching element 2 is connected to a gate driving circuit 4 of a control circuit block 3. The main switching element 2 performs a switching operation in response to a driving signal generated by the gate driving circuit 4. The switching operation switches the input power supply voltage VIN.

The secondary winding 1b of the switching transformer 1 is connected to a rectifying/smoothing circuit made up of a rectifier diode 5 and a smoothing capacitor 6. The switching transformer 1 acting as an energy converter, the rectifier diode 5, and the smoothing capacitor 6 constitute an energy converter circuit 7.

The energy converter circuit 7 converts the input power supply voltage VIN, which has been switched by the main switching element 2, to a second DC voltage having a voltage value different from the voltage value of the input power supply voltage VIN. To be specific, the energy converter circuit 7 rectifies and smoothes an AC voltage induced to the secondary winding 1b by the switching operation of the main switching element 2, so that the second DC voltage is generated.

The second DC voltage is applied to a load 8 connected to an output terminal OUT. In other words, the second DC voltage is an output voltage VOUT. An output voltage detection circuit 9 detects the voltage level of the output voltage VOUT and feeds back a feedback signal FB_S, which indicates the detected voltage level, to the control circuit block 3.

The main switching element 2 and the control circuit block 3 are integrated on the same substrate and are included in a semiconductor device 10. The control circuit block 3 controls the operation of the main switching element 2.

The semiconductor device 10 includes a DRAIN terminal, a SOURCE terminal, a VDD terminal, an FB terminal, and an SS terminal as terminals for external connection. The DRAIN terminal is connected to the input terminal of the main switching element 2 and the input terminal of the control circuit block 3. The SOURCE terminal is connected to the output terminal of the main switching element 2 and the reference potential terminal of the control circuit block 3. The VDD terminal is connected to the power supply terminal of the control circuit block 3. The FB terminal is connected to the feedback terminal of the control circuit block 3.

The DRAIN terminal is connected, outside the semiconductor device 10, to the input power supply terminal IN via the primary winding 1a of the switching transformer 1. The SOURCE terminal is connected, outside the semiconductor device 10, to the terminal RETURN. The VDD terminal is connected, outside the semiconductor device 10, to a power supply capacitor 11 acting as a power supply of the control circuit block 3. The FB terminal is fed with the feedback signal FB_S from the output voltage detection circuit 9. The SS terminal is connected to a soft start capacitor 12 outside the semiconductor device 10. The soft start capacitor 12 is an example of an external capacitor provided on the semiconductor device 10.

The control circuit block 3 includes a regulator 13. The regulator 13 is made up of a constant current source and a switch. One end of the regulator 13 is connected to the DRAIN terminal and the other end of the regulator 13 is connected to the VDD terminal. The regulator 13 keeps constant the voltage of the power supply capacitor 11, that is, the voltage of the VDD terminal based on the input power supply voltage VIN supplied to the DRAIN terminal through the primary winding 1a of the switching transformer 1. The VDD terminal voltage is the power supply voltage of the control circuit block 3.

The control circuit block 3 further includes a start/stop circuit 14. The start/stop circuit 14 controls the charging of the power supply capacitor 11 which is charged by the regulator 13. To be specific, the start/stop circuit 14 turns on the switch of the regulator 13 until the VDD terminal voltage reaches a constant voltage. Thus charging current is supplied from the regulator 13 to the VDD terminal. When the VDD terminal voltage reaches at least the constant voltage, the start/stop circuit 14 turns off the switch of the regulator 13, so that the current supply from the regulator 13 to the VDD terminal is stopped. Further, the start/stop circuit 14 generates a starting signal when the VDD terminal voltage reaches a starting voltage, and the start/stop circuit 14 generates a start/stop signal when the VDD terminal voltage decreases to a start/stop voltage.

The control circuit block 3 further includes an oscillator 15. The oscillator 15 is an example of an oscillator circuit. The oscillator 15 oscillates a maximum on-duty cycle signal for determining the maximum on-duty cycle of the main switching element 2 and a clock signal clock for determining the oscillation frequency of the main switching element 2. The clock signal clock determines timing for turning on the main switching element 2.

The control circuit block 3 further includes a drain current detection circuit 16. The drain current detection circuit 16 is an example of an element current detection circuit. The drain current detection circuit 16 detects a drain current IDS which is an element current passing through the main switching element 2, converts the detected drain current IDS to a voltage, and generates an element current detection signal indicating the current value of the drain current IDS. The element current detection signal is a voltage signal. To be specific, the drain current detection circuit 16 detects the on voltage of the main switching element 2. The on voltage is the product of the drain current IDS passing through the main switching element 2 and the on resistance of the main switching element 2. The drain current detection circuit 16 generates the element current detection signal at a voltage level corresponding to the on voltage of the main switching element 2.

The control circuit block 3 further includes a feedback signal control circuit FB 17. The feedback signal control circuit FB 17 generates a signal at a voltage level corresponding to the voltage level of the output voltage VOUT based on the feedback signal FB_S supplied from the output voltage generating circuit 9 to the FB terminal. The signal generated by the feedback signal control circuit FB 17 determines a first reference voltage VR corresponding to the detected value of the drain current IDS. Hereinafter, the detected value of the drain current IDS may be referred to as a detected current value ILIMR. In a normal operation, the drain current IDS is detected by the detected current value ILIMR.

The control circuit block 3 further includes a clamping circuit 18 for overcurrent protection of the drain current IDS. The clamping circuit 18 generates a clamp signal for fixing the maximum current value of the drain current IDS passing through the main switching element 2 or detecting an overcurrent of the drain current IDS. The clamp signal determines a second reference voltage VS corresponding to a maximum detected current value ILIMIT of the drain current IDS. In this case, the second reference voltage VS is the overcurrent detection value of the drain current IDS.

The control circuit block 3 further includes a comparator 19. The comparator 19 compares a lower voltage level of the first reference voltage VR determined by the signal generated by the feedback signal control circuit FB 17 and the second reference voltage VS determined by the clamp signal generated by the clamping circuit 18 and the voltage level of the element current detection signal generated by the drain current detection circuit 16, and the comparator 19 generates a comparison signal indicating the comparison result. The comparison signal determines timing for turning off the main switching element 2.

The control circuit block 3 further includes a switching control signal generating circuit 20 for generating a switching control signal, which is a pulse signal, based on the clock signal clock oscillated by the oscillator 15 and the comparison signal generated by the comparator 19.

To be specific, the switching control signal generating circuit 20 includes a flip-flop circuit 21 and a three-input NAND circuit 22. The set terminal of the flip-flop circuit 21 is fed with the clock signal clock oscillated by the oscillator 15, and the reset terminal of the flip-flop circuit 21 is fed with the comparison signal from the comparator 19. The NAND circuit 22 is fed with a signal from an output terminal Q of the flip-flop circuit 21, the starting signal and the start/stop signal from the start/stop circuit 14, and the maximum on-duty cycle signal oscillated by the oscillator 15. The NAND circuit 22 performs a logic operation on these signals, so that the switching control signal is generated. The switching control signal generating circuit 20 shifts the signal level of the switching control signal to a signal level for turning on the main switching element 2, based on the clock signal clock oscillated by the oscillator 15. Further, the switching control signal generating circuit 20 shifts the signal level of the switching control signal to a signal level for turning off the main switching element 2, based on the comparison signal generated by the comparator 19. Moreover, when the signal for determining the timing for turning off the main switching element 2 is not supplied from the comparator 19 in the maximum on-duty cycle period determined by the maximum on-duty cycle signal oscillated by the oscillator 15, the switching control signal generating circuit 20 shifts the signal level of the switching control signal to the signal level for turning off the main switching element 2, based on the maximum on-duty cycle signal. When the start/stop signal is supplied from the start/stop circuit 14, the switching control signal generating circuit 20 shifts the signal level of the switching control signal to the signal level for turning off the main switching element 2.

The control circuit block 3 further includes the gate driving circuit 4. The gate driving circuit 4 generates the driving signal for driving the main switching element 2, based on the switching control signal from the switching control signal generating circuit 20. To be specific, the gate driving circuit 4 controls the voltage value and the application time of voltage applied to the control terminal of the main switching element 2 and an amount of current supplied to the control terminal of the main switching element 2, based on the switching control signal from the switching control signal generating circuit 20. Thus the amount of the drain current IDS passing through the main switching element 2 is controlled.

The control circuit block 3 further includes a blanking period generating circuit 23. The blanking period generating circuit 23 generates an on-time blanking pulse signal BLK based on the driving signal generated by the gate driving circuit 4. The on-time blanking pulse signal BLK prohibits the main switching element 2 from being turned off from the time the main switching element 2 is turned on to the time a blanking time elapses. A period from the time the main switching element 2 is turned on to the time the blanking time elapses is a blanking period.

To be specific, in the switching power supply, the drain current detection circuit 16 is connected to the comparator 19 via a switch 24. The blanking period generating circuit 23 turns off the switch 24 in response to the on-time blanking pulse signal BLK during the blanking period. Thus the signal generated by the drain current detection circuit 16 is disabled and the main switching element 2 is prohibited from being turned off. After the blanking period, the blanking period generating circuit 23 turns on the switch 24 in response to the on-time blanking pulse signal BLK. Thus the signal generated by the drain current detection circuit 16 becomes valid and the main switching element 2 is allowed to be turned off. The blanking period generating circuit 23 can prevent the main switching element 2 from being erroneously turned off by a spike current generated when the main switching element 2 is turned on.

The control circuit block 3 further includes a soft start period generating circuit 25. The soft start period generating circuit 25 generates a soft start period TSS from the time the main switching element 2 starts oscillation to the time a soft start time elapses.

To be specific, the soft start period generating circuit 25 is made up of a constant current source and a switch. The constant current source is connected via the switch to the soft start capacitor 12 provided outside the SS terminal of the semiconductor device 10. When the switch is turned on in response to the starting signal from the start/stop circuit 14, the constant current source starts charging the soft start capacitor 12. The end of the soft start period TSS is determined by the voltage level of the soft start capacitor 12, that is, an SS terminal voltage.

The control circuit block 3 further includes a blanking time adjusting circuit 26. The blanking time adjusting circuit 26 supplies an adjusting signal for adjusting the blanking time to the blanking period generating circuit 23. The adjusting signal adjusts the blanking time.

To be specific, the SS terminal voltage is transmitted to the blanking time adjusting circuit 26. The blanking time adjusting circuit 26 generates the adjusting signal for shortening the blanking time as compared with in a normal operation after the lapse of the soft start period TSS, until the end of the soft start period TSS determined by the SS terminal voltage. Further, the blanking time adjusting circuit 26 generates the adjusting signal for returning the blanking time to the blanking time of the normal operation after the lapse of the soft start period TSS.

Moreover, in the switching power supply, the SS terminal voltage is also transmitted to the clamping circuit 18. The clamping circuit 18 reduces the voltage level of the clamp signal, that is, the second reference voltage VS serving as an overcurrent detection value as compared with the voltage level of a normal operation after the lapse of the soft start period TSS, until the end of the soft start period TSS determined by the SS terminal voltage.

The following will describe the operations of the switching power supply configured thus.

When the input power supply voltage VIN is applied from the input power supply terminal IN via the primary winding 1a of the switching transformer 1 to the DRAIN terminal connected to the input terminal of the main switching element 2, current is supplied from the regulator 13 of the control circuit block 3 to the power supply capacitor 11 connected to the VDD terminal, so that a VDD terminal voltage increases. The input power supply voltage VIN is a DC voltage (not shown) such as a voltage obtained by rectifying, for example, a commercial AC voltage with a rectifier such as a diode bridge and smoothing the voltage with an input capacitor.

The switch of the regulator 13 is turned on until the VDD terminal voltage reaches the constant voltage, so that current is supplied from the regulator 13 to the VDD terminal. After that, when the VDD terminal voltage reaches at least the constant voltage, the switch of the regulator 13 is turned off, so that the current supply from the regulator 13 to the VDD terminal is stopped and the VDD terminal voltage is kept at a constant potential.

A junction field-effect transistor (FET) may be provided (not shown) between the constant current source of the regulator 13 and the DRAIN terminal. With this configuration, a high voltage applied to the high potential side of the junction FET is pinched off to a low voltage on the low potential side of the junction FET due to the pinch-off effect of the junction FET, so that a high voltage can be directly supplied to the control circuit block 3. Thus it is possible to reduce a power loss caused by a starting resistance and the like, thereby achieving a switching power supply with high power conversion efficiency. This configuration is not limited to the switching power supply of the first embodiment but is also applicable to switching power supplies according to other embodiments.

The start/stop circuit 14 turns on the switch of the regulator 13 until the VDD terminal voltage reaches the constant voltage. When the VDD terminal voltage reaches at least the constant voltage, the switch of the regulator 13 is turned off. The start/stop circuit 14 generates the starting signal when the VDD terminal voltage reaches the starting voltage, and the start/stop circuit 14 generates the start/stop signal when the VDD terminal voltage decreases to the start/stop voltage.

When fed with the starting signal from the start/stop circuit 14, the soft start period generating circuit 25 supplies a constant current from the constant current source to the soft start capacitor 12 connected to the SS terminal, so that the SS terminal voltage increases. The soft start period TSS ranges from the time the starting signal is supplied to the time the SS terminal voltage reaches a constant voltage.

When the starting signal from the start/stop circuit 14 starts the oscillation of the main switching element 2, that is, the switching operation, an AC voltage is induced to the secondary winding 1b and the output voltage VOUT from the energy converter circuit 7 is applied to the load 8 connected to the output terminal OUT.

The output voltage VOUT is detected by the output voltage detection circuit 9. The output voltage detection circuit 9 generates the feedback signal FB_S indicating the voltage level of the output voltage VOUT. The feedback signal FB_S is supplied to the feedback signal control circuit FB 17 of the control circuit block 3 via the FB terminal.

The feedback signal control circuit FB 17 reduces the first reference voltage VR based on the feedback signal FB_S when a load decreases and the output voltage VOUT increases. Contrarily, the feedback signal control circuit FB 17 increases the first reference voltage VR when the load increases and the output voltage VOUT decreases.

In a normal operation after the lapse of the soft start period TSS, the first reference voltage VR corresponding to the detected value of the drain current IDS serves as the reference voltage of the comparator 19. When the load decreases and the first reference voltage VR also decreases, the detected value of the drain current IDS is reduced and the on time of the main switching element 2 is shortened, so that the peak value of the drain current IDS passing through the main switching element 2 decreases and the output voltage VOUT decreases. Contrarily, when the load increases and the first reference voltage VR also increases, the detected value of the drain current IDS is increased and the on time of the main switching element 2 is extended, so that the peak value of the drain current IDS passing through the main switching element 2 increases and the output voltage VOUT increases. In the switching power supply, PWM control is performed thus in the current mode, so that the output voltage VOUT is stabilized at a predetermined voltage value.

Referring to FIGS. 2 to 5, the drain current IDS passing through the main switching element 2 will be described below. FIGS. 2 to 5 are waveform charts indicating the states of the drain current IDS passing through the main switching element 2.

In FIGS. 2 to 5, Ton is a period during which the main switching element 2 is turned on, IDS is the current waveform of the drain current passing through the main switching element 2 in the period Ton, ILIMIT is the maximum detected current value of the drain current IDS determined by the clamp signal, Td is a detection delay time from the time the comparator 19 generates the signal for determining the timing for turning off the main switching element 2 to the time the main switching element 2 is actually turned off, IDpeak is the maximum current value of the drain current IDS, that is, the peak value of the drain current IDS in each switching period, and IMAX is the maximum permissible current value of the main switching element 2. The relationship between the maximum permissible current value IMAX and the maximum detected current value ILIMIT varies among manufacturers and ILIMIT is substantially set at two thirds of IMAX or below.

FIG. 2 shows the waveform of the drain current IDS in a normal operation when a sufficient time has elapsed and the soft start period TSS has been completed after power-on and the output voltage VOUT is stabilized at the predetermined voltage value.

In FIG. 2, Toff1 is a period during which a regenerated current IFRD passes through the rectifier diode 5 of the energy converter circuit 7 in the off period of the main switching element 2, TBLK is a blanking time, and ILIMR is the detected value of the drain current IDS, that is, the detected current value of the drain current IDS. The absolute value of the detected current value ILIMR is any value not larger than the maximum detected current value ILIMIT. Further, T11, T12, T13, and T14 are switching periods during which the main switching element 2 performs a switching operation. In FIG. 2, the regenerated current IFRD passing in the period Toff1 is indicated by a chain line.

The drain current IDS passing in the period Ton during which the main switching element 2 is turned on is expressed by equation (1) as follows:

IDS=(VIN−VOUT)/L×Ton (1)

The regenerated current IFRD passing through the rectifier diode 5 in the off period of the main switching element 2 is expressed by equation (2) as follows:

IFRD=−VOUT/L×Toff1 (2)

In equations (1) and (2), VIN is the input power supply voltage, VOUT is the output voltage, and L is the inductance value of the switching transformer 1.

According to equation (1), in the period Ton during which the main switching element 2 is turned on, the current waveform of the drain current IDS is inclined according to a voltage difference between the input power supply voltage VIN and the output voltage VOUT when the inductance value L of the switching transformer 1 is kept constant. According to equation (2), in the off period of the main switching element 2, the current waveform of the regenerated current IFRD passing through the rectifier diode 5 is inclined according to the output voltage VOUT.

As shown in FIG. 2, in a normal operation in which the output voltage VOUT is stabilized at the predetermined voltage value, the on period Ton of the main switching element 2 is longer than a minimum on period Tmin determined by the sum of the blanking time TBLK and the detection delay time Td. Thus the drain current IDS is limited by the detected current value ILIMR smaller than the maximum detected current value ILIMIT. For this reason, when the drain current IDS reaches the detected current value ILIMR, the main switching element 2 is turned off after the predetermined detection delay time Td.

As shown in FIG. 2, since the output voltage VOUT is stabilized, the inclination of the current waveform of the drain current IDS and the inclination of the current waveform of the regenerated current IFRD are stabilized without considerably varying among the switching periods T11, T12, T13, and T14.

FIG. 3 shows the waveform of the drain current IDS when the maximum detected current value of the drain current IDS is set at ILIMITss smaller than ILIMIT of a normal operation in the soft start operation TSS at power-on as in a typical switching power supply of the prior art.

In FIG. 3, Toff2 is a period during which the main switching element 2 is turned off, T1, T2, T3, and T4 are switching periods during which the main switching element 2 performs a switching operation, and Is is the initial current value of the drain current IDS in each switching period.

Further, in FIG. 3, the regenerated current IFRD passing in the period Toff2 is indicated by a chain double-dashed line. For comparison, in the switching period T1, the regenerated current IFRD in a normal operation is indicated by a chain line.

Since the output voltage VOUT is small at power-on, the current waveform of the drain current IDS is steeply inclined according to equation (1) in the period Ton during which the main switching element 2 is turned on. According to equation (2), the current waveform of the regenerated current IFRD passing through the rectifier diode 5 is less steeply inclined in the period during which the main switching element 2 is turned off.

As shown in FIG. 3, since the drain current IDS is steeply inclined in the switching period T1, the drain current IDS reaches the maximum detected current value ILIMITss in the blanking period. In the blanking period, however, the main switching element 2 is prohibited from being turned off. Thus the main switching element 2 is turned off after the lapse of the blanking period and the detection delay time Td. In other words, the on period of the main switching element 2 is the minimum on period Tmin=TBLK+Td.

In the period Ton during which the main switching element 2 is turned on, energy is accumulated in the secondary winding 1b of the switching transformer 1. Since the regenerated current IFRD is less steeply inclined, only a part of energy accumulated in the secondary winding 1b is transmitted to the output side of the switching transformer 1 in the period Toff2 during which the main switching element 2 is turned off. Energy not regenerated in the switching period T1 serves as the initial current of the drain current IDS in the switching period T2. When the main switching element 2 is turned on in the presence of the initial current, the current waveform of the drain current IDS is called continuous mode.

Also in the switching period T2, the main switching element 2 is driven in the minimum on period Tmin. Thus the maximum current value of the drain current IDS further increases. In this way, the drain current IDS is not limited by the overcurrent detection value and the main switching element 2 is driven in the minimum on period Tmin so as to increase the initial current value and the peak value of the drain current IDS in each switching period. This phenomenon is called minimum pulse driving.

The following will describe the case where the output voltage VOUT slightly increases in the switching period T3. The output voltage VOUT is gradually increased by energy transmitted from the output side of the switching transformer 1 in each switching period. As a result, in the period Ton during which the main switching element 2 is turned on, the current waveform of the drain current IDS passing through the main switching element 2 is less steeply inclined than in the switching period T2 according to equation (1). Further, in the period Toff2 during which the main switching element 2 is turned off, the current waveform of the regenerated current IFRD passing through the rectifier diode 5 is more steeply inclined than in the switching period T2 according to equation (2). In the switching period T3, the same waveform as the waveform of the regenerated current IFRD in the switching period T2 is indicated by a broken line.

As the output voltage VOUT increases, an increase in the drain current IDS passing through the main switching element 2 slightly decreases. However, it is not possible to prevent an increase in the peak value IDpeak of the drain current IDS.

As a result of the foregoing operation, even when the maximum detected current value of the drain current IDS is set at ILIMITss smaller than ILIMIT in a normal operation, the drain current IDS passing through the main switching element 2 is not lower than the maximum permissible current value IMAX, so that the main switching element 2 may be degraded or broken.

FIG. 4 shows the waveform of the drain current IDS when the blanking time is set at TBLKs shorter than TBLK of a normal operation in the soft start period TSS at power-on.

FIG. 4 shows the case where TBLKs is set at a half of TBLK. In this case, in the switching periods T1, T2, T3, and T4, the current waveforms of the drain current IDS and the regenerated current IFRD are inclined as in FIG. 3.

In FIG. 4, the main switching element 2 is turned off in the period Toff2. Further, the main switching element 2 performs a switching operation in the switching periods T1, T2, T3, and T4. Moreover, Is is the initial current value of the drain current IDS in each switching period.

In FIG. 4, the regenerated current IFRD passing in the period Toff2 is indicated by a chain double-dashed line. For comparison, the waveform of the drain current IDS in FIG. 3 is indicated by a broken line in the switching periods T2, T3, and T4.

As shown in FIG. 4, by shortening the blanking time, the drain current IDS is limited by the maximum detected current value ILIMIT in the switching period T1. Further, even when the initial current value increases and the minimum pulse driving is generated in the switching period T2, an increase “IDpeak-Is” in the drain current IDS is smaller than an increase in the drain current IDS in the switching period T2 of FIG. 3. When the output voltage VOUT gradually increases from the switching period T3, the initial current value decreases. As a result, the peak value IDpeak of the drain current IDS is lower than the peak value IDpeak of the drain current IDS of FIG. 3 and gradually decreases from the switching period T3.

Thus it is possible to prevent the drain current IDS from increasing to at least the maximum permissible current value of the main switching element 2, thereby achieving overcurrent protection for protecting the main switching element 2 from degradation and damage.

From the switching period T3, as the output voltage VOUT increases, the drain current IDS is less steeply inclined and the regenerated current IFRD is more steeply inclined, so that the initial current value decreases. Thus even when the blanking time changes from TBLKs to TBLK, the drain current IDS is limited by the detected current value ILIMR determined by the feedback signal control circuit FB 17 and the on period of the main switching element 2 is longer than the sum of the blanking time TBLK and the detection delay time Td of a normal operation.

FIG. 5 shows the waveform of the drain current IDS when the blanking time is set at TBLKs shorter than TBLK of a normal operation and the maximum detected current value of the drain current IDS is set at ILIMITss smaller than ILIMIT of a normal operation in the soft start period TSS at power-on.

FIG. 5 shows the case where TBLKs is set at a half of TBLK and ILIMITss is set at a half of ILIMIT. In this case, in the switching periods T1, T2, T3, and T4, the current waveforms of the drain current IDS and the regenerated current IFRD are inclined as in FIG. 4.

In FIG. 5, the main switching element 2 is turned off in the period Toff2. Further, the main switching element 2 performs a switching operation in the switching periods T1, T2, T3, and T4. Moreover, Is is the initial current value of the drain current IDS in each switching period.

In FIG. 5, the regenerated current IFRD passing in the period Toff2 is indicated by a chain double-dashed line. For comparison, the waveform of the drain current IDS of FIG. 4 is indicated by a broken line.

As shown in FIG. 5, by shortening the blanking time and reducing the maximum detected current value, the on period of the main switching element 2 in the switching period T1 is set at the minimum on time Tmins=TBLKs +Td. Thus the maximum current value of the drain current IDS in the switching period T1 is smaller than the maximum current value of the drain current IDS in the switching period T1 of FIG. 4. As a result, an increase in the drain current IDS is kept constant from the switching period T2 but the initial current value Is is smaller than the initial current value of the drain current IDS of FIG. 4. Thus the peak value IDpeak of the drain current IDS is lower than the peak value IDpeak of the drain current IDS of FIG. 4 and gradually decreases from the switching period T3.

Moreover, in the soft start period TSS at power-on, the maximum detected current value of the drain current IDS is set smaller than in a normal operation, so that an amount of converted energy per unit time decreases. Thus the output voltage VOUT smoothly rises.

From the switching period T3, as the output voltage VOUT increases, the drain current IDS is less steeply inclined and the regenerated current IFRD is more steeply inclined, so that the initial current value decreases. Thus even when the blanking time changes from TBLKs to TBLK and the maximum detected current value of the drain current IDS changes from ILIMITss to ILIMIT, the drain current IDS is limited by the detected current value ILIMR determined by the feedback signal control circuit FB 17 and the on time of the main switching element 2 is longer than the sum of the blanking time TBLK and the detection delay time Td of a normal operation.

In FIGS. 4 and 5, the blanking time and the maximum detected current value in the soft start period TSS are set at halves of those of a normal operation. The blanking time and the maximum detected current value in the soft start period TSS are not necessarily limited to the time and value of FIGS. 4 and 5.

In FIGS. 4 and 5, the blanking time in the soft start period TSS is set at a half of that of a normal operation by the blanking time adjusting circuit 26. The blanking time adjusting circuit 26 may set the blanking time at the minimum value at the start of the soft start period TSS and gradually increase the blanking time in the soft start period TSS. Further, in this case, the blanking time adjusting circuit 26 may gradually or digitally increase the blanking time in the soft star period TSS. Even with this setting, as has been discussed, the drain current IDS is less steeply inclined, the regenerated current IFRD is more steeply inclined, and the initial current value decreases as the output voltage VOUT increases from the switching period T3, so that the peak value of the drain current IDS decreases. Thus even when the blanking time changes from TBLKs to TBLK, the drain current IDS is limited by the detected current value ILIMR determined by the feedback signal control circuit FB 17 and the on period of the main switching element 2 is longer than the sum of the blanking time TBLK and the detection delay time Td of a normal operation. Further, the blanking time is smoothly shifted to duration necessary for a normal operation after the lapse of the soft start period TSS.

In FIG. 5, the clamping circuit 18 sets the maximum detected current value in the soft start period TSS at a half of that of a normal operation. The clamping circuit 18 may set the voltage level of the clamp signal, that is, the maximum detected current value of the drain current IDS at the minimum value at the start of the soft start period TSS and may gradually increase the voltage level in the soft start period TSS. Moreover, in this case, the clamping circuit 18 may gradually or digitally increase the voltage level of the clamp signal, that is, the maximum detected current value of the drain current IDS in the soft start period TSS. Even with this setting, as has been discussed, the drain current IDS is less steeply inclined, the regenerated current IFRD is more steeply inclined, and the initial current value decreases as the output voltage VOUT increases from the switching period T3, so that the peak value of the drain current IDS decreases. Thus even when the blanking time changes from TBLKs to TBLK and the maximum detected current value of the drain current IDS changes from ILIMITss to ILIMIT, the drain current IDS is limited by the detected current value ILIMR determined by the feedback signal control circuit FB 17 and the on period of the main switching element 2 is longer than the sum of the blanking time TBLK and the detection delay time Td of a normal operation. Further, the maximum detected current value, that is, the overcurrent detection value is smoothly shifted to a level necessary for a normal operation after the lapse of the soft start period TSS. The energy transmitted to the output side of the switching transformer 1 increases with the passage of time, so that the output voltage VOUT reaches the predetermined voltage value and faulty start does not occur after the lapse of the soft start period TSS.

In the first embodiment, the main switching element 2 and the control circuit block 3 are integrated on the same substrate and are mounted into a single package. By configuring the switching power supply with the package in which the main switching element 2 and the control circuit block 3 are mounted, the number of components of the switching power supply can be considerably reduced. Further, since the drain current IDS passing through the main switching element 2 is detected in the package, the detection is less likely to be affected by noise and the like from the outside. Thus the probability of erroneous detection of the drain current IDS decreases with higher safety.

Second Embodiment

The following will describe a second embodiment of the present invention. FIG. 6 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to the second embodiment. In FIG. 6, members corresponding to the members of FIG. 1 are indicated by the same reference numerals as those of FIG. 1 and the explanation thereof is omitted. In the switching power supply, PWM control of current mode is used as a control method of the switching operation of a main switching element as in the first embodiment.

As shown in FIG. 6, an energy converter circuit 7 is a series circuit made up of a coil 27 acting as an energy converter, a smoothing capacitor 6, and a rectifier diode 28. The switching power supply is a chopper step-down switching power supply having an output load of positive polarity. To be specific, one end of the coil 27 is connected to one end of the smoothing capacitor 6, the other end of the smoothing capacitor 6 is connected to the anode of the rectifier diode 28, and the cathode of the rectifier diode 28 is connected to the other end of the coil 27.

A semiconductor device 10 has a DRAIN terminal connected to an input power supply terminal IN. The DRAIN terminal is connected to the input terminal of a main switching element 2. The semiconductor device 10 has a SOURCE terminal connected to the common junction of the coil 27 and the cathode of the rectifier diode 28. The SOURCE terminal is connected to the output terminal of the main switching element 2. Further, the other end of the smoothing capacitor 6 and the anode of the rectifier diode 28 are both connected to a terminal RETURN serving as a reference potential.

In a chopper switching power supply, generally, a fast recovery diode having a short reverse recovery time trr is used as the rectifier diode 28 to reduce a switching loss.

The energy converter circuit 7 converts an input power supply voltage VIN, which has been switched by the main switching element 2, to an output voltage VOUT having a voltage value different from the voltage value of the input power supply voltage VIN. To be specific, in the energy converter circuit 7, energy accumulated in the coil 27 by the switching operation of the main switching element 2 is smoothed by the smoothing capacitor 6, so that the output voltage VOUT is generated.

The switching power supply is different from the first embodiment in the configuration of a control circuit block 3. To be specific, the control circuit block 3 includes a comparator 29 which compares an SS terminal voltage with a reference voltage and generates a comparison signal indicating the comparison result. Further, in the switching power supply, a blanking time adjusting circuit is not provided and a clamping circuit 18 is not connected to an SS terminal. Thus in the switching power supply, a blanking time TBLK and an overcurrent detection value are kept constant.

Moreover, the switching power supply is different from the first embodiment in the configuration of a gate driving circuit 4. To be specific, the gate driving circuit 4 is made up of an N-channel MOS transistor 30, P-channel MOS transistors 31a and 31b, and an OR circuit 32. The P-channel MOS transistors 31a and 31b have the same current drive capability. The P-channel MOS transistor 31b and the N-channel MOS transistor 30 constitute a pre-driver 33, and the common output of the gate driving circuit 4 and the pre-driver 33 is connected to the control terminal of the main switching element 2. One input terminal of the OR circuit 32 and the input terminal of the pre-driver 33 are fed with a switching control signal from a switching control signal generating circuit 20, and the other input terminal of the OR circuit 32 is fed with the comparison signal from the comparator 29. Further, the gate of the P-channel MOS transistor 31a is fed with a signal generated by the OR circuit 32.

The following will describe the operations of the switching power supply configured thus.

When the input power supply voltage VIN is applied from the input power supply terminal IN to the DRAIN terminal connected to the input terminal of the main switching element 2, current is supplied from a regulator 13 of the control circuit block 3 to a power supply capacitor 11 connected to a VDD terminal, so that a VDD terminal voltage increases. The input power supply voltage VIN is a DC voltage (not shown) such as a voltage obtained by rectifying, for example, a commercial AC voltage with a rectifier such as a diode bridge and smoothing the voltage with an input capacitor.

The switch of the regulator 13 is turned on until the VDD terminal voltage reaches a constant voltage, so that current is supplied from the regulator 13 to the VDD terminal. After that, when the VDD terminal voltage reaches at least the constant voltage, the switch of the regulator 13 is turned off, so that the current supply from the regulator 13 to the VDD terminal is stopped and the VDD terminal voltage is kept at a constant potential.

A start/stop circuit 14 turns on the switch of the regulator 13 until the VDD terminal voltage reaches the constant voltage. When the VDD terminal voltage reaches at least the constant voltage, the switch of the regulator 13 is turned off. The start/stop circuit 14 generates a starting signal when the VDD terminal voltage reaches a starting voltage, and the start/stop circuit 14 generates a start/stop signal when the VDD terminal voltage decreases to a start/stop voltage.

When fed with the starting signal from the start/stop circuit 14, a soft start period generating circuit 25 supplies a constant current from a constant current source to a soft start capacitor 12 connected to the SS terminal. Thus the SS terminal voltage increases. A soft start period TSS is set from the time the starting signal is supplied to the time the SS terminal voltage exceeds the reference voltage of the comparator 29. When the SS terminal voltage exceeds the reference voltage of the comparator 29, the logical level of the comparison signal generated by the comparator 29 is shifted to L level.

In the soft start period TSS, the logical level of the comparison signal generated by the comparator 29 is H level. Thus the logical level of a signal supplied from the OR circuit 32 to the gate of the P-channel MOS transistor 31a is also H level and the P-channel MOS transistor 31a is turned off. Therefore, in the soft start period TSS, the P-channel MOS transistor 31b and the N-channel MOS transistor 30 drive the main switching element 2 according to the switching control signal from the switching control signal generating circuit 20.

After the lapse of the soft start period TSS, the logical level of the comparison signal generated by the comparator 29 is L level. Thus the P-channel MOS transistor 31a, the P-channel MOS transistor 31b, and the N-channel MOS transistor 30 drive the main switching element 2 according to the switching control signal from the switching control signal generating circuit 20.

As has been discussed, in the switching power supply, the turn-on drive capability of the gate driving circuit 4 in the soft start period TSS is lower than in a normal operation after the lapse of the soft start period TSS. Thus the turn-on time of the main switching element 2 is longer in the soft start period TSS than in a normal operation.

When the starting signal from the start/stop circuit 14 starts the oscillation of the main switching element 2, that is, the switching operation of the main switching element 2, power is supplied through the SOURCE terminal to the energy converter circuit 7 made up of the coil 27, the smoothing capacitor 6, and the rectifier diode 28, and the output voltage VOUT from the energy converter circuit 7 is applied to a load 8 connected to an output terminal OUT.

The output voltage VOUT is detected by an output voltage detection circuit 9. The output voltage detection circuit 9 generates a feedback signal FB_S indicating the voltage level of the output voltage VOUT. The feedback signal FB_S is supplied to a feedback signal control circuit FB 17 of the control circuit block 3 through an FB terminal.

The feedback signal control circuit FB 17 reduces a first reference voltage VR based on the feedback signal FB_S when a load decreases and the output voltage VOUT increases. Contrarily, the feedback signal control circuit FB 17 increases the first reference voltage VR when the load increases and the output voltage VOUT decreases.

In a normal operation after the lapse of the soft start period TSS, the first reference voltage VR corresponding to the detected value of a drain current IDS serves as the reference voltage of a comparator 19. When the load decreases and the first reference voltage VR also decreases, the detected value of the drain current IDS is reduced and the on time of the main switching element 2 is shortened, so that the peak value of the drain current IDS passing through the main switching element 2 decreases and the output voltage VOUT decreases. Contrarily, when the load increases and the first reference voltage VR also increases, the detected value of the drain current IDS is increased and the on time of the main switching element 2 is extended, so that the peak value of the drain current IDS passing through the main switching element 2 increases and the output voltage VOUT increases. In the switching power supply, PWM control is performed thus in the current mode, so that the output voltage VOUT is stabilized at a predetermined voltage value.

Referring to FIGS. 7 and 8, the drain current IDS passing through the main switching element 2 will be described below. FIGS. 7 and 8 are waveform charts indicating the states of the drain current IDS.

FIGS. 7 and 8 each show the waveform of the drain current IDS passing through the main switching element 2 and the waveform of a regenerated current IFRD passing from the anode to the cathode of the rectifier diode 28, in a normal operation when a sufficient time has elapsed and the soft start period TSS has been completed after power-on and the output voltage VOUT is stabilized at a predetermined voltage value.

In the case of the chopper switching power supply, the on duty of the switching control signal in a normal operation is determined by a voltage difference between the input power supply voltage VIN and the output voltage VOUT. The voltage difference between the input power supply voltage VIN and the output voltage VOUT also determines whether the current waveform of the drain current IDS passing through the main switching element 2 is placed in continuous mode or discontinuous mode.

FIG. 7 shows the waveforms of the drain current IDS and the regenerated current IFRD when the current waveform of the drain current IDS is placed in the discontinuous mode. In FIG. 7, Ton is a period during which the main switching element 2 is turned on, IDS is the current waveform of the drain current passing in the period Ton, Toff1 is a period during which the regenerated current IFRD passes through the rectifier diode 28 of the energy converter circuit 7 in a period during which the main switching element 2 is turned off, IFRD is the current waveform of the regenerated current applied in the period Toff1, IDpeak is the current value of current applied when the main switching element 2 is turned off, and Isp1 is the current value of a spike current component applied when the main switching element 2 is turned on.

In a normal operation, the drain current IDS is limited by a detected current value ILIMR not larger than a maximum detected current value ILIMIT. The maximum detected current value ILIMIT is determined by the clamping circuit 18 and the detected current value ILIMR is determined by the feedback signal control circuit FB 17. The absolute value of the detected current value ILIMR is any value not larger than the maximum detected current value ILIMIT. In a normal operation, when the drain current IDS reaches the detected current value ILIMR, the main switching element 2 is turned off after a predetermined detection delay time Td. At this point, the current value of the drain current IDS reaches IDpeak. In FIG. 7, ILIMIT, ILIMR, and Td are not shown.

By energy accumulated in the coil 27 in the period Ton during which the main switching element 2 is turned on, the regenerated current IFRD passes through a loop of the coil 27, the smoothing capacitor 6, and the rectifier diode 28 in a period during which the main switching element 2 is turned off. The regenerated current IFRD passing through the rectifier diode 28 decreases with a constant inclination from the peak value as large as IDpeak. In the discontinuous mode, energy accumulated in the coil 27 is exhausted before the main switching element 2 is turned on. Thus the regenerated current IFRD is not applied when the main switching element 2 is turned on.

When the main switching element 2 is turned on, current charged in the off period of the main switching element 2 passes as a spike current through a capacitance parasitic on the main switching element 2, the rectifier diode 28, and so on. However, the parasitic capacitance value is no more than several pF and thus the current value Isp1 of the spike current component is much smaller than IDpeak.

FIG. 8 shows the waveforms of the drain current IDS and the regenerated current IFRD when the current waveform of the drain current IDS is placed in the continuous mode. In FIG. 8, Ton is a period during which the main switching element 2 is turned on, IDS is the current waveform of the drain current passing in the period Ton, Toff2 is a period during which the main switching element 2 is turned off, IFRD is the current waveform of the regenerated current passing in the period Toff2, and IDpeak is the current value of current applied when the main switching element 2 is turned off. Isp2 is the current value of the spike current component and Is is the current value of the initial current other than the spike current component out of currents applied when the main switching element 2 is turned on.

In a normal operation, the drain current IDS is limited by the detected current value ILIMR, which is not larger than the maximum detected current value ILIMIT, as in the discontinuous mode. Thus when the drain current IDS reaches the detected current value ILIMR, the main switching element 2 is turned off after the predetermined detection delay time Td. At this point, the current value of the drain current IDS reaches IDpeak. In FIG. 8, ILIMIT, ILIMR, and Td are not shown.

By energy accumulated in the coil 27 in the period Ton during which the main switching element 2 is turned on, the regenerated current IFRD passes through the loop of the coil 27, the smoothing capacitor 6, and the rectifier diode 28 in a period during which the main switching element 2 is turned off. The regenerated current IFRD passing through the rectifier diode 28 decreases with a constant inclination from the peak value as large as IDpeak. In the continuous mode, a forward voltage is applied to the rectifier diode 28 until immediately before the main switching element 2 is subsequently turned on. Thus the regenerated current IFRD is applied also when the main switching element 2 is turned on. The positive current value of the regenerated current IFRD is an initial current value Is of the drain current IDS.

When the main switching element 2 is turned on, the voltage applied to the rectifier diode 28 changes from a forward voltage to a reverse voltage, so that a negative current passes from the cathode to the anode of the rectifier diode 28. The negative current is a reverse recovery current Irr. At this point, the voltage is applied to the rectifier diode 28 through the main switching element 2. In the case of the chopper switching power supply, the rectifier diode 28 and the main switching element 2 are directly connected to each other, so that a current having the same current value as the reverse recovery current Irr passes through the main switching element 2. Further, at this point, current charged in the off period of the main switching element 2 passes through the capacitance parasitic on the main switching element 2, the rectifier diode 28, and so on.

In a flyback switching power supply and the like, a magnetically-coupled transformer is interposed between a rectifier diode and a main switching element and a current having the same current value as the reverse recovery current Irr of the rectifier diode does not pass through the main switching element.

The current value Isp2 of the spike current component generated when the main switching element 2 is turned on is the sum of the capacitance parasitic on the main switching element 2, the rectifier diode 28, and so on, the current value of current charged in the off period of the main switching element 2, and the current value of the reverse recovery current Irr. The current value of the reverse recovery current Irr depends upon the reverse recovery time trr peculiar to the rectifier diode 28 and also considerably depends upon an applied reverse voltage. In other words, the larger the reverse voltage, dV/dt, and dI/dt, that is, the larger the potential change at high speeds, the larger the current value of the reverse recovery current Irr. Further, dI/dt increases with the current value of the forward current having been applied at the application of the reverse voltage, that is, with the initial current value Is. Thus the current value of the reverse recovery current Irr also increases.

As has been discussed, in the continuous mode, the current value of current applied when the main switching element 2 is turned on is the total value of the initial current value Is and the current value Isp2 of the spike current component, and the current value is much larger than the current value Isp1 in the discontinuous mode.

FIG. 9 shows a drain current IDS in a soft start period TSS of a typical chopper switching power supply according to the prior art. FIG. 10 shows the waveform of a drain current IDSS in the soft start period TSS of the switching power supply according to the second embodiment of the present invention.

In FIGS. 9 and 10, Ton is a period during which the main switching element 2 is turned on, IDS is the current waveform of the drain current passing through the main switching element in the period Ton, Toff2 is a period during which the main switching element 2 is turned off, IDpeak is the maximum current value of the drain current IDS, that is, the peak value of the drain current IDS in each switching period, Is is the initial current value of the drain current IDS in each switching period, Isp2 is the current value of the spike current component in each switching period, and IMAX is the maximum permissible current value of the main switching element. Further, T1, T2, T3, and T4 are switching periods during which the main switching element performs a switching operation. Moreover, in FIGS. 9 and 10, the regenerated current IFRD passing from the anode to the cathode of the rectifier diode in the period Toff2 is indicated by a chain double-dashed line.

As shown in FIG. 9, the input power supply voltage VIN is high and the output voltage VOUT is nearly zero at power-on. Thus in the period Ton during which the main switching element is turned on, the current waveform of the drain current IDS is steeply inclined. In the period Toff2 during which the main switching element is turned off, the current waveform of the regenerated current IFRD passing through the rectifier diode is less steeply inclined. Thus at power-on, the current waveform of the drain current IDS passing through the main switching element is placed in the continuous mode. For this reason, even when the on duty of the main switching element is minimized or the overcurrent detection value is suppressed as in the typical switching power supply of the prior art, minimum pulse driving is repeated in the switching periods T1 and T2 as shown in FIG. 9, so that the initial current value Is and the peak value IDpeak of the drain current IDS increase.

When the main switching element is turned on, the voltage applied to the rectifier diode changes from a forward voltage to a reverse voltage, so that the reverse recovery current Irr passes through the rectifier diode and the spike current passes through the main switching element. The spike current is the sum of the capacitance parasitic on the main switching element, the rectifier diode, and so on, the current charged in the off period of the main switching element, and the reverse recovery current Irr. At power-on, the initial current value Is of the drain current IDS increases in each switching period, so that the current value Isp2 of the spike current component also increases in each switching period.

Thus at power-on, the initial current value Is of the drain current IDS and the current value Isp2 of the spike current component increase in each switching period. Further, a rate of increase in the current value Isp2 of the spike current component is larger than a rate of increase in the peak value IDpeak of the drain current IDS. As a result, in the typical switching power supply of the prior art, a current value obtained by adding the current value Isp 2 of the spike current component to the initial current value Is is larger than the peak value IDpeak of the drain current IDS at power-on as shown in FIG. 9.

The following will describe the case where the output voltage VOUT slightly increases in the switching period T3. The output voltage VOUT is gradually increased by energy transmitted from the output side of the coil in each switching period. As a result, in the period Ton during which the main switching element is turned on, the current waveform of the drain current IDS passing through the main switching element is less steeply inclined than in the switching period T2. In the period Toff2 during which the main switching element is turned off, the current waveform of the regenerated current IFRD passing through the rectifier diode is more steeply inclined than in the switching period T2. In the switching period T3, the same waveform as the waveform of the regenerated current IFRD in the switching period T2 is indicated by a broken line.

In this way, as the output voltage VOUT increases, an increase in the drain current IDS passing through the main switching element slightly decreases. However, it is not possible to prevent an increase in the initial current value Is of the drain current IDS and the current value Isp2 of the spike current component.

As a result of the foregoing operation, even when the on duty of the main switching element is minimized or the overcurrent detection value is suppressed as in the typical switching power supply of the prior art, the current value obtained by adding the current value Isp2 of the spike current component to the initial current value Is is not smaller than the maximum permissible current value IMAX as shown in FIG. 9, so that the main switching element may be degraded or broken.

In contrast to the prior art, in the switching power supply of the second embodiment, the main switching element 2 is turned on by the current drive capability of the two P-channel MOS transistors 31a and 31b in a normal operation and the main switching element 2 is turned on only by the current drive capability of the P-channel MOS transistor 31b in the soft start period TSS at power-on, so that the turn-on drive capability of the gate driving circuit 4 is reduced by half in the soft start period TSS. As a result, the turn-on time of the main switching element 2 in the soft start period TSS is longer than the turn-on time in a normal operation and dV/dt and dI/dt are small, thereby suppressing the reverse recovery current Irr and the current value Isp2 of the spike current component.

Thus it is possible to suppress the initial current value Is of the drain current IDS and the current value Isp2 of the spike current component which increase in each switching period, so that as shown in FIG. 10, it is possible to prevent the current value obtained by adding the current value Isp2 of the spike current component to the initial current value Is from increasing to at least the maximum permissible current value IMAX of the main switching element 2. It is therefore possible to achieve overcurrent protection for protecting the main switching element 2 from degradation and damage.

In the second embodiment, the turn-on drive capability of the gate driving circuit in the soft start period is reduced by half from that of a normal operation. It is not necessary to limit the turn-on drive capability of the gate driving circuit in the soft start period to that of the second embodiment.

Third Embodiment

The following will describe a third embodiment of the present invention. FIG. 11 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to the third embodiment. In FIG. 11, members corresponding to the members of FIGS. 1 and 6 are indicated by the same reference numerals as those of FIGS. 1 and 6 and the explanation thereof is omitted.

As shown in FIG. 11, the switching power supply is different from the second embodiment in that a control circuit block 3 includes a blanking time adjusting circuit 26 and a clamping circuit 18 is connected to an SS terminal as in the first embodiment.

With this configuration, in a soft start period TSS, it is possible to reduce the turn-on drive capability of a gate driving circuit 4, obtain a shorter blanking time than in a normal operation, and reduce the maximum detected current value of a drain current IDS, which passes through a main switching element 2, as compared with in a normal operation.

Thus even in the case of minimum pulse driving at power-on, it is possible to reduce the current value of current applied when the main switching element 2 is turned on and the current value of the drain current IDS applied when the main switching element 2 is turned off. Thus it is possible to prevent the current value of current passing through the main switching element 2 from increasing to at least the maximum permissible current value of the main switching element 2, thereby achieving overcurrent protection for protecting the main switching element 2 from degradation and damage with higher safety.

Moreover, in the soft start period TSS at power-on, the maximum detected current value of the drain current IDS is set smaller than in a normal operation, so that an amount of energy conversion per unit time decreases. Thus an output voltage VOUT smoothly rises.

As has been discussed in the first embodiment, the blanking time adjusting circuit 26 may gradually increase the blanking time in the soft start period TSS at power-on, from the minimum value at the start of the soft start period TSS. In this case, the blanking time adjusting circuit 26 may gradually or digitally increase the blanking time in the soft star period TSS. With this operation, the blanking time is smoothly shifted to duration necessary for a normal operation after the lapse of the soft start period TSS.

Further, as has been discussed in the first embodiment, the clamping circuit 18 may gradually increase the voltage level of a clamp signal, that is, the maximum detected current value of the drain current IDS in the soft start period TSS at power-on, from the minimum value at the start of the soft start period TSS. In this case, the clamping circuit 18 may gradually or digitally increase the voltage level of the clamp signal, that is, the maximum detected current value of the drain current IDS in the soft start period TSS. With this operation, the maximum detected current value, that is, the overcurrent detection value is smoothly shifted to a level necessary for a normal operation after the lapse of the soft start period TSS. Moreover, energy transmitted to the output side of a coil 27 increases with the passage of time, so that the output voltage VOUT reaches a predetermined voltage value and faulty start does not occur after the lapse of the soft start period TSS.

Fourth Embodiment

The following will describe a fourth embodiment of the present invention. A switching power supply and a semiconductor device of the fourth embodiment are different from the first to third embodiments in the configuration of a soft start period generating circuit 25. FIG. 12 shows an example of the soft start period generating circuit 25 included in the switching power supply and the semiconductor device according to the fourth embodiment.

As shown in FIG. 12, the soft start period generating circuit 25 includes a first constant current source 34 which supplies a constant current ILS(SS1) to a soft start capacitor (not shown) connected to an SS terminal, and a second constant current source 35 which draws current at a constant current ILS(SS2) from the soft start capacitor (not shown) connected to the SS terminal.

The soft start period generating circuit 25 further includes a comparator 36 and a comparator 37. The inverting input terminal of the comparator 36 is connected to the SS terminal and the non-inverting input terminal of the comparator 36 is fed with a predetermined reference voltage VLS2. The inverting input terminal of the comparator 37 is connected to the SS terminal and the non-inverting input terminal of the comparator 37 is fed with a predetermined reference voltage VLS1. The reference voltage VLS1 is lower than the reference voltage VLS2 (reference voltage VLS1<reference voltage VLS2).

The soft start period generating circuit 25 further includes an inverter 38 which inverts a signal from the common output of the comparator 36 and the comparator 37, a counter circuit 39 which is fed with a signal from the common output of the comparator 36 and the comparator 37, and a third constant current source 40 which supplies a constant current ILS(SS3) to the soft start capacitor (not shown) connected to the SS terminal.

The soft start period generating circuit 25 further includes a switch 41 which is interposed between the first constant current source 34 and the SS terminal in a state controlled by a signal from a start/stop circuit (not shown), a switch 42 which is interposed between the switch 41 and the SS terminal in a state controlled by a signal from the common output of the comparator 36 and the comparator 37, and a switch 43 which is interposed between the second constant current source 35 and the SS terminal in a state controlled by a signal from the inverter 38.

The soft start period generating circuit 25 further includes a switch 44 placed in a state controlled by a signal from the common output of the comparator 36 and the comparator 37. The switch 44 determines power supply to the comparator 36.

The soft start period generating circuit 25 further includes a switch 45 placed in a state controlled by a signal from the inverter 38. The switch 45 determines power supply to the comparator 37.

The soft start period generating circuit 25 further includes a switch 46 which is interposed between the third constant current source 40 and the SS terminal in a state controlled by a signal SS_END generated by the counter circuit 39. The signal SS_END generated by the counter circuit 39 indicates the end of a soft start period.

In the soft start period generating circuit 25, the two constant current sources 34 and 35 charge and discharge the soft start capacitor (not shown). The two comparators 36 and 37 detect the voltage level of the soft start capacitor (not shown), that is, the upper limit of an SS terminal voltage by the reference voltage VLS2 and detect the lower limit by the reference voltage VLS1. The four switches 42, 43, 44, and 45 switch charge and discharge of the soft start capacitor (not shown) based on the signal generated by the two comparators 36 and 37. The counter circuit 39 counts up a count value based on the signal generated by the two comparators 36 and 37, and generates, when the count value reaches a predetermined value, the signal SS_END indicating the end of the soft start period.

Before a starting signal is supplied from the start/stop circuit (not shown) to each block, the SS terminal voltage is fixed at the same potential as a SOURCE terminal voltage. When the starting signal is supplied from the start/stop circuit to each block, the SS terminal voltage is not fixed (not shown).

When the starting signal is supplied from the start/stop circuit (not shown) to each block, the switch 41 is turned on by the starting signal from the start/stop circuit. At this point, the SS terminal voltage is lower than VLS1 and VLS2. Further, at this point, the switches 44 and 45 are both turned on. Thus a signal having a high logic level is generated from the comparators 36 and 37 at this point.

The switches 42 and 44 are turned on in a period during which a signal having a high logic level is supplied from the common output of the comparator 36 and the comparator 37, and the switches 42 and 44 are turned off in a period during which a signal having a low logic level is supplied. The switches 43 and 45 are turned on in the period during which the signal having a low logic level is supplied from the common output of the comparator 36 and the comparator 37, and the switches 43 and 45 are turned off in the period during which the signal having a high logic level is supplied.

Thus when the starting signal is supplied to each block, the switch 44 is kept turned on and the switch 45 is turned off, so that the comparator 36 is fed with an internal circuit power supply voltage. However, the comparator 37 is not fed with the internal circuit power supply voltage. The internal circuit power supply voltage is the power supply voltage of a control circuit block 3. With this operation, the comparator 37 stops operating and the signal having a high logic level is generated by the comparator 36 and is supplied from the common output of the comparator 36 and the comparator 37. As a result, the constant current ILS(SS1) from the first constant current source 34 is supplied to the soft start capacitor (not shown) through the SS terminal. Further, the counter circuit 39 at this point receives the signal having a high logic level.

When the soft start capacitor (not shown) is charged by the constant current ILS(SS1) and the SS terminal voltage reaches VLS2, the comparator 36 generates the signal having a low logic level. As a result, the switch 42 is turned off and the supply of the constant current ILS(SS1) from the first constant current source 34 to the soft start capacitor (not shown) is stopped. After that, the switch 43 is turned on and the second constant current source 35 discharges the soft start capacitor (not shown) at the constant current ILS(SS2). Since the switch 44 is turned off and the switch 45 is turned on at this point, the comparator 36 stops operating and the comparator 37 starts operating to generate the signal having a low logic level. The counter circuit 39 at this point receives the signal having a low logic level.

When the soft start capacitor (not shown) is discharged by the constant current ILS(SS2) and the SS terminal voltage decreases to VLS1, the comparator 37 generates the signal having a high logic level. As a result, the switch 43 is turned off and the discharge of the soft start capacitor (not shown) by the second constant current source 35 is stopped. After that, the switch 42 is turned on and the supply of the constant current ILS(SS1) from the first constant current source 34 to the soft start capacitor (not shown) is started. Since the switch 45 is turned off and the switch 44 is turned on at this point, the comparator 37 stops operating and the comparator 36 starts operating to generate the signal having a high logic level. The counter circuit 39 at this point receives the signal having a high logic level and counts up the count value.

When the count value of the counter circuit 39 reaches the predetermined value after the series of operations is repeated several times, the counter circuit 39 generates the signal SS_END indicating the end of the soft start period. The SS_END signal turns on the switch 46, so that the constant current ILS(SS3) from the third constant current source 40 is supplied to the soft start capacitor (not shown). When the SS_END signal is generated, the switches 44 and 45 are both turned off and the comparators 36 and 37 stop operating (not shown). As a result, after the soft start period is completed, the SS terminal voltage increases to the internal circuit power supply voltage and is fixed at the voltage.

By using the soft start period generating circuit 25, the soft start period can be determined by a constant current value, the capacitance value of the soft start capacitor, and the count value of the counter circuit. Thus it is possible to reduce the capacitance value of the soft start capacitor externally provided on the semiconductor device.

The counter circuit 39 may generate a signal at a voltage level corresponding to the count value. Thus an overcurrent detection value determined by a clamping circuit can be gradually increased in the soft start period or a blanking time can be gradually increased by a blanking time adjusting circuit in the soft start period.

Fifth Embodiment

The following will describe a fifth embodiment of the present invention. FIG. 13 is a circuit diagram showing an example of a switching power supply and a semiconductor device according to the fifth embodiment. In FIG. 13, members corresponding to the members of FIGS. 1, 6, and 11 are indicated by the same reference numerals as those of FIGS. 1, 6, and 11 and the explanation thereof is omitted.

As shown in FIG. 13, the switching power supply is different from the first to third embodiments in a configuration for detecting a drain current passing through a main switching element 2 and a configuration for preventing the main switching element 2 from being erroneously turned off by a spike current. Further, the switching power supply is different from the first to third embodiments in that the oscillation of the main switching element 2 is started when a signal for determining timing for starting the oscillation of the main switching element 2 is supplied to a semiconductor device 10, and the oscillation of the main switching element 2 is stopped when a signal for determining timing for stopping the oscillation of the main switching element 2 is supplied to the semiconductor device 10.

First, the configuration for detecting the drain current in the switching power supply will be described below. In the switching power supplies of the first to third embodiments, the drain current detection circuit 16 detects a drain current passing through the main switching element 2 based on the on voltage of the main switching element 2, whereas in the fifth embodiment, a drain current detection circuit 16 of the switching power supply is a series circuit made up of a sub-switching element 47 and a resistor 48 fed with current passing through the sub-switching element 47, and the drain current detection circuit 16 is connected in parallel with the main switching element 2. To be specific, the input terminal of the sub-switching element 47 is connected to the input terminal of the main switching element 2 and the output terminal of the sub-switching element 47 is connected to the output terminal of the main switching element 2 via the resistor 48. The control terminal of the sub-switching element 47 is connected to the control terminal of the main switching element 2, and a gate driving circuit 4 drives the sub-switching element 47 and the main switching element 2 in a shared manner. The sub-switching element 47 is fed with current having a current value smaller than the current value of current passing through the main switching element 2, with a constant ratio relative to the current value of current passing through the main switching element 2.

The drain current detection circuit 16 configured thus generates voltage across the resistor 48 so as to have a voltage value corresponding to the current value of current passing through the sub-switching element 47. The voltage generated across the resistor 48 is supplied to a comparator 19 as an element current detection signal indicating the current level of a drain current IDS.

In the configuration for detecting the drain current based on the on voltage of the main switching element 2 as in the first to third embodiments, the drain current cannot be accurately detected for a certain period of time after the main switching element 2 is turned on. Generally, the drain current cannot be accurately detected for several hundreds nsec. In the fifth embodiment, with the configuration for detecting the drain current passing through the main switching element 2 based on current passing through the resistor 48, the drain current can be reliably and accurately detected even immediately after the main switching element 2 is turned on.

The configuration for detecting the drain current is not limited to the switching power supply of the fifth embodiment and is also applicable to the switching power supplies of the other embodiments.

The following will describe the configuration for preventing the main switching element 2 from being erroneously turned off by the spike current in the switching power supply. In the switching power supplies according to the first to third embodiments, the supply of the element current detection signal from the drain current detection circuit 16 to the comparator 19 is prevented by the on-time blanking pulse signal BLK from the blanking period generating circuit 23. In the switching power supply of the fifth embodiment, the comparator 19 is connected to a switching control signal generating circuit 20 via an AND circuit 49. One input terminal of the AND circuit 49 is fed with a comparison signal from the comparator 19 and the other input terminal of the AND circuit 49 is fed with an on-time blanking pulse signal BLK from a blanking period generating circuit 23. To be specific, the blanking period generating circuit 23 supplies a signal having a low logic level to the AND circuit 49 in a blanking period, so that the comparison signal from the comparator 19 is disabled. Thus in the blanking period, the main switching element 2 is prohibited from being turned off.

The configuration for preventing the main switching element 2 from being erroneously turned off by the spike current is not limited to the switching power supply of the fifth embodiment and is also applicable to the switching power supplies of the other embodiments.

The following will describe a configuration for controlling the start and stop of oscillation of the main switching element 2 in the switching power supply. The switching power supply includes an input power supply voltage detection circuit 50, which is connected to an input power supply terminal IN, outside the semiconductor device 10. The input power supply voltage detection circuit 50 is an example of an external starting signal generating circuit. Further, outside the semiconductor device 10 in the switching power supply, a soft start capacitor 12 is connected to an SS terminal and a switch 51 for starting and stopping oscillation is also connected to the SS terminal. The SS terminal also acts as an external starting terminal fed with the signal for determining timing for starting/stopping the oscillation of the switching element 2. The switch 51 is connected between the SS terminal and a SOURCE terminal in a state controlled by a signal from the input power supply voltage detection circuit 50. In this case, the voltage of the soft start capacitor 12 determines not only the end of a soft start period but also the timing for starting/stopping the oscillation of the main switching element 2. Further, a comparator 52 for starting/stopping oscillation is added to a control circuit block 3 included in the semiconductor device 10. One input terminal of the comparator 52 is connected to the SS terminal and the other input terminal of the comparator 52 is fed with a predetermined reference voltage. The comparator 52 compares the voltage of the soft start capacitor 12, that is, an SS terminal voltage and the reference voltage, and generates a signal indicating the comparison result. This signal is supplied to the input terminal of a NAND circuit 22 of the switching control signal generating circuit 20 instead of a starting signal and a start/stop signal which are generated by a start/stop circuit 14.

When the main switching element 2 is forcibly turned off, the switch 51 is turned on. Thus the SS terminal voltage is at the same potential as a SOURCE terminal voltage, so that a signal having a low logic level is supplied from the comparator 52 to the NAND circuit 22 and the main switching element 2 is kept turned off. Even when the main switching element 2 is turned off, an input power supply voltage VIN is applied to a DRAIN terminal and thus the power supply voltage of the control circuit block 3 is kept at a starting voltage or higher.

When the switch 51 is turned off, the soft start capacitor 12 is charged by the constant current source of a soft start period generating circuit 25, so that the SS terminal voltage increases. When the SS terminal voltage is higher than the reference voltage of the comparator 52, a signal having a high logic level is supplied from the comparator 52 to the NAND circuit 22. As a result, the main switching element 2 starts oscillation.

In this way, the switching power supply can control the start and stop of oscillation of the main switching element by using the signal supplied to the semiconductor device 10. Further, even when the oscillation of the main switching element 2 is stopped by the signal supplied to the semiconductor device 10, the internal circuit power supply voltage of the semiconductor device 10 is kept constant. Thus the switching power supply can achieve restart without causing a delay time, that is, the start of oscillation of the main switching element 2 without causing a delay time.

The switching power supply further includes the input power supply voltage detection circuit 50 which detects the input power supply voltage VIN and generates, when the input power supply voltage VIN reaches a predetermined value, an external starting signal for turning off the switch 51. The semiconductor device 10 has an internal circuit power supply voltage of about 10 V. Thus when the input power supply voltage VIN is 10 V or higher at power-on, the power supply voltage is supplied to each block of the control circuit block 3 and the semiconductor device 10 becomes operable. The input power supply voltage detection circuit 50 has a predetermined value set at a voltage value not smaller than the internal circuit power supply voltage of the semiconductor device 10, so that the main switching element can start oscillation without causing a delay time when the input power supply voltage VIN reaches the predetermined value.

The configuration for controlling the start and stop of oscillation of the main switching element 2 by the signal supplied to the semiconductor device 10 is not limited to the switching power supply of the fifth embodiment but is also applicable to the switching power supplies of the other embodiments. In the foregoing explanation, the soft start period generating circuit 25 is made up of the constant current source and the switch. The soft start period generating circuit 25 may be configured as shown in FIG. 12. In this case, the reference voltage of the comparator 52 for starting/stopping oscillation is set at a voltage not higher than a reference voltage VLS1 of a comparator 37 of the soft start period generating circuit 25.

As has been discussed, in the switching power supply, the external starting terminal is connected to the external soft start capacitor 12 and the control circuit block 3 determines the timing for starting the oscillation of the main switching element 2 based on the voltage of the external capacitor 12 having been charged by the soft start period generating circuit 25.

In the switching power supply configured thus, the SS terminal acting as the external starting terminal and the connection terminal of the external soft start capacitor 12 are shared, thereby reducing the number of terminals of the semiconductor device 10. Even when the external starting terminal and the connection terminal of the external soft start capacitor 12 are shared, the internal circuit power supply voltage is kept constant by a regulator 13 based on the input power supply voltage VIN. Thus the supply of the power supply voltage to the control circuit block 3 can be started regardless of the timing for starting the oscillation of the main switching element 2. It is therefore possible to shorten a delay time from the time the signal to be supplied to the external starting terminal is generated to the time the main switching element 2 actually starts oscillation.

Although only some exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

Number	Date	Country	Kind
2008-321688	Dec 2008	JP	national
2009-186183	Aug 2009	JP	national

SEMICONDUCTOR LASER APPARATUS

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